coreboot May 2012

coreboot@coreboot.org

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287 discussions

Patch set updated for coreboot: 2af8cea Fix printk types in SPI flash drivers
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1041 -gerrit commit 2af8cea9fd41eecf0bbddf2579d7ea9dada5dad3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 14 13:52:32 2012 -0700 Fix printk types in SPI flash drivers - use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/eon.c | 2 +- src/drivers/spi/macronix.c | 6 ++++-- src/drivers/spi/spansion.c | 3 ++- src/drivers/spi/sst.c | 2 +- src/drivers/spi/stmicro.c | 3 ++- src/drivers/spi/winbond.c | 6 +++--- 6 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 4056953..b7c0630 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -86,7 +86,7 @@ static int eon_write(struct spi_flash *flash, cmd[3] = byte_addr; printk(BIOS_SPEW, - "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 130e746..84e79ef 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -141,7 +141,8 @@ static int macronix_write(struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); @@ -165,7 +166,8 @@ static int macronix_write(struct spi_flash *flash, byte_addr = 0; } - printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @ 0x%lx\n", + printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @" + " 0x%x\n", len, offset - len); spi_release_bus(flash->spi); diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index a4f370a..5479cae 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -162,7 +162,8 @@ static int spansion_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index c5bec12..3ca5563 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -194,7 +194,7 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) ret = sst_byte_write(flash, offset, buf + actual); done: - printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%lx\n", + printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%x\n", ret ? "failure" : "success", len, offset - actual); spi_release_bus(flash->spi); diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 8cbdad5..9322c06 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -163,7 +163,8 @@ static int stmicro_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 65818d5..7b6d105 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -130,8 +130,8 @@ static int winbond_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n", - buf + actual, + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); @@ -155,7 +155,7 @@ static int winbond_write(struct spi_flash *flash, byte_addr = 0; } - printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%lx\n", + printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%x\n", len, offset - len); ret = 0;

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New patch to review for coreboot: 88a1ccf nvramtool: use C99 PRIx64 / PRId64 for uint64_t variables
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1053 -gerrit commit 88a1ccfa55bad83429c09acdb3cb6e2aa84cb03e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 24 13:36:30 2012 -0700 nvramtool: use C99 PRIx64 / PRId64 for uint64_t variables In printf/printk, using %lld or %ld for uint64_t will warn on either 64bit or 32bit machines. However, C99 defines PRIx64 / PRId64 to provide the right modifiers for printing uint64_t variables. Use them instead. Change-Id: I68df5d069a1e99d1a75885173ddfd7815197afea Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/nvramtool/lbtable.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c index 71c3244..83597e4 100644 --- a/util/nvramtool/lbtable.c +++ b/util/nvramtool/lbtable.c @@ -29,6 +29,8 @@ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. \*****************************************************************************/ +#include <stdint.h> +#include <inttypes.h> #include <arpa/inet.h> #include <string.h> #include <sys/mman.h> @@ -655,10 +657,10 @@ static void memory_print_fn(const struct lb_record *rec) start = unpack_lb64(ranges[i].start); end = start + size - 1; printf("%s memory:\n" - " from physical addresses 0x%016llx to 0x%016llx\n" - " size is 0x%016llx bytes (%lld in decimal)\n", - mem_type, start, end, size, - (unsigned long long)size); + " from physical addresses 0x%016" PRIx64 + " to 0x%016" PRIx64 "\n size is 0x%016" PRIx64 + " bytes (%" PRId64 " in decimal)\n", + mem_type, start, end, size, size); if (++i >= entries) break;

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Patch set updated for coreboot: c960958 Fix size_t for certain versions of GCC
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1040 -gerrit commit c960958a82b43dc4401d8f300e0d90daefc9341f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 14 13:21:08 2012 -0700 Fix size_t for certain versions of GCC When compiling coreboot with the latest ChromeOS toolchain, GCC complains that some printk calls use %zu in connection with size_t types since it resolves the typedefs to long unsigned int. The problem is solved by using the GCC built-in __SIZE_TYPE__ if it exists and define __SIZE_TYPE__ to long unsigned int otherwise. Change-Id: I449c3d385b5633a05e57204704e981de6e017b86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/stddef.h | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h index e4fc019..a6c3fc6 100644 --- a/src/arch/x86/include/stddef.h +++ b/src/arch/x86/include/stddef.h @@ -2,7 +2,10 @@ #define I386_STDDEF_H typedef long ptrdiff_t; -typedef unsigned long size_t; +#ifndef __SIZE_TYPE__ +#define __SIZE_TYPE__ unsigned long +#endif +typedef __SIZE_TYPE__ size_t; typedef long ssize_t; typedef int wchar_t;

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Patch merged into coreboot/master: b972fec Add EM100 mode to Intel Firmware Descriptor tool
by gerrit＠coreboot.org 24 May '12

24 May '12

the following patch was just integrated into master: commit b972fecf8b37384fa75de7e5d1e33827fce8b675 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 15:53:43 2012 -0700 Add EM100 mode to Intel Firmware Descriptor tool To avoid having two copies for every firmware descriptor (one for EM100 use and one for real SPI flash use), add an EM100 mode to ifdtool that allows to "dumb down" a fast image to the settings required for the EM100 to work. Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu May 24 10:41:49 2012, giving +1 See http://review.coreboot.org/1039 for details. -gerrit

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Patch merged into coreboot/master: 813532b chromeos: Fix compilation of coreboot-utils package
by gerrit＠coreboot.org 24 May '12

24 May '12

the following patch was just integrated into master: commit 813532b8352bd643fb507c472d518fafebf1edfe Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 12:58:11 2012 -0700 chromeos: Fix compilation of coreboot-utils package The ChromeOS build system provides a set of CXXFLAGS, however those do not contain -DCOMPACT. This breaks the compilation of cbfstool in coreboot-utils. This fix overrides CXXFLAGS so that coreboot-utils compiles again. Change-Id: If9495bdd815fe2cdaeba5386afa953558742467b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu May 24 10:27:35 2012, giving +1 See http://review.coreboot.org/1038 for details. -gerrit

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Patch merged into coreboot/master: cb5e566 Converted the FRAMEBUFFER_VESA_MODE to a choice.
by gerrit＠coreboot.org 24 May '12

24 May '12

the following patch was just integrated into master: commit cb5e566eb996dac15b34d56dc4982d8c094260ac Author: Steve Goodrich <steve.goodrich(a)se-eng.com> Date: Fri May 18 11:18:47 2012 -0600 Converted the FRAMEBUFFER_VESA_MODE to a choice. Being a diligent soul, I changed the "enter a numeric value for the mode you want" option to a choice of common modes. New modes can be added quite easily. Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a Signed-off-by: Steve Goodrich <steve.goodrich(a)se-eng.com> See http://review.coreboot.org/1036 for details. -gerrit

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Patch merged into coreboot/master: b071aa2 abuild: Disable abuild-level parallelism for now
by gerrit＠coreboot.org 24 May '12

24 May '12

the following patch was just integrated into master: commit b071aa230fe252af638aed7d0bfc979cb914b93e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon May 21 20:10:04 2012 +0200 abuild: Disable abuild-level parallelism for now It still failed because make touches files it isn't supposed to touch. Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu May 24 18:09:17 2012, giving +2 See http://review.coreboot.org/1037 for details. -gerrit

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Patch merged into coreboot/master: 6cf94df cbtypes.h: Unify cbtypes.h used in AMD board's code
by gerrit＠coreboot.org 24 May '12

24 May '12

the following patch was just integrated into master: commit 6cf94dfec7b4ac5cdb3716ae45726a5fa8ea0235 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 21 23:47:56 2012 +0530 cbtypes.h: Unify cbtypes.h used in AMD board's code Remove all the repeated sections of code in cbtypes.h and place it in a common location. Add include dir in vendor code's Makefile. Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Apr 26 18:54:23 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu May 24 17:38:41 2012, giving +2 See http://review.coreboot.org/912 for details. -gerrit

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Patch set updated for coreboot: d75af2f Sandybridge: Fix MRC cache calculation
by Patrick Georgi 24 May '12

24 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1046 -gerrit commit d75af2fac06191f07b91fdad5f61fa936deebb2a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:21:10 2012 -0700 Sandybridge: Fix MRC cache calculation The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/mrccache.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 5c4c382..aad2b91 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -65,8 +65,8 @@ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { u8 *mrc_region; u32 region_size; - u32 *data; #ifdef USE_FDT_FMAP_FOR_MRC_CACHE + u32 *data; const struct fdt_header *fdt_header; const struct fdt_property *fdtp; int offset, len; @@ -114,10 +114,8 @@ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) region_size = fdt32_to_cpu(data[1]); mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); #else - data = (u32 *)((void *)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION + 12)); - region_size = CONFIG_MRC_CACHE_SIZE; - mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + be32_to_cpu(data[0])); + mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); #endif *mrc_region_ptr = (struct mrc_data_container *)mrc_region;

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Patch set updated for coreboot: d03766d Drop config variable CPU_MODEL_INDEX
by Patrick Georgi 24 May '12

24 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1047 -gerrit commit d03766d8bac5f99128d9c8a0adbc2ef7cb5e71ba Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 16:30:54 2012 -0700 Drop config variable CPU_MODEL_INDEX It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs and the code can easily be changed to not rely on any Kconfig magic. Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/model_206ax/Kconfig | 8 -------- src/cpu/intel/model_206ax/acpi.c | 11 ++--------- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c11f21a..d2d4c73 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -36,18 +36,10 @@ if CPU_INTEL_MODEL_206AX config CPU_MODEL_NAME string default "Intel SandyBridge CPU" - - config CPU_MODEL_INDEX - hex - default 0x2a endif if CPU_INTEL_MODEL_306AX config CPU_MODEL_NAME string default "Intel IvyBridge CPU" - - config CPU_MODEL_INDEX - hex - default 0x3a endif diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 1a8ceb7..6153174 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -44,15 +44,8 @@ static int get_cores_per_package(void) if (c.x86 != 6) return 1; - switch (c.x86_model) { - case CONFIG_CPU_MODEL_INDEX: - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - break; - default: - cores = (cpuid_ebx(1) >> 16) & 0xff; - break; - } + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; return cores; }

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coreboot May 2012