I own an Acer Aspire VN7-572G and have not been impressed with its OEM
firmware. After discovering that it does not utilise Intel's Boot Guard
technology, that several Skylake and Kabylake laptops (it has a Skylake
chip, but I read that the platforms are similar) have received successful
coreboot ports and reading the porting guide on the wiki, I figured that I
could give porting coreboot to my laptop a shot.
When I was done, I figured that I had an image that might boot so I flashed
it to my laptop with a Raspberry Pi and a SOIC clip. However, here's what
a) It powers on quietly, as expected;
b) The backlight and power LED light up;
c) The fans spin up to high and then it stays that way. It does nothing
else. The display is dark too.
After 15 minutes and a second attempt, I figured that I could no longer
blame anything on a long first boot-up and gave up and flashed back to
Now, in all honesty I should have tried first without cleaning Intel ME but
I find it so much more likely that I did something wrong than that cleaning
ME was the sole problem.
Can anyone advise me on how to continue? My code is here:
Could a Coreboot Coverity admin please re-run the scan against master?
Looks like the last analyzed version was from Sep 24, 2019. I would like
to see what AGESA issues remain.
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Mailing list etiquette:
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Need some guidance. Please read.
I am porting coreboot for a "Broadwell D 1519" based motherboard which has both Memory Down as well as 2 DIMM slots. Hence, I built an image for Facebook Watson since its the closest mainboard with no code changes. The call from FSP_FSP_INIT never returns to the ChipsetFspReturnPoint( ). Probably something crashed inside the FSP or something else.
This is possibly happening because I have passed no information regarding the RAM chips (down or DIMM) from romstage_fsp_rt_buffer_callback(). I have following 2 questions :
1. How can I see the default values for FSP UDP structure, so that I get to know what I need to modify? BCT tool does not dump that info.
2. In intel/soc/fsp_broadwell/ , the save_dimm_info() is done after FSP_FSP_INIT returns. Shouldn't the SPD details have been fetched before and passed to the FSP_FSP_INIT, as it is this API that handles the memory init.
This is to continue the discussion from the coreboot leadership meeting. Thunderbolt devices are not correctly initialized by Coreboot such that the OS can boot without kernel parameters and allow for Thunderbolt hotplugging. Additional bus numbers and memory must be allocated.
I will be working on support for this for our System76 mainboards.
Here were the notes taken about it during the meeting, see 9 October 2019, PCIe Hotplug on newer Intel socs:
As of 27th November and commit  platforms using AMD binaryPI blobs
have been disabled from automatic build testing. The following are
This is inline with CAR_GLOBAL_MIGRATION deprecation as mandated by
4.11 release requirements. You should expect that the board sources
and platform support will disappear by 14th December, at latest,
unless you show interest *and* are able to provide bootlogs for the
PCEngines APU2 and variants are an exception to this, they were
converted to POSTCAR_STAGE and work away from ROMCC_BOOTBLOCK shows
You'll know me as one of the driving forces keeping our i440BX port alive.
I did see the two latest patches trying to modernize it and I swear I'll
get to it soon, because to be honest, that P2B-LS board has a special place
in my mind and is not going away, although it is not seeing much use
anymore in practice, which brings me to my next step and question.
I have three more modern boards (read: 2012 and they share the same 16GB
pair of DDR3L memory modules) with cousins already in the tree but not the
exact model. I do know I need to get some info in, but I want to get a take
on which one will have the best chance to get a working port first:
Lenovo ThinkPad X230 Tablet. This is now my daily machine. Due to some
snafu on my part I bought a second unit with only Wacom pen but no touch.
The non-tablet X230 is in the tree and there were some notes on tablet
hardware. I need to buy a test clip to access the flash chip. Now I wonder
if this guy is "already" supported.
Asus M4A785TD-M EVO. AM3, family 10h, closest cousin was m4a785t-m, but I
don't know where it went now.
Asus P8Z77-M. Closest cousin is p8z77-m_pro. Mine is not pro, but I don't
know off my head what the difference is. And I get to deal with ME.
More info once I get back to my desktop.
Hot off the heels of the previous hotfix is a fresh release based on
the newly-tagged coreboot 4.11. In addition to being rebased on the
latest version of coreboot, this release features a host of
improvements and fixes:
* fixed issue with NVRAM being corrupted by Windows
* new/improved UEFI Boot Options/Settings screens
* improved header layout
* simplified menu options
* more descriptive naming for SATA, NVMe, and USB drives in boot menu
* easier to make changes to and save bootorder entries
* open-source coreboot native graphics init (libgfxinit) now used for
Haswell, Broadwell, and Skylake devices instead of closed-source GOP
* better scaling of boot splash/menus for HiDPI displays
This MrChromebox release offers coreboot/Tianocore images for close to
70 Chromebooks/Chromeboxes as well as all Purism Librem laptops, all
easily flashed using my ChromeOS Firmware Utility Script ; a full
list of supported devices can be found on my site .
All other devices supported by the coreboot 4.11 release can easily
take advantage of the improvements in my tree by cloning my coreboot
repo and building as usual.
All changes on the Tianocore side have already been merged and are
available to anyone using the default coreboot repo.
As usual, the full list of changes can be found on my github repos: