coreboot November 2019

coreboot@coreboot.org

52 participants
51 discussions

[PATCH v2 0/3] firmware: google: Fix minor bugs
by patrick.rudolph＠9elements.com 18 Nov '19

18 Nov '19

From: Patrick Rudolph <patrick.rudolph(a)9elements.com> This patch series fixes 3 independent bugs in the google firmware drivers. Patch 1-2 do proper cleanup at kernel module unloading. Patch 3 adds a check if the optional GSMI SMM handler is actually present in the firmware and responses to the driver. Changes in v2: - Add missing return statement - Add s-o-b on GSMI patches - Add define for reserved GSMI command Arthur Heymans (2): firmware: google: Unregister driver_info on failure and exit in gsmi firmware: google: Probe for a GSMI handler in firmware Patrick Rudolph (1): firmware: google: Release devices before unregistering the bus drivers/firmware/google/coreboot_table.c | 7 +++++++ drivers/firmware/google/gsmi.c | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) -- 2.21.0

2 1

[Patch v2 1/3] firmware: google: Release devices before unregistering the bus
by patrick.rudolph＠9elements.com 18 Nov '19

18 Nov '19

From: Patrick Rudolph <patrick.rudolph(a)9elements.com> Fix a bug where the kernel module can't be loaded after it has been unloaded as the devices are still present and conflicting with the to be created coreboot devices. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- drivers/firmware/google/coreboot_table.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/firmware/google/coreboot_table.c b/drivers/firmware/google/coreboot_table.c index 8d132e4f008a..0205987a4fd4 100644 --- a/drivers/firmware/google/coreboot_table.c +++ b/drivers/firmware/google/coreboot_table.c @@ -163,8 +163,15 @@ static int coreboot_table_probe(struct platform_device *pdev) return ret; } +static int __cb_dev_unregister(struct device *dev, void *dummy) +{ + device_unregister(dev); + return 0; +} + static int coreboot_table_remove(struct platform_device *pdev) { + bus_for_each_dev(&coreboot_bus_type, NULL, NULL, __cb_dev_unregister); bus_unregister(&coreboot_bus_type); return 0; } -- 2.21.0

2 3

Re: Decryption of post codes that appear during Intel FSP operation?
by Alexey Borovikov 17 Nov '19

17 Nov '19

Hi, all! For the FSP 1.0 package for Baytrail platform, where can I find a description of the postcodes? On github does not this information in documentation. Thanks

1 0

[AMD 16h / ASUS AM1I-A] 1866MHz CL9 RAM runs only as 1333MHz CL9 - how to fix?
by Mike Banon 17 Nov '19

17 Nov '19

A pair of 1866MHz CL9 RAM modules* runs only as 1333MHz CL9 on 16h AM1I-A with coreboot is installed, but worked faster when a proprietary UEFI was installed. To fix this "turtle RAM" coreboot problem I tried to play with buildOpts.c - https://review.coreboot.org/c/coreboot/+/33920 , but the things like "#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY" sadly did not help. Any ideas how to improve the RAM speeds? How I can force this RAM to run faster? Best regards, Mike Banon [*] Crucial Ballistix Tactical Series DDR3 1866MHz CL9 (PC3-14900 9-9-9-24) UDIMM 240-Pin modules, part number BLT8G3D1869DT1TX0

3 9

[PATCH 0/2] firmware: google: Expose coreboot tables and CBMEM
by patrick.rudolph＠9elements.com 17 Nov '19

17 Nov '19

From: Patrick Rudolph <patrick.rudolph(a)9elements.com> As user land tools currently use /dev/mem to access coreboot tables and CBMEM, provide a better way by using sysfs attributes. Unconditionally expose all tables and buffers making future changes in coreboot possible without modifying a kernel driver. Patrick Rudolph (2): firmware: google: Expose CBMEM over sysfs firmware: google: Expose coreboot tables over sysfs drivers/firmware/google/Kconfig | 6 + drivers/firmware/google/Makefile | 1 + drivers/firmware/google/cbmem-coreboot.c | 164 +++++++++++++++++++++++ drivers/firmware/google/coreboot_table.c | 59 ++++++++ drivers/firmware/google/coreboot_table.h | 13 ++ 5 files changed, 243 insertions(+) create mode 100644 drivers/firmware/google/cbmem-coreboot.c -- 2.21.0

4 5

Coreboot on Asus C101PA Chromebook aka Bob
by Sahaj Sarup 16 Nov '19

16 Nov '19

Hi All, Are their any build and flashing instructions for this main-board? And what's the support status atm? -- Best Regards Sahaj Sarup

1 0

[PATCH 0/3] firmware: google: Fix minor bugs
by patrick.rudolph＠9elements.com 16 Nov '19

16 Nov '19

From: Patrick Rudolph <patrick.rudolph(a)9elements.com> This patch series fixes 3 independent bugs in the google firmware drivers. Patch 1-2 do proper cleanup at kernel module unloading. Patch 3 adds a check if the optional GSMI SMM handler is actually present in the firmware and responses to the driver. Arthur Heymans (2): firmware: google: Unregister driver_info on failure and exit in gsmi firmware: google: Probe for a GSMI handler in firmware Patrick Rudolph (1): firmware: google: Release devices before unregistering the bus drivers/firmware/google/coreboot_table.c | 6 ++++++ drivers/firmware/google/gsmi.c | 24 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+) -- 2.21.0

3 7

Signing the coreboot Image
by Jorge Fernandez Monteagudo 15 Nov '19

15 Nov '19

Hi all, Sorry my noob question but I would like to clarify something. The steps detailed in the 'Signing the coreboot Image' section from https://doc.coreboot.org/security/vboot/index.html are already integrated in the coreboot.rom building process? Now I can see the steps: CREATE GBB (without BMPFV) successfully created new GBB to: build/gbb.stub.tmp SETUP GBB - import root_key from root_key.vbpubk: success - import recovery_key from recovery_key.vbpubk: success successfully saved new image to: build/gbb.region.tmp WRITE GBB W: Written area will abut bottom of target region: any unused space will keep its current contents FLASHMAP Layout generated for RO and A partition. at the end of the building process. Thanks! Jorge

1 0

Decryption of post codes that appear during Intel FSP operation?
by dponamorev＠gmail.com 15 Nov '19

15 Nov '19

Hi! Please tell me where I can get the decryption of post codes that appear during Intel FSP operation? Codes such as 0x57, 0x59, 0x58, 0x62 ... I see that they appear during testing and memory tuning, but I would like to have more detailed information. Maybe someone knows the number of the Intel document to download? Regards, Dmitry

3 5

How to measure the differents parts of coreboot?
by Jorge Fernandez Monteagudo 14 Nov '19

14 Nov '19

Hi all, I would like to extend to TPM PCR register the differents parts of coreboot once loaded. Is it correct to use the pointers from memlayout.h? For instance to extent the romstage to PCR1 I do something like: extern char _romstage, _eromstage; tlcl_measure(1, &_romstage, &_eromstage - &_romstage); Is it correct to do the same bootblock, ramstage, verstage, etc? My goal is to extend all the coreboot. Thanks! Jorge

2 18

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2019