I just released FILO 0.4.
http://te.to/~ts1/filo/
It can boot distro CDs if you give a proper command line.
SuSE 8.2 LiveEval CD worked without a glitch, I enjoyed the
KDE desktop, OpenOffice, etc, from the CD on an EPIA booted
from LinuxBIOS.
Also added support for booting from BIOS flash, to boot an
alternative bootloader like Etherboot.
PCI support in IDE driver is also added (or recovered), but
the native PCI mode is not fully tested.
I tried to configure EPIA (V1) code to use native mode,
and the ports read something not 0xff, but the drive doesn't
respond to soft reset.
I don't know the bug is in FILO, LinuxBIOS, or the hardware.
I'll work on config file support next time.
Version 0.4 ts1 2003-10-15
* Support for ATAPI CD-ROM.
* ISO-9660 filesystem is taken from a GRUB patch by
Leonid Lisovskiy <lly(a)pisem.net>. The filesystem code was originally
written by Kousuke Takai <tak(a)kmc.gr.jp> for GRUB/98 project.
* Support for mounting boot disk image of El Torito bootable CD-ROM.
("hdc1" means the boot disk image of the CD-ROM at hdc.)
* Support for memory as device, raw device as image, and
user-specifiable device offset and length.
(eg. boot: mem@0xfffd0000,0x10000)
* PCI support in IDE driver. Now it by default uses PCI enumeration
to find the PCI IDE controller, and can use native PCI mode
if the controller is configured to this mode by BIOS.
To disable this, turn off SUPPORT_PCI.
* Fixed Linux loader to boot RedHat 9 kernel properly.
--
Takeshi
Ron,
I have checked pci.c in fifo. It need to be changes as follow.
It seems otherwise it can not scan the peer root bus.
Maybe someone need to make it can handle peer root bus refer to the code in
Linux kernel or Etherboot.
Regards
YH.
void pci_init(void)
{
/* Count devices */
dev_list = 0;
debug("Scanning PCI: ");
pci_scan_bus(0);
pci_scan_bus(1); // For Tyan s2880,s2881,s2882,s2885,s4880
// pci_scan_bus(3); //For Tyan s2885
debug("found %d devices\n", n_devs);
/* Make the list */
dev_list = malloc(n_devs * sizeof(struct pci_dev));
n_devs = 0;
pci_scan_bus(0);
pci_scan_bus(1); // For Tyan s2880,s2881,s2882,s2885,s4880
// pci_scan_bus(3); //For Tyan s2885
#if DEBUG
{
int i;
for (i = 0; i < n_devs; i++) {
debug("%02x:%02x.%x %04x:%04x %04x %02x\n",
PCI_BUS(dev_list[i].addr),
PCI_DEV(dev_list[i].addr),
PCI_FN(dev_list[i].addr),
dev_list[i].vendor,
dev_list[i].device,
dev_list[i].devclass,
dev_list[i].prog_if);
}
}
#endif
}
-----邮件原件-----
发件人: YhLu
发送时间: 2003年12月10日 9:27
收件人: 'ron minnich'
抄送: Hendricks David W.
主题: Re: IDE on s2885 and LinuxBIOS
Is it working with On current tree or using old source tree to make sure all
8111/8131 on bus 0?
Yinghai Lu
-----邮件原件-----
发件人: ron minnich [mailto:rminnich@lanl.gov]
发送时间: 2003年12月10日 7:25
收件人: YhLu
抄送: Hendricks David W.
主题: Re: IDE on s2885 and LinuxBIOS
I wonder what differes from HDAMA to s2885? filo works fine on HDAMA
ron
I'm trying to get the STPC Elite development board to use
linuxbios with Filo, but after elfboot announces itself
the board reboots:
----------------------
.....
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2
LinuxBIOS-1.0.0 Thu Nov 6 16:13:37 GMT 2003 starting...
Copying LinuxBIOS to ram.
....
------------------------
My config file looks like this:
target /home/fox/build/freebios1/stpc
mainboard stpc/elite
biosbase 0xffff0000
option CONFIG_COMPRESS=0
option SERIAL_CONSOLE=1
option TTYS0_BAUD=38400
option DEFAULT_CONSOLE_LOGLEVEL=9
option DEBUG=1
# option ROM_IMAGE_SIZE=131072
option ROM_SIZE=131072
option USE_ELF_BOOT=1
option PAYLOAD_SIZE=65536
payload /home/fox/build/filo-0.4/filo.elf
Any ideas as to what I've missed ?
--
Peter Fox <peter.fox(a)aeroflex.com> Aeroflex Test Solutions
Principal Design Engineer Stevenage
Any opinions expressed above are http://www.aeroflex.com/
not necessarily those of Aeroflex. Tel: + 44 (0) 1438 742200
Brainstorming earlier today I think I have found a way to use
an linux kernel for the boot loader and to implement pcbios
compatibility without too much cost. The idea is to use
a uclinux kernel. And implement a ``user space'' aplication
that is a user space shim that makes kernel calls.
There are a few nasty details to work out like how to handle
services that are expected to work in vm86 mode. But I'm
not certain I care.
Other thoughts?
After I come back from my christmas vacation I am going to have to try
it and see how will it will actually work.
Eric
I've heard that you can use LinuxBIOS to bootload other operating
systems (like Windows, etc). Is it possible for LinuxBIOS to boot the
device and install a block of code in memory that handles BIOS disk
requests using some sort of network block device protocol?
Failing this, does anybody know of a cheap hardware device that would
do the same thing?
Thanks.
- a
--
"If Darl McBride [the CEO of SCO, who claims the GPL 'destroys
intellectual property'] was in charge, he'd probably make marriage
unconstitutional too, since clearly it de-emphasizes the commercial
nature of normal human interaction, and probably is a major
impediment to the commercial growth of prostitution"
-- Linus Torvalds
Hi,
Which file system should I use for diskonchip millennium while using
with linuxbios?
_________________________________________________________________
Free transactions in any ATM across India.
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Devi Priya wrote:
> I like to use either Flash memory or DOC and not both. I want to know if
> I have my Flash memory or DOC mapped to lower address what modification
> should I do to the linuxbios coding. like regarding setiing the RAMBASE,
> ROMBASE...........
>
The power-up reset address for the Geode is FFFFFFF0h, you can't change
that.
Your only strapping options are:
(1) Enable either an 8 bit or 16 bit boot ROM access
(2) Enable either a LPC or ISA boot ROM access.
-Bari
> Regards,
> Priya.
>
>
>> From: Bari Ari <bari(a)onelabs.com>
>> To: Devi Priya <ijpriya(a)hotmail.com>
>> CC: linuxbios(a)clustermatic.org
>> Subject: Re: Flash mapped to lower address?
>> Date: Fri, 26 Dec 2003 20:45:41 -0600
>>
>>
>>
>> Devi Priya wrote:
>>
>>> If i have my Flash memory mapped to the lower address
>>> (0x0000-0x3FFFFF), then what modification should be made to linux bios?
>>
>>
>> Are you using NAND Flash or DOC or both ? Are you trying to boot from
>> the DOC?
>>
>> You may also want to look at the
>>
>> Geode™ IA on a Chip Devices: Booting from the M-Systems DiskOnChip
>> Millennium Application Note
>>
>> http://www.m-sys.com/files/documentation/doc/App_Note_047_Des_DOC_FD_Boot_R…
>>
>>
>> http://www.m-sys.com/files/documentation/doc/App_Note_031_PC_Rev_2.2.pdf
>>
>> -Bari
>>
>>
>>
>> _______________________________________________
>> Linuxbios mailing list
>> Linuxbios(a)clustermatic.org
>> http://www.clustermatic.org/mailman/listinfo/linuxbios
>
>
> _________________________________________________________________
> NRI’s, Free Money transfer to India.
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> Click here.
>
>
>
If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF),
then what modification should be made to linux bios?
_________________________________________________________________
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Hi,
>From the AMD data sheet:
The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap determines
the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#,WR# and ROMCS#
asserted.
The Boot Flash supported by the SC1200/SC1201 can be
up to 16 MB. It is supported with the ROMCS# signal.
As the corelogic module positively decodes the memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset, I can have my Flash memory mapped to
the lower address. Is it?
>From: ron minnich <rminnich(a)lanl.gov>
>To: Devi Priya <ijpriya(a)hotmail.com>
>CC: linuxbios(a)clustermatic.org
>Subject: Re: Flash mapped to lower address?
>Date: Wed, 24 Dec 2003 18:39:20 -0700 (MST)
>
>On Tue, 23 Dec 2003, Devi Priya wrote:
>
> > If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF),
> > then what modification should be made to linux bios?
>
>why on earth would you map flash to this address? it makes no sense to me.
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios(a)clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
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