Hello,
Wondering if anyone can help me with this one:
I have a basic EPIA board
(http://www.viavpsd.com/product/epia_mini_itx_spec.jsp?motherboardId=21)
, the one with the 533MHz CPU.
Anyway, I managed to find myself a PLCC Flash chip which seems like it
will work (http://www.farnell.com/datasheets/23247.pdf), but when I run
the flash program it complains that it does not recognise the chip. So,
I added an entry for the chip in "flash.h" hoping I could use the
regular routines for the EPIA, but it says it cannot unlock the chip.
Can someone help me with this one pls? Could someone supply a diff,
using the above datasheet, that would enable me to use the chip? Even
some tips on what I'd need to do if I had to write the code would be
appreciated.
Thanks,
Surj
Hello there,
I'd like to flash my ChainTech motherboard with a Linux kernel or just grub.
Did anyone did this before? And if so, how did you do it?
Cheers,
Kees
P.S. It's a pity the documentation on the web is very sparse, maybe I can
write some?
Andrew Ip wrote:
>Have you checked out the clock connected to LPC? On W311, FS2 can be
>set to 24 or 48 MHz. It could be the problem, since I have similar problem
>with USB on a custom cle266 board. FYI, it can be programmed thru smb.
>Here is from we have done to program the USB clock.
>...
>You may want to put similar code in serial init. Hope this help.
I tried this and...it worked! My simple test program is below. Linuxbios
puts the smb stuff at 0xf00 and it is already enabled (at least in my patch).
So all I had to do was do the outb's to get it to work. Thanks *very* much.
Note to Ron: Let me know if you want the epia-m, I'll still send one off if
you want it. I've got a spare 10000 (1 gig) that you can have. Note I
don't read email sent to the address I'm posting from...best send to
dash(a)xdr.com to get to me.
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <sys/io.h>
#include <stdlib.h>
#define SMB_STATUS (base + 0)
#define SMB_CONTROL (base + 2)
#define SMB_COMMAND (base + 3)
#define SMB_ADDRESS (base + 4)
#define SMB_DATA (base + 5)
#define I2C_TRANS_CMD 0x40
#define CLOCK_SLAVE_ADDRESS 0x69
int main(int argc, char **argv)
{
int res;
int base=0xf00;
res=iopl(3);
if(res)
{
perror("iopl");
exit(-1);
}
outb( 0xff, SMB_STATUS );
// USB out 48MHz
outb( 0x7f, SMB_DATA );
outb( 0x83, SMB_COMMAND );
outb( (CLOCK_SLAVE_ADDRESS<<1), SMB_ADDRESS );
outb( 0x8|I2C_TRANS_CMD, SMB_CONTROL );
while( inb(SMB_STATUS) & 0x01 );
}
-Dave
I scanned the entire mailing and website for LinuxBIOS and didn't see a
single reference to the Intel 82845G/GL. Is this configuration
supported? If not, would it be "easy" to add support for it?
I'm very new to LinuxBIOS (just discovered the website a month or so ago
and still don't fully grok it) but have two machines with this chipset
I'd like to get setup as sample boxes to show my boss the increase in
boot time. (From what I hear, it speeds up boot time CONSIDERABLY)
Thanks in advance for your time,
Brian Thomason
Lindows.com Developer Relations
Here is what I did to integrate this into linuxbios. I
created the following file
src/mainboard/via/epia-m/smbusenable.inc
/* Useful macros PCIBUS, and SMBUS functions for getting DRAM going. */
/* courtesy Eric Biederman of linuxnetworx.com */
#define CS_WRITE_BYTE(addr, byte) \
movl $addr, %eax ; \
movl $byte, %edx ; \
PCI_WRITE_CONFIG_BYTE
#define CS_WRITE_WORD(addr, word) \
movl $addr, %eax ; \
movl $word, %ecx ; \
PCI_WRITE_CONFIG_WORD
#define CS_WRITE_LONG(addr, dword) \
movl $addr, %eax ; \
movl $dword, %ecx ; \
PCI_WRITE_CONFIG_DWORD
#define DEVFN(device, function) (((device) << 3) + (function))
#ifndef CONFIG_ADDR
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
#endif
/* generic SMB routines that work for many systems. The only one that might
* not work is the enable_smbus.
* you have to define PM_FUNCTION for this to work.
*/#define SMBUS_IO_BASE 0xf00
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBHSTCMD 3
#define SMBHSTADD 4
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
/* (DA) Lines added to get this to compile */
#define PM_DEVFN CONFIG_ADDR(0,0x11*8,0)
#define DRAM_CONFIG_PORT 0x5a
#define SMBUS_MEM_DEVICE_0 0x50
#define LAST_SMBUS_MEM_DEVICE SMBUS_MEM_DEVICE_0
#define REGISTERED_DRAM_REGISTER $0x69
#define REGISTERED_DRAM $0x2d
#define NONREGISTERED_DRAM $0
/* put the SMBUS at port 0xf00 + enable*/
CS_WRITE_WORD(PM_DEVFN+ 0xd0, SMBUS_IO_BASE|1) /* iobase addr */
CS_WRITE_BYTE(PM_DEVFN + 0xd2, (0x4 << 1) | 1) /* smbus enable */
CS_WRITE_WORD(PM_DEVFN + 0x4, 1) /* iospace enable */
/* The VT1211 serial port needs 48 mhz clock, on power up it is getting
only 24 mhz, there is some mysterious device on the smbus that can
fix this...this code below does it. */
#define MYOUTB(val, port) movb val, %al; movw port, %dx ; outb %al, %dx
#define I2C_TRANS_CMD 0x40
#define CLOCK_SLAVE_ADDRESS 0x69
MYOUTB( $0xff, $(SMBUS_IO_BASE+SMBHSTSTAT))
MYOUTB( $0x7f, $(SMBUS_IO_BASE+SMBHSTDAT0))
MYOUTB( $0x83, $(SMBUS_IO_BASE+SMBHSTCMD))
MYOUTB( $(CLOCK_SLAVE_ADDRESS<<1), $(SMBUS_IO_BASE+SMBHSTADD))
MYOUTB( $(8 | I2C_TRANS_CMD), $(SMBUS_IO_BASE+SMBHSTCTL))
movw $(SMBUS_IO_BASE+SMBHSTSTAT), %dx
smbwait1:
inb %dx, %al
and $1, %al
jnz smbwait1
----- Now in src/mainboard/via/epia-m/Config we need to include the above
file, so it ends up looking like this:
mainboardinit mainboard/via/epia-m/smbusenable.inc
mainboardinit superio/via/vt1211/setup_serial.inc
mainboardinit pc80/serial.inc
-Dave
Thanks for ur suggestion.
My flash is 4 MB. My processor can address up to 4 GB physical address
space. That means after power-on, in shematic should I map the flash memory
like 0xFFC00000-0xFFFFFFFF and
0x00000000-0x003FFFFF? 0r in upper address, is it enough to map the 256KB
region to the Flash ie 0xFFFC0000-0xFFFFFFFF? and the lower address to
0x00000000-0x003FFFFF
>From: ron minnich <rminnich(a)lanl.gov>
>To: Devi Priya <ijpriya(a)hotmail.com>
>CC: linuxbios(a)clustermatic.org
>Subject: Re: sc1200?
>Date: Wed, 17 Dec 2003 22:07:00 -0700 (MST)
>
>at power-on, on all chipsets for PCs I have used, FLASH is mapped at BOTH
>0xffffff0 and 0xffff0.
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios(a)clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
_________________________________________________________________
Dont miss out on jobs that are not advertised.
http://go.msnserver.com/IN/38902.asp Post your CV on naukri.com today.
Hi,
After power-on, the x86 processor is placed in real mode. That means the CPU
looks for the instruction at the address 0xffff0. Is it correct? In SC1200
datasheet, it is given that,
"Approximately 150 to 250 external clock cycles after RESET is deasserted,
the processor begins executing instructions at the top of physical memory
(address location
FFFFFFF0h). The actual number of clock cycles depends on the clock scaling
in use. Also, before execution begins, an additional 220 clock cycles are
needed when self-test is
requested. Typically, an intersegment jump is placed at FFFFFFF0h. This
instruction will force the processor to begin execution in the lowest 1 MB
of address space."
In real mode, the CPU can address only 1 MB. Then how this address could be
addressed by the CPU?
To which address does my Flash memory gets mapped to at power-on?
_________________________________________________________________
Dont miss out on jobs that are not advertised.
http://go.msnserver.com/IN/38902.asp Post your CV on naukri.com today.
I am at my wits end regarding how to get the serial ports on the epia-m to
run at full 115,200 baud rate. Here is a summary of what is known:
1) The serial ports are driven by the VT1211 superio chip.
2) Under AWARD bios the serial ports are capable of 115,200 operation.
3) Under linuxbios they can only run at 57,600 max.
4) Booting up with AWARD then soft reset (or hit reset button on motherboard)
into linuxbios still maintains 115,200 baud
5) Hard reset (power off then on) into linuxbios reduces maximum baud rate to
57,600.
6) All registers of the VT1211 are identical after linuxbios bootup, whether
from award -> softreset -> linuxbios bootup or hardreset -> linuxbios bootup.
I am speaking of all registers of all logical devices of the VT1211, including
all the global registers. I wrote a program to dump everything then diff'd the
two outputs, they're identical.
I have repeatedly tried asking VIA for help, in various different ways. The
VT1211 datasheet and the VT1211 bios porting guide have not resolved the
issue. VIA has proven incapable of addressing the problem.
I have one last idea. There is an emulator to test VGA bios's, I was messing
with it a few months back. Is there an emulator for the full BIOS? I'd like
to be able to watch all io port accesses of the award bios, maybe I can
trap when it goes to write to the 0x2e + 0x2f io ports to configure the
vt1211 serial ports, then look for something near there that might be related.
The idea would be to figure out what magical thing the AWARD bios is doing
to initialize the serial port.
Failing that is there any way to disassemble a BIOS image?
Any ideas welcome.
BTW if anyone has figured out how to fix the problem, please just f*cking
out with it, I think I've been very generous in the past with enhancements
and turnabout is fair play.
Thanks--
Dave
>I don't know what the problem is, I don't have an EPIA-M yet.
>...
>Are your sure the clock source for the superio or uart is the same for
>linuxbios and award?
>The "emulator for VGA bios" will actually run anything...
If sending you an epia-m would mean you'd begin looking at it I'll
get you one. Let me know.
I'm not sure of the clock source, VIA hasn't provided a schematic for the
board. The datasheet indicates 2 clock sources, one is for the LPC
interface and the other is for the main clock. LPC is the 33 mhz pci clock.
The other clock is 48 mhz. I had a scope on the chip and as near as I can
tell the 48 mhz clock was in fact 48 mhz. I didn't look at the 33 mhz clock
at all.
-Dave
