coreboot January 2021

coreboot@coreboot.org

46 participants
34 discussions

A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

by dponamorev＠gmail.com

Hi! We developed our CRB motherboard on Intel Atom C3538 (4 core) Denverton_NS processor. Faced with the following problem. For part of processors with the same SKU and steping (Atom C3538), lapic #4 in devicetree.cb needed (95%), and for the other part lapic #0 (5%). Intel confirmed that it might be so and that's okay ... Part of devicetree.cb: device cpu_cluster 0 on device lapic 4 on end end If we do not specify lapic id correctly in devicetree.cb, freeBSD OS does not BOOT (Unix like). FreeBSD BOOT log (set lapic #4 in devicetree.cb but need lapic #0): Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 APIC: Found table at 0x7f769420 APIC: Using the MADT enumerator. MADT: Found CPU APIC ID 0 ACPI ID 0: enabled SMP: Added CPU 0 (AP) MADT: Found CPU APIC ID 4 ACPI ID 1: enabled SMP: Added CPU 4 (AP) MADT: Found CPU APIC ID 12 ACPI ID 2: enabled SMP: Added CPU 12 (AP) MADT: Found CPU APIC ID 16 ACPI ID 3: enabled SMP: Added CPU 16 (AP) MADT: Found CPU APIC ID 24 ACPI ID 4: enabled SMP: Added CPU 24 (AP) Copyright (c) 1992-2019 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 11.3-RELEASE #0 r349754: Fri Jul 5 04:45:24 UTC 2019 root@releng2.nyi.freebsd.org:/usr/obj/usr/src/sys/GENERIC amd64 FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0) Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 Table 'HPET' at 0x7f7694a0 ACPI: No SRAT table found PPIM 0: PA=0xa0000, VA=0xffffffff82410000, size=0x10000, mode=0 VT(vga): resolution 640x480 Preloaded elf kernel "/boot/kernel/kernel" at 0xffffffff8226d000. Calibrating TSC clock ... TSC clock: 2100071708 Hz CPU: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz (2100.07-MHz K8-class CPU) Origin="GenuineIntel" Id=0x506f1 Family=0x6 Model=0x5f Stepping=1 Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE> Features2=0x4ff8ebbf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,RDRAND> AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM> AMD Features2=0x101<LAHF,Prefetch> Structured Extended Features=0x2294e283<FSGSBASE,TSCADJ,SMEP,ERMS,NFPUSG,MPX,PQE,RDSEED,SMAP,CLFLUSHOPT,PROCTRACE,SHA> Structured Extended Features3=0xac000400<MD_CLEAR,IBPB,STIBP,ARCH_CAP,SSBD> XSAVE Features=0xf<XSAVEOPT,XSAVEC,XINUSE,XSAVES> IA32_ARCH_CAPS=0x69<RDCL_NO,SKIP_L1DFL_VME> VT-x: Basic Features=0xda0400<SMM,INS/OUTS,TRUE> Pin-Based Controls=0xff<ExtINT,NMI,VNMI,PreTmr,PostIntr> Primary Processor Controls=0xfff9fffe<INTWIN,TSCOff,HLT,INVLPG,MWAIT,RDPMC,RDTSC,CR3-LD,CR3-ST,CR8-LD,CR8-ST,TPR,NMIWIN,MOV-DR,IO,IOmap,MTF,MSRmap,MONITOR,PAUSE> Secondary Processor Controls=0x1d6fff<APIC,EPT,DT,RDTSCP,x2APIC,VPID,WBINVD,UG,APIC-reg,VID,PAUSE-loop,RDRAND,VMFUNC,VMCS,XSAVES> Exit Controls=0xda0400<PAT-LD,EFER-SV,PTMR-SV> Entry Controls=0xda0400 EPT Features=0x6334141<XO,PW4,UC,WB,2M,1G,INVEPT,AD,single,all> VPID Features=0xf01<INVVPID,individual,single,all,single-globals> TSC: P-state invariant, performance statistics DTLB: 4k pages, fully associative, 32 entries Data TLB: 4 KBytes pages, 4-way set associative, 512 entries Instruction TLB: 4 KByte pages, fully associative, 48 entries DTLB: 2M/4M Byte pages, 4-way associative, 32 entries L2 cache: 2048 kbytes, 16-way associative, 64 bytes/line real memory = 8589934592 (8192 MB) Physical memory chunk(s): 0x0000000000010000 - 0x000000000009bfff, 573440 bytes (140 pages) 0x0000000000100000 - 0x00000000001fffff, 1048576 bytes (256 pages) 0x0000000002400000 - 0x000000007f74ffff, 2100625408 bytes (512848 pages) 0x0000000100000000 - 0x000000027012efff, 6175256576 bytes (1507631 pages) avail memory = 8220336128 (7839 MB) Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 Table 'HPET' at 0x7f7694a0 ACPI: No DMAR table found Event timer "LAPIC" quality 600 ACPI APIC Table: <COREv4 COREBOOT> WARNING: L1 data cache covers less APIC IDs than a core 0 < 1 Package ID shift: 5 L2 cache ID shift: 2 L1 cache ID shift: 1 Core ID shift: 1 panic: AP #4 (PHY# 0) failed! cpuid = 0 KDB: stack backtrace: #0 0xffffffff80b4c4b7 at kdb_backtrace+0x67 #1 0xffffffff80b054ce at vpanic+0x17e #2 0xffffffff80b05343 at panic+0x43 #3 0xffffffff80f752a4 at native_start_all_aps+0x344 #4 0xffffffff80f74c4f at cpu_mp_start+0x2ef #5 0xffffffff80b5cb76 at mp_start+0xa6 #6 0xffffffff80aa0b48 at mi_startup+0x118 #7 0xffffffff8031202c at btext+0x2c Uptime: 1s Other Linux OS boot but show an incorrect number of cores (5 instead of 4) and offline processor cores appear (see log). Ubuntu 18.04 LTS (GNU/Linux 4.15.0-20-generic x86_64) # lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 5 On-line CPU(s) list: 0,2-4 Off-line CPU(s) list: 1 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 95 Model name: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz Stepping: 1 CPU MHz: 2097.502 CPU max MHz: 2100.0000 CPU min MHz: 800.0000 BogoMIPS: 4200.00 Virtualization: VT-x L1d cache: 24K L1i cache: 32K L2 cache: 2048K NUMA node0 CPU(s): 0,2-4 What can be done in this situation? How to make a universal version of devicetree.cb?

1 month, 4 weeks

Testing code present in SMM

by Mick

Dear everyone, For my master project I will apply hardening techniques (sanitizers/CFI) to System Mangement Mode (SMM). Now for my evaluation, I want to test code in SMM and ideally cover all SMI handlers coreboot offers. However, in my experience, System Management Interrupts (SMIs) rarely trigger and the variety in SMIs is also rather low (testing via QEMU). I was wondering whether anyone is familiar with testing such a low-level component. In the coreboot repository, I couldn't find any tests related to SMM and looking online also hasn't provided me any answers. Is there anyone who has experience with similar problems or can perhaps point me into the right direction, as I am inexperienced with testing such low-level components. I hope I've explained myself clearly, if not, please indicate so! Kind regards, Mick

8 months, 2 weeks

Coreboot BIOS question

by SuperNova

Hello, I am a new user of Coreboot who recently purchased a Protectli firewall with Coreboot pre-installed. The firewall is running PfSense that I installed on it. Everything was going ok for a few days until I started having issues with PfSense and now I am having problems getting PfSense to launch at all. I believe this is related to a hardware issue with the firewall. During the coreboot launch I am getting an infinite loop which is triggered at the following line: cpu reset proxy stopped cpu 1 Sounds like an issue with the hardware to me. I believe I saw this same issue referencing cpu 2 as well. I have tried over a period of several weeks to boot up and I always get this message and then a loop back to the the coreboot initialization. At this point I cannot tell if this is a coreboot, pfsense, or hardware issue, and I am getting ready to just buy another firewall with pfsense already installed and I am hoping someone has the time to give me a brief idea of what might be going on here. I am fairly PC savy but am having difficulty drilling down to what might be driving this specific issue on the web. I do like your product and plan to purchase a PC with coreboot in the near future. Thanks a lot for your time. -Aaron Sent with [ProtonMail](https://protonmail.com) Secure Email.

8 months, 3 weeks

Problems with CAR setup on Tiger Lake

by Michał Żygowski

Dear coreboot community, I have a Tiger Lake UP3 RVP and I try to build a working coreboot on it, however facing an early stuck during CAR setup. Tried different approaches: - native coreboot's CAR setup - the last seen post code is 0x26 - FSP-T CAR setup - the last seen post code is 0x7F (which is TempRamInit Exit event according to FSP integration guide), FSP from public repo, Client variant Used microcode from original RVP firmware. Are there any patches that I have to apply to make it working? Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com

8 months, 3 weeks

New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1445764: Incorrect expression (CONSTANT_EXPRESSION_RESULT) /src/soc/intel/broadwell/raminit.c: 155 in setup_sdram_meminfo() ________________________________________________________________________________________________________ *** CID 1445764: Incorrect expression (CONSTANT_EXPRESSION_RESULT) /src/soc/intel/broadwell/raminit.c: 155 in setup_sdram_meminfo() 149 return; 150 } 151 152 memset(mem_info, 0, sizeof(*mem_info)); 153 /* Translate pei_memory_info struct data into memory_info struct */ 154 mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; >>> CID 1445764: Incorrect expression (CONSTANT_EXPRESSION_RESULT) >>> "8 < 8" is always false regardless of the values of its operands because those operands are identical. This occurs as the logical first operand of "?:". 155 for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) { 156 struct dimm_info *dimm = &mem_info->dimm[i]; 157 const struct pei_dimm_info *pei_dimm = 158 &pei_data->meminfo.dimm[i]; 159 dimm->dimm_size = pei_dimm->dimm_size; 160 dimm->ddr_type = pei_dimm->ddr_type; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

9 months

Debugging Windows 10 BSOD

by Raul Rangel

I'm trying to boot the Windows 10 Installer on a picasso based device using coreboot + tianocore. I keep getting a BSOD after the windows logo shows with the very descriptive stop code `ACPI BIOS ERROR`. I've enabled bootdebug on the USB stick using the following: bcdedit /store H:\boot\bcd /bootdebug {bootmgr} on bcdedit /store H:\boot\bcd /bootdebug {default} on bcdedit /store H:\boot\bcd /debug {debug} on Here is the BCD: C:\Windows\system32>bcdedit /store h:\boot\bcd Windows Boot Manager -------------------- identifier {bootmgr} description Windows Boot Manager locale en-US inherit {globalsettings} bootdebug Yes default {default} displayorder {default} toolsdisplayorder {memdiag} timeout 30 Windows Boot Loader ------------------- identifier {default} device ramdisk=[boot]\sources\boot.wim,{7619dcc8-fafe-11d9-b411-000476eba25f} path \windows\system32\boot\winload.exe description Windows Setup locale en-US inherit {bootloadersettings} bootdebug Yes osdevice ramdisk=[boot]\sources\boot.wim,{7619dcc8-fafe-11d9-b411-000476eba25f} systemroot \windows bootmenupolicy Standard detecthal Yes winpe Yes debug Yes ems No C:\Windows\system32>bcdedit /store h:\boot\bcd /dbgsettings debugtype Serial debugport 1 baudrate 115200 I have also added the SPCR table: [000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] [004h 0004 4] Table Length : 00000050 [008h 0008 1] Revision : 02 [009h 0009 1] Checksum : F1 [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 0000002A [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20200925 [024h 0036 1] Interface Type : 00 [025h 0037 3] Reserved : 000000 [028h 0040 12] Serial Port Register : [Generic Address Structure] [028h 0040 1] Space ID : 00 [SystemMemory] [029h 0041 1] Bit Width : 20 [02Ah 0042 1] Bit Offset : 00 [02Bh 0043 1] Encoded Access Width : 03 [DWord Access:32] [02Ch 0044 8] Address : 00000000FEDC9000 [034h 0052 1] Interrupt Type : 03 [035h 0053 1] PCAT-compatible IRQ : 04 [036h 0054 4] Interrupt : 00000004 [03Ah 0058 1] Baud Rate : 00 [03Bh 0059 1] Parity : 00 [03Ch 0060 1] Stop Bits : 00 [03Dh 0061 1] Flow Control : 00 [03Eh 0062 1] Terminal Type : 00 [04Ch 0076 1] Reserved : 00 [040h 0064 2] PCI Device ID : FFFF [042h 0066 2] PCI Vendor ID : FFFF [044h 0068 1] PCI Bus : 00 [045h 0069 1] PCI Device : 00 [046h 0070 1] PCI Function : 00 [047h 0071 4] PCI Flags : 00000000 [04Bh 0075 1] PCI Segment : 00 [04Ch 0076 4] Reserved : 00000000 And the DBG2 table: [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 0000005C [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 78 [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20200925 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0030 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000A [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 20 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 000000F8 [052h 0082 10] Namepath : "\_SB.FUR0" Given all this I have yet to see windows dump anything to the serial console. The device just reboots after the BSOD message. Does anyone have any experience debugging Windows boot errors? Can you share any tips? :) Thanks, Raul

9 months

Re: Testing code present in SMM

by Mick

Hello Peter, Thank you for your response! Cool! And ambitious. :) > Yeah, the project is pretty hacky, to be frank, and will be limited to the setup where SMRAM is from a0000h to bffffh. In general coreboot makes an attempt to not go overboard with SMM code, in > particular the QEMU board code may have almost none, to the point where > it's far from representative for modern platforms. > Yes, I'm aware of coreboot's stance on SMM. If I recall correctly, QEMU seemed to have trouble clearing the SMI_STS register. We will likely use hardware to test the setup. You're confirming my fear related to testing SMM in QEMU. I hope we will be able to see more SMM activity on a real board, but I don't know what to expect, as I have trouble finding sources that discuss how SMM is used in the "wild" (besides articles on reversing and exploiting SMM). Are you aware whether SMM is tested (for new functionality, for instance), and if so, how that is being done? Or is this done by using existing hardware setups? I do not have a lot of experience with low-level hardware. Thanks for your input :). Kind regards, Mick

9 months

Questions about Asus A88XM-E

by magiccat1＠protonmail.com

All, I have an Asus A88XM-E, and I am trying to install Coreboot on it. 1 ) The chip that came with the board says "GD25Q64(B)" (8192 kB, SPI). I think the chip definitely broken somehow. Everytime I tried to flashrom, it says Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x00000fff: 0xd0c ERASE FAILED! when I tried sudo flashrom -w build/coreboot.rom --programmer ch341a_spi, it says Verifying flash... FAILED at 0x00000000! Expected=0x5f, Found=0xff, failed byte count from 0x00000000-0x007fffff: 0xb5 Your flash chip is in an unknown state. I am having a hard time flashing back to original bios as well. Can I buy W25Q64FVAIG to replace? The chip says GD25B64BP1G . Is that caused by using 5 V to be broken? I only performed flashrom -w and flashrom -r . 2) For configuration, I copied this configuration: https://review.coreboot.org/cgit/board-status.git/tree/asus/a88xm-e/4.12-32… to .config and added the board. I have exported the vga bios from Linux using: cp /sys/devices/pci0000:00/0000:00:01.0/rom vgabios.bin . The above config does not work with make, it tries to go to a webpage for secondary payload, and that webpage is changed. Removing those two lines CONFIG_COREINFO_SECONDARY_PAYLOAD=y && CONFIG_TINT_SECONDARY_PAYLOAD=y will let me build the rom. When I do sudo flashrom -w build/coreboot.rom --programmer ch341a_spi, it sometimes says write done: Erasing and writing flash chip... Erase/write done. Verifying flash... FAILED at 0x00000000! Expected=0x5f, Found=0xff, failed byte count from 0x00000000-0x007fffff: 0xb5 Your flash chip is in an unknown state. When I boot with Coreboot, I see a black screen. I renamed vgabios.bin to pci1002,990c.rom, and I put that file in the ~/Coreboot/ folder. Thanks for helping out,

9 months

basic support for AMD APU

by Tom Psyborg

Hi Is there any basic code in coreboot tree for recent AMD APUs ? Specifically Bristol Ridge FX-9830P is of my interest, how much work is needed to get laptop booting it?

9 months

Proper way to obtain GbE.bin for Denverton atom

by Balaji Sivakumar

Hello Everyone, I am currently working on a custom Denverton board similar to the Intel Harcuvar board. I am working to enable the Intel Lan controller, Did anyone generate the GbE.binary(firmware) for the Intel Lan controller of denverton atom or should i check with Intel for binary? We are using flash descriptor and ME binaries integrated into the coreboot, similar way i am working to integrate the GbE binary as well part of coreboot to properly initialize the Lan controller. -- Thanks, Balaji

9 months

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coreboot January 2021