Dear everyone,
For my master project I will apply hardening techniques (sanitizers/CFI) to
System Mangement Mode (SMM). Now for my evaluation, I want to test code in
SMM and ideally cover all SMI handlers coreboot offers. However, in my
experience, System Management Interrupts (SMIs) rarely trigger and the
variety in SMIs is also rather low (testing via QEMU). I was wondering
whether anyone is familiar with testing such a low-level component. In the
coreboot repository, I couldn't find any tests related to SMM and looking
online also hasn't provided me any answers.
Is there anyone who has experience with similar problems or can perhaps
point me into the right direction, as I am inexperienced with testing such
low-level components.
I hope I've explained myself clearly, if not, please indicate so!
Kind regards,
Mick
Hello,
I am a new user of Coreboot who recently purchased a Protectli firewall with Coreboot pre-installed. The firewall is running PfSense that I installed on it. Everything was going ok for a few days until I started having issues with PfSense and now I am having problems getting PfSense to launch at all. I believe this is related to a hardware issue with the firewall. During the coreboot launch I am getting an infinite loop which is triggered at the following line:
cpu reset proxy stopped cpu 1
Sounds like an issue with the hardware to me. I believe I saw this same issue referencing cpu 2 as well. I have tried over a period of several weeks to boot up and I always get this message and then a loop back to the the coreboot initialization. At this point I cannot tell if this is a coreboot, pfsense, or hardware issue, and I am getting ready to just buy another firewall with pfsense already installed and I am hoping someone has the time to give me a brief idea of what might be going on here. I am fairly PC savy but am having difficulty drilling down to what might be driving this specific issue on the web. I do like your product and plan to purchase a PC with coreboot in the near future.
Thanks a lot for your time.
-Aaron
Sent with [ProtonMail](https://protonmail.com) Secure Email.
Dear coreboot community,
I have a Tiger Lake UP3 RVP and I try to build a working coreboot on it,
however facing an early stuck during CAR setup. Tried different approaches:
- native coreboot's CAR setup - the last seen post code is 0x26
- FSP-T CAR setup - the last seen post code is 0x7F (which is
TempRamInit Exit event according to FSP integration guide), FSP from
public repo, Client variant
Used microcode from original RVP firmware.
Are there any patches that I have to apply to make it working?
Best regards,
--
Michał Żygowski
Firmware Engineer
https://3mdeb.com | @3mdeb_com
Hi,
Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.
1 new defect(s) introduced to coreboot found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 1445764: Incorrect expression (CONSTANT_EXPRESSION_RESULT)
/src/soc/intel/broadwell/raminit.c: 155 in setup_sdram_meminfo()
________________________________________________________________________________________________________
*** CID 1445764: Incorrect expression (CONSTANT_EXPRESSION_RESULT)
/src/soc/intel/broadwell/raminit.c: 155 in setup_sdram_meminfo()
149 return;
150 }
151
152 memset(mem_info, 0, sizeof(*mem_info));
153 /* Translate pei_memory_info struct data into memory_info struct */
154 mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt;
>>> CID 1445764: Incorrect expression (CONSTANT_EXPRESSION_RESULT)
>>> "8 < 8" is always false regardless of the values of its operands because those operands are identical. This occurs as the logical first operand of "?:".
155 for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) {
156 struct dimm_info *dimm = &mem_info->dimm[i];
157 const struct pei_dimm_info *pei_dimm =
158 &pei_data->meminfo.dimm[i];
159 dimm->dimm_size = pei_dimm->dimm_size;
160 dimm->ddr_type = pei_dimm->ddr_type;
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
Hello Peter,
Thank you for your response!
Cool! And ambitious. :)
>
Yeah, the project is pretty hacky, to be frank, and will be limited to the
setup where SMRAM is from a0000h to bffffh.
In general coreboot makes an attempt to not go overboard with SMM code, in
> particular the QEMU board code may have almost none, to the point where
> it's far from representative for modern platforms.
>
Yes, I'm aware of coreboot's stance on SMM. If I recall correctly, QEMU
seemed to have trouble clearing the SMI_STS register. We will likely use
hardware to test the setup. You're confirming my fear related to testing
SMM in QEMU. I hope we will be able to see more SMM activity on a real
board, but I don't know what to expect, as I have trouble finding sources
that discuss how SMM is used in the "wild" (besides articles on reversing
and exploiting SMM).
Are you aware whether SMM is tested (for new functionality, for instance),
and if so, how that is being done? Or is this done by using existing
hardware setups? I do not have a lot of experience with low-level hardware.
Thanks for your input :).
Kind regards,
Mick
All,
I have an Asus A88XM-E, and I am trying to install Coreboot on it.
1 ) The chip that came with the board says "GD25Q64(B)" (8192 kB, SPI). I think the chip definitely broken somehow. Everytime I tried to flashrom, it says
Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x00000fff: 0xd0c
ERASE FAILED!
when I tried sudo flashrom -w build/coreboot.rom --programmer ch341a_spi, it says
Verifying flash... FAILED at 0x00000000! Expected=0x5f, Found=0xff, failed byte count from 0x00000000-0x007fffff: 0xb5
Your flash chip is in an unknown state.
I am having a hard time flashing back to original bios as well. Can I buy W25Q64FVAIG to replace? The chip says GD25B64BP1G . Is that caused by using 5 V to be broken? I only performed flashrom -w and flashrom -r .
2) For configuration, I copied this configuration:
https://review.coreboot.org/cgit/board-status.git/tree/asus/a88xm-e/4.12-32…
to .config and added the board. I have exported the vga bios from Linux using: cp /sys/devices/pci0000:00/0000:00:01.0/rom vgabios.bin .
The above config does not work with make, it tries to go to a webpage for secondary payload, and that webpage is changed. Removing those two lines CONFIG_COREINFO_SECONDARY_PAYLOAD=y && CONFIG_TINT_SECONDARY_PAYLOAD=y will let me build the rom. When I do sudo flashrom -w build/coreboot.rom --programmer ch341a_spi, it sometimes says write done:
Erasing and writing flash chip... Erase/write done.
Verifying flash... FAILED at 0x00000000! Expected=0x5f, Found=0xff, failed byte count from 0x00000000-0x007fffff: 0xb5
Your flash chip is in an unknown state.
When I boot with Coreboot, I see a black screen. I renamed vgabios.bin to pci1002,990c.rom, and I put that file in the ~/Coreboot/ folder.
Thanks for helping out,
Hi
Is there any basic code in coreboot tree for recent AMD APUs ?
Specifically Bristol Ridge FX-9830P is of my interest, how much work
is needed to get laptop booting it?
Hello Everyone,
I am currently working on a custom Denverton board similar to the Intel
Harcuvar board. I am working to enable the Intel Lan controller, Did
anyone generate the GbE.binary(firmware) for the Intel Lan controller of
denverton atom or should i check with Intel for binary? We are using flash
descriptor and ME binaries integrated into the coreboot, similar way i am
working to integrate the GbE binary as well part of coreboot to
properly initialize the Lan controller.
--
Thanks,
Balaji
Hi everyone,
Is there any chance to get this trivial commit merged?
https://review.coreboot.org/c/coreboot/+/45829
I've added description of missing payloads and links to
Documentation/payloads.md
Low priority, but would be nice to have.
Thanks,
bzt
