coreboot January 2013

coreboot@coreboot.org

32 participants
607 discussions

by coreboot

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

6 years, 2 months

EHCI debug port finder

by Carl-Daniel Hailfinger

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

6 years, 9 months

Dual SPI Flash adapter attempt 2.0

by Oliver Schinagl

Hi list(s), Here's my second attempt at routing the previously mailed png of my schema. It was a lot trickier to route then my previous version, but I think it worked out! As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1 should be 10k or ideally 100k, as Peter mentioned earlier. Hopefully there's no obvious mistakes and can start working on alternative layouts (so it is insert-able in different angles). DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow. That said, DRC check passes when I set the copper width/distance to 7mil's instead of the current 8 mils. I'm planning on having these PCB's manufactured by Seeed studio and their minimal width is much smaller. Minimum trace width: 6mil Minimum trace/vias/pads space : 6mil Minimum silkscreen width : 4mil Minimum silkscreen text size : 32mil I've used a grid size of 10mil and distances of 8 mils, as I didn't want to rely on the minimum of seed. The silkscreen I positioned using a grid size of 5 mil's however. Not sure what they mean with a 'minimum silkscreen text size' however. Anyhow, feedback greatly appreciated, so I can start working on alternative layouts :)

6 years, 11 months

#186: 3com 3c905tx / gpxe boot problem

by coreboot

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: just because) novice in the field, I encountered some problems with netbooting with coreboot. Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE} respectively. NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy slow! Although loading, the kernel is never able to start itself. Same kernel on HDU is no problem at all (GRUB2) Note: the gpxe-image is on the nic, coreboot payload is seabios. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186> coreboot <http://www.coreboot.org/>

7 years, 1 month

unsupported mb questions (amd fam10h)

by Roman Elshin

I try to get coreboot working with asrock 880g pro3 board. First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333? Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible to boot from sata. Are sb850 supported by coreboot? ----------------------------------------------------------------------- diff -urN a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c --- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14 21:49:54.000000000 +0400 @@ -94,7 +94,10 @@ rev = REV_SB800_A11; } else if (rev_id == 0x41) { rev = REV_SB800_A12; - } else { + } else if (rev_id == 0x42) { + rev = REV_SB800_A13; + } + else { die("It is not SB800 or SB810\r\n"); } diff -urN a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h --- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000 +0400 @@ -48,7 +48,7 @@ #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 - +#define REV_SB800_A13 0x13 #ifdef __PRE_RAM__ void sb800_lpc_port80(void); -------------------------------------------------------------------------

7 years, 7 months

Re: [coreboot] ASUS m5a88-v AGESA port (bulldozer)

by darkdefende＠gmail.com

Idwer Vollering writes: > Done. Thanks for attaching the log for me. Some recent commits to coreboot master seems to have solved my problem with the pci scan hang. Now I don't have to hack around it any more. However it still freezes after it's done (?) loading seabios. I have uploaded my changes to https://github.com/DarkDefender/coreboot if anyone want's to look at them. I've tried to enable more debugging options in the "OptionsIds.h" for AGESA but it doesn't seem to do anything. The asserts are triggered druing boot are still the same as before. I've tried to look at it but I didn't really understand what I should change to solve them.

7 years, 8 months

Looking for Linux messages (`dmesg`) and coreboot log of AMD Persimmon for comparison with ASRock E350M1

by Paul Menzel

Dear coreboot folks, I am planning on working on the ASRock E350M1 a bit. As it is similar to the AMD Persimmon board, it would be awesome to have the Persimmon logs for comparison. Could you please attach them to your reply with a note what GNU/Linux distribution you use and what Linux version. Thanks, Paul

7 years, 10 months

AMD Parmer/Thatcher: Remaining differences in `BiosCallOuts.c`

by Paul Menzel

Dear coreboot folks, after $ git show --stat 2892023fd422794bb82658dde3e8d489af2bdd55 commit 2892023fd422794bb82658dde3e8d489af2bdd55 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jan 17 12:04:08 2013 -0700 AGESA F15tn: Move callouts into northbridge wrapper There are currently too many things in the mainboard directories that are really more suited to being in the northbridge / southbridge wrappers. This is a start at moving some of those functions down into the wrappers. Move the bios callback functions into the northbridge/amd/agesa/family15tn directory from the mainboard directories. These can still be overridden by any mainboard just by updating the pointer in the callback table to point to a customized version of the function. Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2169 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> src/mainboard/amd/parmer/BiosCallOuts.c | 464 ++------------------------------------------------------------------------- src/mainboard/amd/parmer/BiosCallOuts.h | 55 +-------- src/mainboard/amd/thatcher/BiosCallOuts.c | 464 ++------------------------------------------------------------------------- src/mainboard/amd/thatcher/BiosCallOuts.h | 55 +-------- src/northbridge/amd/agesa/family15tn/Makefile.inc | 4 + src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c | 405 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h | 53 +++++++++ the following differences remain. $ diff -u src/mainboard/amd/{parmer,thatcher}/BiosCallOuts.c --- src/mainboard/amd/parmer/BiosCallOuts.c 2013-01-23 00:25:21.150153420 +0100 +++ src/mainboard/amd/thatcher/BiosCallOuts.c 2013-01-23 00:25:21.150153420 +0100 @@ -72,9 +72,9 @@ } /** - * AMD Parmer Platform ALC272 Verb Table + * AMD Thatcher Platform ALC272 Verb Table */ -const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { +const CODEC_ENTRY Thatcher_Alc272_VerbTbl[] = { {0x11, 0x411111F0}, {0x12, 0x411111F0}, {0x13, 0x411111F0}, @@ -92,9 +92,9 @@ {0xff, 0xffffffff} }; -const CODEC_TBL_LIST ParmerCodecTableList[] = +const CODEC_TBL_LIST ThatcherCodecTableList[] = { - {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, + {0x10ec0272, (CODEC_ENTRY*)&Thatcher_Alc272_VerbTbl[0]}, {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; Could these objects be named the same? @@ -165,33 +165,33 @@ /* Thermal Zone Parameter */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x35; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0E;//6 | BIT3; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; /* IMC Fan Policy temperature thresholds */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 105;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 60; /*AC1 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 105; /*critical threshold* in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; /* IMC Fan Policy PWM Settings */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ @@ -205,10 +205,10 @@ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x54; FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 1; /* PWM steping rate in unit of PWM level percentage */ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; @@ -221,12 +221,12 @@ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 80; /*critical threshold* in Celsius, 0xFF is not define */ FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 100; /* AL0 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ In Parmer most of this stuff seems to be set to 0. Do the values in Thatcher’s file be used for Parmer too? @@ -296,13 +296,15 @@ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ParmerCodecTableList[0]); + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&ThatcherCodecTableList[0]); /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */ oem_fan_control(FchParams_env); - /* sata configuration */ + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; Does the Parmer board have XHCI? } printk(BIOS_DEBUG, "Done\n"); So if there are no problems with that, first a patch to unify the object names should be made, then one to use Thatcher’s values for Parmer too and then moving everything to the northbridge directory. Thanks, Paul

8 years

[PATCH v2] spkmodem

by Vladimir 'φ-coder/phcoder' Serbinenko

A new version of spkmodem. This one doesn't lose the bit sync even if I disconnect the cable for the short time (but, of course data sent when no cable is attached is lost) -- Regards Vladimir 'φ-coder/phcoder' Serbinenko

8 years

FOSDEM 2013 - who else comes?

by Rudolf Marek

Hi all, As Carl-Daniel wrote we have a stand (two tables) at FOSDEM on 2,3rd February in Brussel. So far me and Carl-Daniel will come. I will arrive early on Friday and leave on Sunday evening. I will bring my boards with me (2?) and of course also F2A85-M. If anyone wants to come, please let us know. Thanks Rudolf

8 years

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coreboot January 2013