Configuration for Thinkpad T530
by Yannik Catalinac
Hello,
I'm trying to configure coreboot for a Lenovo Thinkpad T530 and I need help because for some parts I didn't find any information on the internet.
The T530 (Machine Type Model: 24297ZG) has the the following specifications:
Intel Core i5-3230M with Intel HD Graphics 4000
NVIDIA NVS 5400M
AUO B156HW01 V.4 FullHD Display
Samsung SSD 840 Pro
16 GB RAM
I want to use a Docking Station.
In the future I want to upgrade the following:
Intel Core i7-3940XM
more and faster RAM
eGPU
I'm going to install only some Linux distributions (no Windows).
I think I will install OpenSuse which has a modified GRUB2 bootloader, where you can choose from which kernel or snapshot you would like to boot (maybe this information is important for configuring coreboot).
Inside the Linux distribution, with graphical environment KDE, I would like to install some virtual machines with QEMU/kvm and there could be also a Windows virtual machine.
I configured everything until now with 'make menuconfig' as listed bellow. Could you please give me some advise which settings I should change and why I should change them. I also wrote some questions behind a few configuration settings (marked with '#####') which I don`t understand. I would really appreciate your help.
1 General setup
1.1 () Local version string
1.2 (fallback) CBFS prefix to use
1.3 Compiler to use (GCC)
1.4 [ ] Allow building with any toolchain
1.5 [ ] Use ccache to speed up (re)compilation
1.6 [ ] Generate flashmap descriptor parser using flex and bison
1.7 [ ] Generate SCONFIG & BINCFG parser using flex and bison
1.8 [*] Use CMOS for configuration values
1.9 [ ] Load default configuration values into CMOS on each boot
1.10 [*] Compress ramstage with LZMA
1.11 [*] Include the coreboot .config file into the ROM image
1.12 [*] Create a table of timestamps collected during boot
1.13 [ ] Print the timestamp values on the console
1.14 [*] Allow use of binary-only repository
1.15 [ ] Code coverage support
1.16 [ ] Undefined behavior sanitizer support
1.17 [ ] Update existing coreboot.rom image
1.18 [ ] Add a bootsplash image
2 Mainboard
2.1 Mainboard Vendor
2.1.1 Lenovo
2.2 Mainboard model
2.2.1 TinkPad T530
2.3 ROM chip size
2.3.1 12 MB
2.4 (0x100000) Size of CBFS filesystem in ROM
2.5 () fmap description file in fmd format
3 Chipset
3.1 -*- Enable VMX for virtualization
3.2 [*] Set lock bit after configuring VMX
3.3 Include CPU microcode in CBFS (Generate from tree)
3.4 () Microcode binary path and filename
3.5 [*] Ignore vendor programmed fuses that limit max. DRAM frequency
3.6 [*] Ignore XMP profile max DIMMs per channel
3.7 Flash locking during chipset lockdown (Don't lock flash sections)
3.8 [*] Lock down chipset in coreboot
3.9 [*] Beep on fatal error
3.10 [*] Flash LEDs on fatal error
3.11 [*] Support bluetooth on wifi cards
3.13 [*] Add Intel descriptor.bin file
3.14 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin) Path and filename of the descriptor.bin file
3.15 [*] Add Intel ME/TXE firmware
3.16 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin) Path to management engine firmware
3.17 [*] Verify the integrity of the supplied ME/TXE firmware
3.18 [*] Strip down the Intel ME/TXE firmware
3.19 [*] Add gigabit ethernet firmware
##### If I read correctly I need that for internet connection and this bianry has just some configuration in it and no excecutable? So this should be not a privacy concerning thing?
3.20 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin) Path to gigabit ethernet firmware
3.21 [*] Add EC firmware
3.22 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/ec.bin) Path to EC firmware
3.23 [*] Lock ME/TXE section
3.24 Bootblock behaviour (Always load fallback)
4 Devices
4.1 Graphics initialization (Use native graphics init) --->
4.2 Display ---> Framebuffer mode (Legacy VGA text mode)
##### I have no idea what to choose here
4.3 [*] Enable PCIe Clock Power Management
##### I read it should increase battery runtime
4.4 [*] Enable PCIe ASPM L1 SubState
##### I read it should increase battery runtime
4.5 [ ] Early PCI bridge
4.6 (0x0000) Override PCI Subsystem Vendor ID
##### What?!
4.7 (0x0000) Override PCI Subsystem Device ID
##### And again: What?!
4.8 [*] Add a VGA BIOS image
##### I'm not sure if I need a VGA Option ROM. In which cases I need it? What disadvantage do I have if I do not integrate a VGA Option ROM? Will I see GRUB when I boot Linux? How could you value that binary in case of privacy and security?
4.9 (pci8086,0106.rom) VGA BIOS path and filename
4.10 (8086,0106) VGA device PCI IDs
4.11 [*] Add a Video Bios Table (VBT) binary to CBFS
##### Same questions as for the VGA BIOS image
4.12 (src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt) VBT binary path and filename
4.13 [ ] Enable I2C controller emulation in software
5 Generic Drivers
5.1 [ ] AS3722 RTC support
5.2 [ ] Enable protection on MRC settings
5.3 [ ] Disable Fast Read command
5.4 [ ] Serial port on SuperIO
5.5 [ ] Oxford OXPCIe952
5.6 (0x0) UART's PCI bus, device, function address
##### What is that? What I have to insert?
5.7 [ ] USB 2.0 EHCI debug dongle support
5.8 [ ] Support for Vital Product Data tables
5.9 [*] Support Intel PCI-e WiFi adapters
##### If enabled, will this include a binary in the coreboot image?
5.10 [*] PS/2 keyboard init
5.11 [ ] Silicon Image SIL3114
5.12 [ ] TI TPS65913 support
5.13 [ ] TI TPS65913 RTC support
6 Security
6.1 Verified Boot (vboot) --->
6.2 Trusted Platform Module ---> [*] Deactivate TPM
##### I disabled it because of security/privacy reasons. Any disadvantages when I disable it?
6.2.2 [ ] Output verbose TPM debug messages
6.2.3 [ ] Enable Delay Workaround for TPM
7 Console
7.1 [*] Squelch AP CPUs from early console.
7.2 [ ] spkmodem (console on speaker) console output
7.3 [*] Use onboard VGA as primary video device
##### On coreboot mailinglist I read: make sure you enable ONBOARD_VGA_IS_PRIMARY in your config, otherwise your integrated graphics will be disabled and you'll lose eGPU hotplug.
7.4 [ ] Network console over NE2000 compatible Ethernet adapter
7.5 [*] Send console output to a CBMEM buffer
7.6 (0x20000) Room allocated for console output in CBMEM
7.7 [ ] SPI Flash console output
7.8 Default console log level (0: EMERG) --->
##### I read that this should decrease boot time. What disadvantages do I have with this setting?
7.9 [ ] Don't show any POST codes
##### What?
7.10 [ ] Store post codes in CMOS for debugging
##### What?
7.11 [ ] Show POST codes on the debug console
##### What?
7.12 [*] Send POST codes to an external device
##### What?
7.13 Device to send POST codes to (None)
##### What?
7.14 [*] Send POST codes to an IO port
##### What?
7.15 (0x80) IO port for POST codes
##### What?
8 System tables
8.1 [*] Generate SMBIOS tables
9 Payload
9.1 Add a payload (SeaBIOS) --->
9.2 SeaBIOS version (1.11.2) --->
##### Or should I choose master?
9.3 (10) PS/2 keyboard controller initialization timeout (milliseconds)
9.4 [ ] Hardware init during option ROM execution
9.5 () SeaBIOS config file
9.6 () SeaBIOS bootorder file
9.7 [ ] Add SeaBIOS sercon-port file to CBFS
9.8 (-1) SeaBIOS debug level (verbosity)
9.9 [ ] Add a PXE ROM
9.10 Payload compression algorithm (Use LZMA compression for payloads) --->
9.11 [ ] FIT support
9.12 [*] Use LZMA compression for secondary payloads
9.13 Secondary Payloads --->
9.13.1 [*] Load coreinfo as a secondary payload
9.13.2 [ ] Load Memtest86+ as a secondary payload
9.13.3 [*] Load nvramcui as a secondary payload
9.13.4 [ ] Load tint as a secondary payload
10 Debugging
10.1 [ ] Halt when hitting a BUG() or assertion error
10.2 [ ] Output verbose CBFS debug messages
10.3 [ ] Output verbose RAM init debug messages
10.4 [ ] Output verbose SMBus debug messages
10.5 [ ] Output verbose SMI debug messages
10.6 [ ] Debug SMM relocation code
10.7 [ ] Output verbose SPI flash debug messages
10.8 [ ] Trace function calls
10.9 [ ] Debug boot state machine
10.10 [ ] Compile debug code in Ada sources
10.11 [ ] Configure image for EM100 usage
Is there anything else I should take care of with a T530?
Thanks for reading until here ;)
Greetings
5 hours, 21 minutes
No GRUB/Graphical boot-output on x4x chipset series with PCIe GPU
by akjuxr3＠dismail.de
I have installed coreboot on 2 different x4x boards. Both with intel G41 chipset and attached GPU to the PCIe slot (so probably not an issue with missing gpu-bios file because the gpu-bios of the PCIe card is been used).
Work-timeline:
1. I got a clean ssd and installed linux on it using the OEM bios. The typical graphical Grub output was visable and i was able to change configuration in it by pressing 'e' at boot.
2. I used this installed linux and git cloned coreboot (today), built everything and flashed with flashrom the coreboot image.
3. Turned the computer fully off. Turned it on and grub graphical output is gone.
I have this issue since i can think of it.
How i build coreboot:
make menuconfig, choose mainboard-vendor, mainboard model, press esc and confirm saving. Then build.
5 hours, 28 minutes
Google Summer of Code 2019
by Patrick Georgi
Dear coreboot community,
I'm preparing the application to have coreboot participate in this
year's Google Summer of Code.
There are two things we should think about until early February for this:
1. We'll need some project proposals, for which I started
https://review.coreboot.org/c/coreboot/+/30972
2. I need to specify the number of mentors we expect to have at hands.
This needn't be a guaranteed commitment, but a rough idea would be
good.
As a mentor-candidate, if we make it into GSoC, we'd try to match you
to a student with a project matching your interest and knowledge.
You'd discuss their plan, follow up at least weekly on their progress
and support them in their process to join and grow in the community.
The time frame would be early May to early September:
https://developers.google.com/open-source/gsoc/timeline.
So if you're interested in growing our community, please speak up :-)
Thanks,
Patrick
--
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Geschäftsführer: Paul Manicle, Halimah DeLaine Prado
19 hours, 38 minutes
Manual microcode update for G505s still needed? e.a.
by Anac
Dear all,
Now with Coreboot version 4.9, is it still recommended to manually
update AMD microcodes for Lenovo G505s as described here? Or is Coreboot
4.9 up-to-date for using a G505s as a Qubes station?
http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#AMD_microcode_up...
How do you handle the AMD GPU AtomBIOS blobs?
https://github.com/g505s-opensource-researcher/g505s-atombios#corebootrom...
may be very clear to experts, but I don't get it. It reads "use one of
these commands:"
1) Adding VGABIOS to coreboot.rom
2) Removing VGABIOS from coreboot.rom
3) Printing coreboot.rom memory map
Which one should I use? Probably No.1. But there are 2 files for my
G505S with discrete HD-8570M (pci1002,990b.rom and pci1002,6663.rom).
Which one should I add? Both, separated by space? Then the command would
look like that?
./util/cbfstool/cbfstool ~/coreboot.rom add -f ~/pci1002,990b.rom
pci1002,6663.rom -n pci****,****.rom -t optionrom
That looks odd. Doesn't it?
What about TPM? Qubes recommends TPM in their system requirements since
it is required for 'Anti Evil Maid'. But Coreboot configuration (make
nconfig) does not allow to activate TPM. Am I doing something wrong or
is TPM just really not an option?
Best regards and thank you!
Anac
1 day, 3 hours
To modify MCTRL.SPDDIS of Intel Denvertion in coreboot
by Hilbert Tu(杜睿哲_Pegatron)
Hi,
Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot?
The Intel Denverton blocks write permission to address A0~AE due to security concern of DIMM SPD, but this also restricts the write access to generic EEPROM access in our platform. So I need to modify the SPDDIS bit to bypass the protection. But I don’t know how to do that in Coreboot. Please help and thanks in advance.
-Hilbert
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2 days, 18 hours
Menu time-out missing when GRUB is loaded quickly and `at_keyboard`
by Paul Menzel
Dear GRUB folks,
When the module `at_keyboard` is directly into the GRUB image
(`--modules`), and GRUB is loaded really quickly, then the timer, which,
after counting down to 0 (`GRUB_TIMEOUT`), starts the selected entry, is
not shown.
I noticed this issue on the ASRock E350M1 with coreboot and a small GRUB
payload, and a PS/2 keyboard connected. Due to the missing time-out, I
manually have to confirm the selected entry. By chance, the keyboard
wasn’t connected setting up the system somewhere else, and that made it
work as expected. So, it looks like, it’s related to `at_keyboard`, and
some race, because the bigger default GRUB payload also does not show
the problem.
Luckily, it’s easily reproducible with GRUB’s standard
`default_payload.elf` and QEMU.
Please find the instructions below to reproduce the issue.
$ git clone https://review.coreboot.org/coreboot
$ cd coreboot
$ # save attached grub.cfg in the directory
$ util/scripts/config -e PAYLOAD_GRUB2
grep: .config: Datei oder Verzeichnis nicht gefunden
$ util/scripts/config -e GRUB2_INCLUDE_RUNTIME_CONFIG_FILE
$ util/scripts/config -e GRUB2_MASTER
$ util/scripts/config -e CONFIG_COREBOOT_ROMSIZE_KB_2048 # default
of 512 KB too small for GRUB payload
$ util/scripts/config -e ANY_TOOLCHAIN
$ # or: make crossgcc-i386 CPUS=`nproc`
$ make olddefconfig
$ make -j`nproc`
$ qemu-system-x86_64 --version
QEMU emulator version 3.1.0 (Debian 1:3.1+dfsg-2+b1)
Copyright (c) 2003-2018 Fabrice Bellard and the QEMU Project
developers
$ qemu-system-x86_64 -M pc -bios build/coreboot.rom -serial stdio
*No* time-out is shown. Telling QEMU to emulate a USB keyboard,
indirectly disabling the PS/2 keyboard, the time-out *is* shown.
$ qemu-system-x86_64 -M pc -bios build/coreboot.rom -serial stdio \
-usb -device usb-kbd
Not including `at_keyboard` directly in GRUB’s “core image”, modules
loaded automatically, the time-out is also shown.
`set debug=at_keyb` did not show anything interesting.
Can you reproduce that, and see what the problem is?
Kind regards,
Paul
PS: Please find the instructions to build GRUB as a coreboot payload
done by coreboot’s Kconfig system automatically, and how put it into the
coreboot filesystem CBFS.
```
$ git clone https://git.savannah.gnu.org/git/grub.git/
$ cd grub
$ git describe --tags --dirty
grub-2.02-238-ga791dc0e3
$ ./autogen.sh
$ ./configure --with-platform=coreboot
$ make default_payload.elf # this includes `at_keyboard`
$ cp default_payload.elf my/coreboot/folder/
$ cd my/coreboot/folder/
$ build/cbfstool build/coreboot.rom print
$ build/cbfstool build/coreboot.rom remove -n fallback/payload
$ build/cbfstool build/coreboot.rom add-payload -f payload.elf -n
fallback/payload -c lzma
```
Kind regards,
Paul
3 days, 13 hours
Coreboot doesn't POST on ASUS KCMA-D8
by espionage724＠posteo.net
I have a KCMA-D8 motherboard with two Opteron 4226s, and 6x4GB (24GB) Hynix HMT151R7BFR4C-H9 RAM sticks. All my attempts of getting Coreboot to POST with this board so far haven't worked. I'm compiling Coreboot from Git (master branch), and can build it without issue. A pre-built Libreboot ROM (20160907) POSTs and boots fine.
For Coreboot's config, I've tried including/excluding CPU microcode updates, along with some less important-sounding options. For hardware, I've tried unplugging everything external (KB/mouse), my GPU (RX 580), and only had a single RAM stick in (slot A1). I've also tried a single CPU being powered (kept the 2nd CPU in but only had a single 4-pin CPU going to the 1st CPU).
Can anyone else confirm Git builds of Coreboot booting on this board, or provide any tips as to anything I could be missing?
I see this issue https://ticket.coreboot.org/issues/151 but there's a board status months after that that looks like it boots: https://review.coreboot.org/cgit/board-status.git/tree/asus/kcma-d8/4.7-7...
4 days, 16 hours
Coreboot build process with gcc 8.1
by Salvatore Bellizzi
Hi,
I have a question reguarding the build process.
Since crossgcc has been updated and gcc is now at version 8.1 I always
encounter an error when building coreboot:
coreboot/src/console/vtxprintf.c:102: undefined reference to
'__udivmoddi4'
Since coreboot uses crossgcc and its own libgcc libraries, I figured
that the __udivmoddi4 function has not yet been implemented.
Anyway I have incurred in this failure several times and even with the
latest 4.9 release. Shouldn't I be able to build at least this latest
release using unmodified crossgcc or am I missing something else?
thanks,
salvatore
6 days, 5 hours
Depreciating FSP1.1 on soc/intel/quark along with util/checklist
by Arthur Heymans
Dear community
soc/intel/quark Has 2 FSP versions hooked up, both FSP1.1 and FSP2.0.
Maintaining the code for both versions does increase the developers
load.
So my question is can we remove the older FSP1.1 implementation?
Is someone using this board in a setup that cannot be obtained with
FSP2.0?
There is only one board that has both FSP versions hooked up which can
be selected in menuconfig, so we wouldn't be dropping a board.
FSP1.1 on the Intel Galileo (only board using soc/intel/quark) is also
the only board that uses util/checklist. This utility allows to check
if certain linker symbols are found. Supposedly it allows board porters
to gradually work towards with a checklist of things to do while
in reality its just an extra burden to maintain a list of symbols.
So can we remove util/checklist? [1] does that.
Kind regards
Arthur Heymans
[1] https://review.coreboot.org/c/coreboot/+/30691
1 week, 1 day
