I own an Acer Aspire VN7-572G and have not been impressed with its OEM
firmware. After discovering that it does not utilise Intel's Boot Guard
technology, that several Skylake and Kabylake laptops (it has a Skylake
chip, but I read that the platforms are similar) have received successful
coreboot ports and reading the porting guide on the wiki, I figured that I
could give porting coreboot to my laptop a shot.
When I was done, I figured that I had an image that might boot so I flashed
it to my laptop with a Raspberry Pi and a SOIC clip. However, here's what
a) It powers on quietly, as expected;
b) The backlight and power LED light up;
c) The fans spin up to high and then it stays that way. It does nothing
else. The display is dark too.
After 15 minutes and a second attempt, I figured that I could no longer
blame anything on a long first boot-up and gave up and flashed back to
Now, in all honesty I should have tried first without cleaning Intel ME but
I find it so much more likely that I did something wrong than that cleaning
ME was the sole problem.
Can anyone advise me on how to continue? My code is here:
As I understand it, the only thing missing with regard to nvidia dGPUs on
Coreboot are the ACPI calls to turn them on and off at run-time, which is
what Optimus is. Things like DRI_PRIME and similar work just fine as long
as the dGPU is running, even under nouveau.
What is the current status of the work to get nvidia Optimus working? From
what I gather there have been a couple of attempts and a recent restart,
but I don't know what the current status of this work is.
I have heard that some laptops currently have the option to switch the dGPU
on or off at boot-time. For which ones does this work?
If the work on Optimus is completed, what laptops are most likely to
support it? My expectation is that turning the GPU on or off may be
different for different laptops, even though the ACPI calls are the same,
and so may not work everywhere.
A week ago I wrote here about my problems trying to port coreboot to
my board. Unfortunately I am still no closer to booting.
In the meantime I flashed my new chip with my OEM firmware backup. It
boots; then I flashed my patched IFD (for chip ID and flash unlock)
and it still boots. So it's not chip compatibility or corrupted
The only sign of life I got is the bootblock banner left in the SPI
console. My PCI POST card is showing nothing, but knowing that it sits
on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not
knowing if it needs software init to work, I am now trying to pull
POST codes off the LPC bus over the TPM header, using an Arduino Due.
Do I have to add some early init to have port 80 accesses sent to LPC
bus for this to work?
Thanks for your help
Dear coreboot folks,
As some you know we at OSF are working on enabling Xeons in coreboot. We have
recently uploaded Skylake-SP which goes in src/soc/intel/skylake_sp. At the
same time we are working on enabling next generation SP processor. I was
wondering what may be a good way to structure the code. It feels wrong to just
throw code into src/soc/intel especially for systems with discrete PCH.
I'd like to hear opinions and discuss what may be a good way to structure and
organize the code. Here is what we want to achieve:
* Make code modular
It looks like certain things are similar to all -SP variants and it makes
sense to share that code rather than copy-paste.
* Allow same motherboard to host different CPU (and potentially different PCH)
The practical thing here is that some server boards support two generations
of CPUs that are pin-compatible. However, chip code is different. PCH may be
same or different.
* Did I already say eliminate/decrease copy-pasta?
Here is a structure that I came up with so far (patch stack ending with 39017)
├─ Kconfig # baseline of config
├─ include/ # common headers
├─ common/ # true common code such as IIO stacks code, ACPI tables
│ ├─ include/ # cpu/northbridge defines specific to given model
│ ├─ Kconfig # whatever overrides from common we need
│ └─ *.c # code that implements specific platform bits
│ ├─ include/ # same
│ ├─ Kconfig # same
│ └─ *.c # same
Now then, the "common" xeon_sp code may be placed in src/northbridge. We
probably should add Lewisburg C62x code in src/southbridge as well. Thoughts?
Alternatively, we can place everything in soc/intel/ and put Xeon server common
code in soc/intel/common/block/ or similar. This may be easiest way
but fells messy.
Is there any other way with pros and cons?
To build Coreboot on Minnowboard MAX - A2, is the following link the updated one or any other latest steps ?
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I am Harshavardhan Unnibhavi, a first year PhD student at the University of
Edinburgh, working in security and storage systems. I am interested in
contributing to Coreboot through GSoC 2020 program.
I am interested in the project to Learn hardware behavior from IO and
memory access logs. The project ideas page doesn't have a very good
description of how to get started. Hence I have a few questions:
1) What contributions, if any, are required to get selected to work on this
2) I am comfortable with C, Python, Git and have a decent amount of machine
learning experience as well. What other skills do I need? I have a decent
knowledge of how the driver works to access hardware resources.
Any other things I should be aware of?
Looking forward to hearing from you.
Can anyone help me regarding the instructions to build coreboot 4.11 release for Harcuvar platform.
I am not able to see the microcode, FSP_T and other settings in make menuconfig (for the Harcuvar platform).
I am already using the settings suggested under the doc "denverton-ns-coreboot-pc-001-release-notes-v1-3 " to build the coreboot version number 4.9.
I am facing the given problem when I am trying to migrate to coreboot-4.11 release (while using the same steps).
Thanks in advance,
I currently cannot boot Linux (Fedora 31) using either TianoCore payload on
a skylake laptop. I've received the error message "NMI watchdog: watchdog
detected hard lockup on CPU #" once, but it's otherwise just been
I've tried enabling the legacy 8254 timer, but I don't think it helped.
This is for a port in progress that did previously boot properly.
Does anyone have an idea what might be wrong with it?
I have a complete Supermicro server system with a H8SCM-F motherboard inside that I'd like to install Coreboot on.
According to the old wiki, it appears to have been pretty well supported (https://www.coreboot.org/Board:supermicro/h8scm).
I looked through the mailing list and found a few threads regarding issues with the board, but those were mostly older or related to the BMC (IPMI) on this reversion, which I do not intend to use at all.
However, while building the payload, I noticed that I couldn't select this model, since there are only Supermicro Intel boards available.
How would I go about flashing my board with the latest Coreboot (if that makes sense)?
Thank you in advance for any hints!
Mr Chromebox uses a script to install Core Boot onto Chrome Book without
opening the laptop, or attaching a PROM; (CH341a, Ponoma 5250 Test Clip,
F to F Breadboard Jumper Cables.)
Is using a Script without using hardware PROM, and so on, like Mr.
Chromebox does with a Chrome Book?
Thanks for what you are doing. and for your replies.