coreboot February 2017

coreboot@coreboot.org

66 participants
212 discussions

Lenovo T410 Coreboot
by A. Veek 14 Dec '18

14 Dec '18

2 1

Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett 12 Sep '17

12 Sep '17

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

5 6

Re: [coreboot] KGPE-D16 BMC Port Offer (was: Fund a TALOS Secure Workstation as coreboot build system)
by Timothy Pearson 17 Apr '17

17 Apr '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 01/19/2017 11:36 AM, Martin Roth wrote: > Hey Merlin, > I was taking and keeping track of the pledges for Talos, so I'd be > happy to continue. > > Martin I just wanted to bring this back up for discussion. Raptor is chipping in funding for over half of the development work, and Martin is matching pledges, so if there's interest in this port your contributions will go a long way, but it still depends on community interest. Are you willing to contribute to this development project? It is a limited time offer, so the quicker we can reach the relatively low goal to get this work underway the better. :-) Thanks! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYijUnAAoJEK+E3vEXDOFbQKAIAKPqeHZylATs3aZXC2QeTmUG p0bnwfU4G+0qkXEwApoYk+y8WRKEkhBsug5EvzEXw65fAAmwi4COVjUBvm2l9kUI m3/51sfrZRpo+H8c1lXld0WiwomTGapm9FX3rqAjLZn354TOqnrfoGYoJQC+ovKm 0AYXCGN8fmWkr6nTj9Q1tWwxEXrRv48YudF8bDFZhbMjOswnagNzImQNTC6wLgnY +7UyqBgpihc8vh3GoGuPQT1mNpAtUwv1PS8HFGnDO86zW9gWB7+xHEGBhMyy+Rys CTNWkI15X4dy8pz6XIsqjuBNSUcgTnVVAelecdm1BfykpgSyPyOf/39JQc/O41M= =HzeR -----END PGP SIGNATURE-----

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CPU Turbo [KGPE-D16]
by Taiidan＠gmx.com 15 Mar '17

15 Mar '17

I am wondering as to: * Why 6274 cpu refuses to turbo to the second turbo state with half of the cores in use (it stops around 100mhz before the first turbo state) * Is it possible to force enable second turbo state for all cpu cores, assuming adequate cooling? Or is it controlled on the CPU itself? Off topic but would rather not make another thread: * Does NUMA ram alignment matter performance wise with only one physical CPU? (RAM being split half and half per core set at the moment) * Does anyone know where I could get a reasonably priced 6287SE or 6284SE? or (even better) an engineering model of 62xx?

2 6

Where to get ME image/flash descriptors for the x220?
by Taiidan＠gmx.com 06 Mar '17

06 Mar '17

I want generic ones, not the sketchy extracted ones that came with my fleabay laptop. The lenovo website doesn't work on my computer BTW

4 5

SPI Flash Writeprotect
by Naveed Ghori 02 Mar '17

02 Mar '17

Hi all, Does Coreboot write to the flash chip it resides on? Can this be disabled? Verify of the SPI bios chip fails once the unit has booted up at least once. Best Regards, Naveed Naveed Ghori | Lead Firmware & Driver Engineer DTI Group Ltd | Transit Security & Surveillance 31 Affleck Road, Perth Airport, Western Australia 6105, Australia P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.ghori(a)dti.com.au<mailto:naveed.ghori@dti.com.au> Visit our website www.dti.com.au<http://www.dti.com.au> The information contained in this email is confidential. If you receive this email in error, please inform DTI Group Ltd via the above contact details. If you are not the intended recipient, you may not use or disclose the information contained in this email or attachments.

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Screenshot of payload cbui (coreboot user interface) by siro
by Paul Menzel 28 Feb '17

28 Feb '17

Dear coreboot folks, Today I tried cbui [1], the new payload written by siro (Patrick) using the single-header ANSI C GUI library *Nuklear* [2]. With QEMU there are problems when using qemu/q35, but trying it on the Lenovo X60 it worked like a charm (I loaded it from GRUB). Please find a picture attached. In both halves there are some horizontal black lines. But I guess that’s related to the native graphics initialization. So, please test and send commits to siro. Awesome job siro! Thanks, Paul [1] https://github.com/siro20/coreboot/commits/cbui [2] https://github.com/siro20/nuklear

1 0

Re: [coreboot] How to reduce formal issues with new contributions from corporations?
by Paul Menzel 28 Feb '17

28 Feb '17

Dear Julius, Am Montag, den 27.02.2017, 13:32 -0800 schrieb Julius Werner: > I don't think it's helpful to single out "corporate developers" as the > black sheep that submit all the style violations. Every contributor, paid > or hobby, new or long-time, needs to pay attention to the project > guidelines equally. Everyone overlooks stuff some time, and it's normal > especially for new contributors to not be quite that familiar with > everything yet. I certainly didn’t mean it that way. I didn’t want to single out anyone as the black sheep. I apologize, if I offended anyone. I totally agree with your view. My focus on corporate developers was motivate by the following two things. 1. Corporate developers certainly contribute most of the commits and code. 2. I believe and assume corporations have *additional* ways to reach “their” developers. > Its our responsibility as reviewers (especially those of us with +2 > rights) to educate them and make sure the rules are followed before a > patch can get submitted. > > That said, I do agree that we have a lot of potential in making this easier > and more consistent for everyone involved. I think the best tool for that > is more automated checking... like that recent idea to make Jenkins add the > checkpatch result visibly to its Verified+1 message. > > I'm not sure if the "where" of the guidelines really makes much of a > difference... maybe we should just make them more discoverable either way? > Could we put a big orange "please ensure that this patch conforms to the > style guidelines at ..." banner in Gerrit somewhere near the submit button? Most people push the commits from the command line I guess, so that – especially in the beginning – they won’t even access the Web interface? For corporations the following ideas came to my mind. The assumption is that in corporations people are higher to see the colleagues in person or to be in the same building. 1. In each division there is some kind of QA person “holding the hands” for the first commit. 2. Before somebody starts working on coreboot there is a small introduction by a colleague already familiar with the guidelines. 3. Do for example Intel, Google or Siemens have documents (tutorials, videos, presentations) they could share? Would it make sense to create those? […] Regarding improving the documentation, I guess everyone agrees (and nobody wants/likes to do it). In my opinion the easiest way would be to copy as much as possible from other project (like the Linux kernel). Though that should be discussed separately. Thanks, Paul

1 0

board status: REACTS uploads incomplete console messages for Asus KGPE-D16
by Paul Menzel 28 Feb '17

28 Feb '17

Dear Timothy, dear coreboot folks, Looking through the board status logs, I noticed that at least for the Asus KGPE-D16 the coreboot console message (ramstage) are incomplete [1]. Searching for the string `Show resources in subtree`, shows that it happened between the following two reports uploaded several months ago. ``` 3768284a9 asus/kgpe-d16/4.4-292-g9891b4a/2016-05-20T02_11_58Z # good [2] ac209a115 asus/kgpe-d16/4.4-343-g1716375/2016-05-30T13_15_24Z # bad [3] ``` The lines dropped down from over 3.000 to under 1.000. As some uploads are “missing” in between, I guess some maintenance work was done on the test stand causing the regression. It’s also not a code issue, as Daniel and I get the full logs with no issues [4]. It’d be great if the test stand could be checked, and repaired. Thanks, Paul [1] https://review.coreboot.org/cgit/board-status.git/diff/asus/kgpe-d16/4.5-10… [2] https://review.coreboot.org/cgit/board-status.git/commit/?id=3768284a9 [3] https://review.coreboot.org/cgit/board-status.git/commit/?id=ac209a115 [4] https://review.coreboot.org/cgit/board-status.git/commit/?id=8e7fe74b18ecd9… [5] https://www.raptorengineering.com/coreboot/autotest/logs/1488182375-3-18503…

1 0

No external PCIe GPU possible/working on Gigabyte g41m-es2l
by qma ster 28 Feb '17

28 Feb '17

Maybe to fix this PCIe GPU issue he just needs to edit a ./coreboot/src/device/Kconfig file? ./coreboot/src/device/Kconfig change config MULTIPLE_VGA_ADAPTERS bool default n to config MULTIPLE_VGA_ADAPTERS bool default y and completely rebuild the coreboot I enabled these options for my G505S laptop with both integrated/discrete graphic, however I am not a gamer so can't notice if there is any positive effect from this option. But maybe this option will significantly improve the thread starter's eGPU experience? What do you think ?

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coreboot February 2017