March 2014 - coreboot - mail.coreboot.org

Re: [coreboot] No VGA output on e350m1 after flashing. what to do?

by Reiner Luett

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.5... You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

1 year, 8 months

5
6
0 / 0

#95: Run coreboot in VirtualBox

by coreboot

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

4 years, 5 months

2
8
0 / 0

Re: [coreboot] Wyse S10 Geode GX2

by andrew＠cogman.info

Hi Jaime, Many thanks for sending me the VSA, it looks like my attempt to use the extracted one was the problem. I don't think I understand enough yet to see why what I was trying to do was wrong! I can confirm, that with your VSA, coreboot boots correctly on an S10 with SeaBIOS and loads (in this case) Slackware perfectly as below. I haven't got gxfb setup so there is no video at the moment, I'll start to run some tests tomorrow and let you know how I get on. Thanks, Andrew boot_log: coreboot-4.0-5512-g6e56de3 Mon Feb 17 19:03:04 GMT 2014 starting... done cpuRegInit Ram1.00 Ram2.00 sdram_set_spd_register Check DIMM 0 Check DIMM 1 Check DDR MAX AUTOSIZE DIMM 0 Check present MODBANKS FIELDBANKS SPDNUMROWS SPDBANKDENSITY DIMMSIZE BEFORT CTZ TEST DIMM SIZE>7 PAGESIZE MAXCOLADDR >11address test RDMSR CF07 WRMSR CF07 ALL DONE AUTOSIZE DIMM 1 Check present set cas latency set all latency MSR MC_CF8F_DATA (20000019) value is 18000108:696332a3 set emrs set ref rate Ram3 sdram_enable step 2 sdram_enable step 3 sdram_enable step 4 sdram_enable step 6 sdram_enable step 7 sdram_enable step 8 RAM DLL lock Ram4 ram setup done Trying CBFS ramstage loader. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (139264 bytes), entry @ 0x100000 coreboot-4.0-5512-g6e56de3 Mon Feb 17 19:03:04 GMT 2014 booting... clocks_per_usec: 366 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.3: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.3: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device >> Entering northbridge.c: enable_dev with path 6 >> Entering northbridge.c: pci_domain_enable Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10077014:00003500 sizeram: sizem 0x200 SysmemInit: enable for 512MBytes SysmemInit: MSR 0x10000028, val 0x2000001f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10077014:00003500 sizeram: sizem 0x200 SMMGL0Init: 536739840 bytes SMMGL0Init: offset is 0x40400000 SMMGL0Init: MSR 0x10000026, val 0x2dfbe040:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10077014:00003500 sizeram: sizem 0x200 SysmemInit: enable for 512MBytes SysmemInit: MSR 0x40000029, val 0x2000001f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000040:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x11FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 Enabling cache GLPCI R1: system msr.lo 0x00100130 msr.hi 0x1ffdf000 GLPCI R2: system msr.lo 0x40400120 msr.hi 0x4041f000 Exit northbridge_init_early Doing cpubug fixes for rev 0x21 CPU_BUG:eng2900 Done cpubug fixes Not Doing ChipsetFlashSetup() ---------- CPU ------------ MSR 0x00001700 is now 0x00000000:0x00100000 MSR 0x00001800 is now 0x00002000:0x00000022 MSR 0x00001808 is now 0x25FFFC02:0x11FFDF00 MSR 0x0000180A is now 0x00000000:0x00000000 MSR 0x0000180B is now 0x21212121:0x21212121 MSR 0x0000180C is now 0x21212121:0x21212121 MSR 0x0000180D is now 0x21212121:0x21212121 MSR 0x0000180E is now 0x00000001:0x00000001 MSR 0x0000180F is now 0x00000001:0x00000001 MSR 0x4C00000F is now 0x830D415A:0x8EA0AD6A ---------- GLIU 0 ------------ MSR 0x10000020 is now 0x20000000:0x000FFF80 MSR 0x10000021 is now 0x20000000:0x080FFFE0 MSR 0x10000022 is now 0x000000FF:0xFFF00000 MSR 0x10000023 is now 0x000000FF:0xFFF00000 MSR 0x10000024 is now 0x000000FF:0xFFF00000 MSR 0x10000025 is now 0x000000FF:0xFFF00000 MSR 0x10000026 is now 0x2DFBE040:0x400FFFE0 MSR 0x10000027 is now 0x000000FF:0xFFF00000 MSR 0x10000028 is now 0x2000001F:0xFDF00100 MSR 0x10000029 is now 0x00000000:0x000FFFFF MSR 0x1000002A is now 0x00000000:0x000FFFFF MSR 0x1000002B is now 0x00000000:0x000FFFFF MSR 0x1000002C is now 0x2000FFFF:0xFFFF0003 MSR 0x100000E0 is now 0x000000FF:0xFFF00000 MSR 0x100000E1 is now 0x000000FF:0xFFF00000 MSR 0x100000E2 is now 0x000000FF:0xFFF00000 MSR 0x100000E3 is now 0x00000000:0x00000000 MSR 0x100000E4 is now 0x00000000:0x00000000 MSR 0x100000E5 is now 0x00000000:0x00000000 MSR 0x100000E6 is now 0x00000000:0x00000000 MSR 0x100000E7 is now 0x00000000:0x00000000 MSR 0x100000E8 is now 0x00000000:0x00000000 MSR 0x10000080 is now 0x00000000:0x00000003 ---------- GLIU 1 ------------ MSR 0x40000020 is now 0x20000000:0x000FFF80 MSR 0x40000021 is now 0x20000000:0x080FFFE0 MSR 0x40000022 is now 0x000000FF:0xFFF00000 MSR 0x40000023 is now 0x20000040:0x400FFFE0 MSR 0x40000024 is now 0x000000FF:0xFFF00000 MSR 0x40000025 is now 0x000000FF:0xFFF00000 MSR 0x40000026 is now 0x000000FF:0xFFF00000 MSR 0x40000027 is now 0x000000FF:0xFFF00000 MSR 0x40000028 is now 0x000000FF:0xFFF00000 MSR 0x40000029 is now 0x2000001F:0xFDF00100 MSR 0x4000002A is now 0x00000000:0x000FFFFF MSR 0x4000002B is now 0x00000000:0x000FFFFF MSR 0x4000002C is now 0x00000000:0x000FFFFF MSR 0x4000002D is now 0x2000FFFF:0xFFFF0003 MSR 0x400000E0 is now 0x000000FF:0xFFF00000 MSR 0x400000E1 is now 0x000000FF:0xFFF00000 MSR 0x400000E2 is now 0x000000FF:0xFFF00000 MSR 0x400000E3 is now 0x60000000:0x033000F0 MSR 0x400000E4 is now 0x00000000:0x00000000 MSR 0x400000E5 is now 0x00000000:0x00000000 MSR 0x400000E6 is now 0x00000000:0x00000000 MSR 0x400000E7 is now 0x00000000:0x00000000 MSR 0x400000E8 is now 0x00000000:0x00000000 MSR 0x40000080 is now 0x00000000:0x00000001 ---------- RCONF ------------ MSR 0x00001810 is now 0x00000000:0x00000000 MSR 0x00001811 is now 0x00000000:0x00000000 MSR 0x00001812 is now 0x00000000:0x00000000 MSR 0x00001813 is now 0x00000000:0x00000000 MSR 0x00001814 is now 0x00000000:0x00000000 MSR 0x00001815 is now 0x00000000:0x00000000 MSR 0x00001816 is now 0x00000000:0x00000000 MSR 0x00001817 is now 0x00000000:0x00000000 ---------- VARIA ------------ MSR 0x51300010 is now 0x00000000:0x00000000 MSR 0x51400014 is now 0x00000000:0x04070003 MSR 0x51400015 is now 0x00000000:0x00000071 ---------- PCI ------------ MSR 0x50002010 is now 0xFFF030F8:0x001A0215 MSR 0x50002011 is now 0x00000300:0x00000100 MSR 0x50002014 is now 0x00000000:0x00FFFF00 MSR 0x50002015 is now 0x35353535:0x35353535 MSR 0x50002016 is now 0x35353535:0x35353535 MSR 0x50002017 is now 0x35353535:0x35353535 MSR 0x50002018 is now 0x0009F000:0x00000130 MSR 0x50002019 is now 0x1FFDF000:0x00100130 MSR 0x5000201A is now 0x4041F000:0x40400120 MSR 0x5000201B is now 0x00000000:0x00000000 MSR 0x5000201E is now 0x00000000:0x00000F00 MSR 0x5000201F is now 0x00000000:0x0000006B ---------- LPC/UART DMA ------------ MSR 0x51400040 is now 0x00000000:0x00000000 MSR 0x51400041 is now 0x00000000:0x000000DC MSR 0x51400042 is now 0x00000000:0x000000FD MSR 0x51400043 is now 0x00000000:0x000000FE MSR 0x51400044 is now 0x00000000:0x000000FF MSR 0x51400045 is now 0x00000000:0x000000C0 MSR 0x51400046 is now 0x00000000:0x000000F9 MSR 0x51400047 is now 0x00000000:0x000000DE MSR 0x51400048 is now 0x00000000:0x000000FF MSR 0x51400049 is now 0x00000000:0x000000FF ---------- DIVIL IRQ ------------ MSR 0x51400020 is now 0x00000000:0x00000000 MSR 0x51400021 is now 0x00000000:0x00000000 MSR 0x51400022 is now 0x00000000:0x00000000 MSR 0x51400023 is now 0x00000000:0x00000000 MSR 0x51400024 is now 0x00000000:0x0000FFFF ---------- DIVIL LBAR ----------- MSR 0x5140000C is now 0x0000F001:0x00006100 MSR 0x51400010 is now 0x00000000:0x00000000 MSR 0x51400011 is now 0x00000000:0x00000000 IOR 0x00006120 is now 0x3DFBC204 IOR 0x00006138 is now 0xFFFFFFFF IOR 0x00006124 is now 0xFFFFFFFF IOR 0x000061E0 is now 0xFFFFFFFF Preparing for VSA... Real mode stub @00000600: 867 bytes CBFS: loading stage vsa @ 0x60000 (57504 bytes), entry @ 0x60020 VSA: Buffer @00060000 *[0k]=ba VSA: Signature *[0x20-0x23] is b0:10:e6:80 Calling VSA module... ... VSA module returned. VSM: VSA2 VR signature verified. Graphics init... VRC_VG value: 0xffff DOMAIN: 0000 enabled >> Entering northbridge.c: enable_dev with path 7 CPU_CLUSTER: 0 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 >> Entering northbridge.c: enable_dev with path 2 PCI: 00:01.0 [1022/0028] enabled >> Entering northbridge.c: enable_dev with path 2 PCI: Static device PCI: 00:01.1 not found, disabling it. PCI: 00:01.2 [1022/2082] enabled cs5536: southbridge_enable: dev is 00116800 PCI: 00:0e.0 [10ec/8139] enabled cs5536: southbridge_enable: dev is 00116898 PCI: 00:0f.0 [1022/2090] bus ops PCI: 00:0f.0 [1022/2090] enabled cs5536: southbridge_enable: dev is 00116930 PCI: 00:0f.2 [1022/209a] ops PCI: 00:0f.2 [1022/209a] enabled cs5536: southbridge_enable: dev is 001169c8 PCI: 00:0f.3 [1022/2093] enabled cs5536: southbridge_enable: dev is 00116a60 PCI: 00:0f.4 [1022/2094] enabled cs5536: southbridge_enable: dev is 00116af8 PCI: 00:0f.5 [1022/2095] enabled PCI: 00:0f.6 [1022/2096] enabled PCI: 00:0f.7 [1022/2097] enabled scan_static_bus for PCI: 00:0f.0 scan_static_bus for PCI: 00:0f.0 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 DOMAIN: 0000 read_resources bus 0 link: 0 DOMAIN: 0000 read_resources bus 0 link: 0 done CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 DOMAIN: 0000 DOMAIN: 0000 child on link 0 PCI: 00:01.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10 PCI: 00:01.1 PCI: 00:01.2 PCI: 00:01.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:0e.0 PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.2 PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:0e.0 10 * [0x0 - 0xff] io PCI: 00:0f.0 14 * [0x400 - 0x4ff] io PCI: 00:0f.0 20 * [0x800 - 0x87f] io PCI: 00:0f.3 10 * [0x880 - 0x8ff] io PCI: 00:0f.0 18 * [0xc00 - 0xc3f] io PCI: 00:0f.0 24 * [0xc40 - 0xc7f] io PCI: 00:0f.0 1c * [0xc80 - 0xc9f] io PCI: 00:0f.2 20 * [0xca0 - 0xcaf] io PCI: 00:0f.0 10 * [0xcb0 - 0xcb7] io PCI: 00:01.0 10 * [0xcb8 - 0xcbb] io DOMAIN: 0000 compute_resources_io: base: cbc size: cbc align: 8 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.2 10 * [0x0 - 0x3fff] mem PCI: 00:0f.6 10 * [0x4000 - 0x5fff] mem PCI: 00:0f.4 10 * [0x6000 - 0x6fff] mem PCI: 00:0f.5 10 * [0x7000 - 0x7fff] mem PCI: 00:0f.7 10 * [0x8000 - 0x8fff] mem PCI: 00:0e.0 14 * [0x9000 - 0x90ff] mem DOMAIN: 0000 compute_resources_mem: base: 9100 size: 9100 align: 14 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.2 constrain_resources: PCI: 00:0e.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.2 constrain_resources: PCI: 00:0f.3 constrain_resources: PCI: 00:0f.4 constrain_resources: PCI: 00:0f.5 constrain_resources: PCI: 00:0f.6 constrain_resources: PCI: 00:0f.7 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:1000 size:cbc align:8 gran:0 limit:ffff Assigned: PCI: 00:0e.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0f.0 14 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 20 * [0x1800 - 0x187f] io Assigned: PCI: 00:0f.3 10 * [0x1880 - 0x18ff] io Assigned: PCI: 00:0f.0 18 * [0x1c00 - 0x1c3f] io Assigned: PCI: 00:0f.0 24 * [0x1c40 - 0x1c7f] io Assigned: PCI: 00:0f.0 1c * [0x1c80 - 0x1c9f] io Assigned: PCI: 00:0f.2 20 * [0x1ca0 - 0x1caf] io Assigned: PCI: 00:0f.0 10 * [0x1cb0 - 0x1cb7] io Assigned: PCI: 00:01.0 10 * [0x1cb8 - 0x1cbb] io DOMAIN: 0000 allocate_resources_io: next_base: 1cbc size: cbc align: 8 gran: 0 done DOMAIN: 0000 allocate_resources_mem: base:febf4000 size:9100 align:14 gran:0 limit:febfffff Assigned: PCI: 00:01.2 10 * [0xfebf4000 - 0xfebf7fff] mem Assigned: PCI: 00:0f.6 10 * [0xfebf8000 - 0xfebf9fff] mem Assigned: PCI: 00:0f.4 10 * [0xfebfa000 - 0xfebfafff] mem Assigned: PCI: 00:0f.5 10 * [0xfebfb000 - 0xfebfbfff] mem Assigned: PCI: 00:0f.7 10 * [0xfebfc000 - 0xfebfcfff] mem Assigned: PCI: 00:0e.0 14 * [0xfebfd000 - 0xfebfd0ff] mem DOMAIN: 0000 allocate_resources_mem: next_base: febfd100 size: 9100 align: 14 gran: 0 done Root Device assign_resources, bus 0 link: 0 >> Entering northbridge.c: pci_domain_set_resources CBMEM region 1ffc0000-1ffdffff (cbmem_late_set_table) DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x0000001cb8 - 0x0000001cbb] size 0x00000004 gran 0x02 io PCI: 00:01.2 10 <- [0x00febf4000 - 0x00febf7fff] size 0x00004000 gran 0x0e mem PCI: 00:0e.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:0e.0 14 <- [0x00febfd000 - 0x00febfd0ff] size 0x00000100 gran 0x08 mem PCI: 00:0f.0 10 <- [0x0000001cb0 - 0x0000001cb7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0f.0 18 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io PCI: 00:0f.0 1c <- [0x0000001c80 - 0x0000001c9f] size 0x00000020 gran 0x05 io PCI: 00:0f.0 20 <- [0x0000001800 - 0x000000187f] size 0x00000080 gran 0x07 io PCI: 00:0f.0 24 <- [0x0000001c40 - 0x0000001c7f] size 0x00000040 gran 0x06 io PCI: 00:0f.2 20 <- [0x0000001ca0 - 0x0000001caf] size 0x00000010 gran 0x04 io PCI: 00:0f.3 10 <- [0x0000001880 - 0x00000018ff] size 0x00000080 gran 0x07 io PCI: 00:0f.4 10 <- [0x00febfa000 - 0x00febfafff] size 0x00001000 gran 0x0c mem PCI: 00:0f.5 10 <- [0x00febfb000 - 0x00febfbfff] size 0x00001000 gran 0x0c mem PCI: 00:0f.6 10 <- [0x00febf8000 - 0x00febf9fff] size 0x00002000 gran 0x0d mem PCI: 00:0f.7 10 <- [0x00febfc000 - 0x00febfcfff] size 0x00001000 gran 0x0c mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 DOMAIN: 0000 DOMAIN: 0000 child on link 0 PCI: 00:01.0 DOMAIN: 0000 resource base 1000 size cbc align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base febf4000 size 9100 align 14 gran 0 limit febfffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 1ff20000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:01.0 PCI: 00:01.0 resource base 1cb8 size 4 align 2 gran 2 limit ffff flags 60000100 index 10 PCI: 00:01.1 PCI: 00:01.2 PCI: 00:01.2 resource base febf4000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10 PCI: 00:0e.0 PCI: 00:0e.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:0e.0 resource base febfd000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 PCI: 00:0f.0 PCI: 00:0f.0 resource base 1cb0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 1c00 size 40 align 6 gran 6 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 1c80 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 1800 size 80 align 7 gran 7 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 1c40 size 40 align 6 gran 6 limit ffff flags 60000100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.2 PCI: 00:0f.2 resource base 1ca0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 1880 size 80 align 7 gran 7 limit ffff flags 60000100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base febfa000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base febfb000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base febf8000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base febfc000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. Enabling resources... PCI: 00:01.0 subsystem <- 0000/0000 PCI: 00:01.0 cmd <- 05 PCI: 00:01.2 cmd <- 02 PCI: 00:0e.0 subsystem <- 0000/0000 PCI: 00:0e.0 cmd <- 03 PCI: 00:0f.0 cmd <- 09 PCI: 00:0f.2 cmd <- 01 PCI: 00:0f.3 subsystem <- 0000/0000 PCI: 00:0f.3 cmd <- 01 PCI: 00:0f.4 subsystem <- 0000/0000 PCI: 00:0f.4 cmd <- 02 PCI: 00:0f.5 subsystem <- 0000/0000 PCI: 00:0f.5 cmd <- 02 PCI: 00:0f.6 cmd <- 02 PCI: 00:0f.7 cmd <- 02 done. Initializing devices... Root Device init S50 ENTER init S50 EXIT init CPU_CLUSTER: 0 init >> Entering northbridge.c: cpu_bus_init Initializing CPU #0 CPU: vendor NSC device 552 CPU: family 05, model 05, stepping 02 geode_gx2_init Enabling cache geode_gx2_init DONE CPU #0 initialized PCI: 00:01.0 init PCI: 00:01.2 init PCI: 00:0e.0 init PCI: 00:0f.0 init cs5536: southbridge_init RTC Init GPIO_ADDR: 00001400 uarts_init: enable COM1 uarts_init: disable COM2 cs5536: southbridge_init: enable_ide_nand_flash is 0 PCI: 00:0f.2 init cs5536_ide: ide_init PCI: 00:0f.3 init PCI: 00:0f.4 init PCI: 00:0f.5 init PCI: 00:0f.6 init PCI: 00:0f.7 init Devices initialized Show all devs...After init. Root Device: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 0 PCI: 00:0e.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.3: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI: 00:01.2: enabled 1 PCI: 00:0f.6: enabled 1 PCI: 00:0f.7: enabled 1 CPU: 00: enabled 1 CBMEM region 1ffc0000-1ffdffff (cbmem_check_toc) CBMEM region 1ffc0000-1ffdffff (cbmem_initialize_empty) Adding CBMEM entry as no. 1 Moving GDT to 1ffc0200...ok Finalize devices... Devices finalized Copying Interrupt Routing Table to 0x000f0000... done. PIRQ Entry 0 Dev/Fn: F Slot: 5 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 20 IRQ: 5 INT: C link: 3 bitmap: 400 IRQ: 10 INT: D link: 4 bitmap: 400 IRQ: 10 Assigning IRQ 5 to 0:f.3 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x20 Assigning IRQ 10 to 0:f.4 i8259_configure_irq_trigger: current interrupts are 0x20 i8259_configure_irq_trigger: try to set interrupts 0x420 Assigning IRQ 10 to 0:f.5 i8259_configure_irq_trigger: current interrupts are 0x420 i8259_configure_irq_trigger: try to set interrupts 0x420 PIRQ Entry 1 Dev/Fn: D Slot: 1 INT: A link: 4 bitmap: 400 IRQ: 10 INT: B link: 3 bitmap: 400 IRQ: 10 INT: C link: 2 bitmap: 20 IRQ: 5 INT: D link: 1 bitmap: 800 IRQ: 11 PIRQ Entry 2 Dev/Fn: E Slot: 2 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 20 IRQ: 5 INT: C link: 3 bitmap: 400 IRQ: 10 INT: D link: 4 bitmap: 400 IRQ: 10 Assigning IRQ 11 to 0:e.0 i8259_configure_irq_trigger: current interrupts are 0x420 i8259_configure_irq_trigger: try to set interrupts 0xc20 PIRQA: 11 PIRQB: 5 PIRQC: 10 PIRQD: 10 Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x1ffc0400... done. PIRQ Entry 0 Dev/Fn: F Slot: 5 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 20 IRQ: 5 INT: C link: 3 bitmap: 400 IRQ: 10 INT: D link: 4 bitmap: 400 IRQ: 10 Assigning IRQ 5 to 0:f.3 i8259_configure_irq_trigger: current interrupts are 0xc20 i8259_configure_irq_trigger: try to set interrupts 0xc20 Assigning IRQ 10 to 0:f.4 i8259_configure_irq_trigger: current interrupts are 0xc20 i8259_configure_irq_trigger: try to set interrupts 0xc20 Assigning IRQ 10 to 0:f.5 i8259_configure_irq_trigger: current interrupts are 0xc20 i8259_configure_irq_trigger: try to set interrupts 0xc20 PIRQ Entry 1 Dev/Fn: D Slot: 1 INT: A link: 4 bitmap: 400 IRQ: 10 INT: B link: 3 bitmap: 400 IRQ: 10 INT: C link: 2 bitmap: 20 IRQ: 5 INT: D link: 1 bitmap: 800 IRQ: 11 PIRQ Entry 2 Dev/Fn: E Slot: 2 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 20 IRQ: 5 INT: C link: 3 bitmap: 400 IRQ: 10 INT: D link: 4 bitmap: 400 IRQ: 10 Assigning IRQ 11 to 0:e.0 i8259_configure_irq_trigger: current interrupts are 0xc20 i8259_configure_irq_trigger: try to set interrupts 0xc20 PIRQA: 11 PIRQB: 5 PIRQC: 10 PIRQD: 10 PIRQ table: 80 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 1ffc1400 Root Device (Wyse s50) DOMAIN: 0000 (AMD GX (previously GX2) Northbridge) PCI: 00:01.0 (AMD GX (previously GX2) Northbridge) PCI: 00:01.1 (AMD GX (previously GX2) Northbridge) PCI: 00:0e.0 (AMD Geode CS5536 Southbridge) PCI: 00:0f.0 (AMD Geode CS5536 Southbridge) PCI: 00:0f.2 (AMD Geode CS5536 Southbridge) PCI: 00:0f.3 (AMD Geode CS5536 Southbridge) PCI: 00:0f.4 (AMD Geode CS5536 Southbridge) PCI: 00:0f.5 (AMD Geode CS5536 Southbridge) CPU_CLUSTER: 0 (AMD GX (previously GX2) Northbridge) APIC: 00 (unknown) PCI: 00:01.2 (unknown) PCI: 00:0f.6 (unknown) PCI: 00:0f.7 (unknown) CPU: 00 (unknown) SMBIOS tables: 296 bytes. Adding CBMEM entry as no. 4 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum c3e2 Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0x1ffc1c00 rom_table_end = 0x1ffc1c00 ... aligned to 0x1ffd0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001ffbffff: RAM 3. 000000001ffc0000-000000001ffdffff: CONFIGURATION TABLES Wrote coreboot table at: 1ffc1c00, 0x1c4 bytes, checksum 4658 coreboot table: 476 bytes. FREE SPACE 0. 1ffc9c00 00016400 GDT 1. 1ffc0200 00000200 IRQ TABLE 2. 1ffc0400 00001000 SMBIOS 3. 1ffc1400 00000800 COREBOOT 4. 1ffc1c00 00008000 Loading segment from rom address 0xfff1e9f8 code (compression=0) New segment dstaddr 0xe6b50 memsize 0x194b0 srcaddr 0xfff1ea30 filesize 0x194b0 (cleaned up) New segment addr 0xe6b50 size 0x194b0 offset 0xfff1ea30 filesize 0x194b0 Loading segment from rom address 0xfff1ea14 Entry Point 0x000fc7a8 Loading Segment: addr: 0x00000000000e6b50 memsz: 0x00000000000194b0 filesz: 0x00000000000194b0 lb: [0x0000000000100000, 0x0000000000122000) Post relocation: addr: 0x00000000000e6b50 memsz: 0x00000000000194b0 filesz: 0x00000000000194b0 it's not compressed! [ 0x000e6b50, 00100000, 0x00100000) <- fff1ea30 dest 000e6b50, end 00100000, bouncebuffer 1ff7c000 Loaded segments Jumping to boot code at 000fc7a8 CPU0: stack: 0011d000 - 0011e000, lowest used address 0011db34, stack used: 1228 bytes entry = 0x000fc7a8 lb_start = 0x00100000 lb_size = 0x00022000 buffer = 0x1ff7c000 Start bios (version -20140217_190357-hroogar) Found mainboard Wyse s50 Ram Size=0x1ffc0000 (0x0000000000000000 high) Relocating low data from 0x000e7400 to 0x000ef790 (size 2153) Relocating init from 0x000e7c69 to 0x1ffa6070 (size 40555) Found CBFS header at 0xfffffcd0 CPU Mhz=365 Found 8 PCI devices (max PCI bus is 00) No apic - only the main cpu is present. Copying PIR from 0x1ffc0400 to 0x000fdba0 Copying SMBIOS entry point from 0x1ffc1400 to 0x000fdb80 Scan for VGA option rom EHCI init on dev 00:0f.5 (regs=0xfebfb010) WARNING - Timeout at i8042_flush:68! Found 0 lpt ports Found 1 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 7a) ATA controller 2 at 170/374/0 (irq 15 dev 7a) ata0-0: CF 8GB ATA-4 Hard-Disk (7647 MiBytes) Searching bootorder for: /pci@i0cf8/*@f,2/drive@0/disk@0 OHCI init on dev 00:0f.4 (regs=0xfebfa000) All threads complete. Scan for option roms Press F12 for boot menu. Searching bootorder for: HALT drive 0x000fdb30: PCHS=15538/16/63 translation=lba LCHS=974/255/63 s=15662304 Space available for UMB: 000c0000-000ef000 Returned 65536 bytes of ZoneHigh e820 map has 5 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000001ffc0000 = 1 RAM 4: 000000001ffc0000 - 000000001ffe0000 = 2 RESERVED enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00 LILO 22.8 Loading Linux........................................................................................................ BIOS data check successful Linux version 2.6.33.4-smp (root@midas) (gcc version 4.4.4 (GCC) ) #2 SMP Wed May 12 22:47:36 CDT 2010 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 000000000009fc00 (usable) BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved) BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) BIOS-e820: 0000000000100000 - 000000001ffc0000 (usable) BIOS-e820: 000000001ffc0000 - 000000001ffe0000 (reserved) Notice: NX (Execute Disable) protection missing in CPU or disabled in BIOS! DMI present. last_pfn = 0x1ffc0 max_arch_pfn = 0x100000 init_memory_mapping: 0000000000000000-000000001ffc0000 ACPI Error: A valid RSDP was not found (20091214/tbxfroot-219) 0MB HIGHMEM available. 511MB LOWMEM available. mapped low ram: 0 - 1ffc0000 low ram: 0 - 1ffc0000 node 0 low ram: 00000000 - 1ffc0000 node 0 bootmap 00009000 - 0000cff8 (9 early reservations) ==> bootmem [0000000000 - 001ffc0000] #0 [0000000000 - 0000001000] BIOS data page ==> [0000000000 - 0000001000] #1 [0000001000 - 0000002000] EX TRAMPOLINE ==> [0000001000 - 0000002000] #2 [0001000000 - 0001df1f64] TEXT DATA BSS ==> [0001000000 - 0001df1f64] #3 [000009fc00 - 0000100000] BIOS reserved ==> [000009fc00 - 0000100000] #4 [0001df2000 - 0001dfa05d] BRK ==> [0001df2000 - 0001dfa05d] #5 [0000002000 - 0000003000] TRAMPOLINE ==> [0000002000 - 0000003000] #6 [0000003000 - 0000007000] ACPI WAKEUP ==> [0000003000 - 0000007000] #7 [0000007000 - 0000009000] PGTABLE ==> [0000007000 - 0000009000] #8 [0000009000 - 000000d000] BOOTMAP ==> [0000009000 - 000000d000] Zone PFN ranges: DMA 0x00000000 -> 0x00001000 Normal 0x00001000 -> 0x0001ffc0 HighMem 0x0001ffc0 -> 0x0001ffc0 Movable zone start PFN for each node early_node_map[2] active PFN ranges 0: 0x00000000 -> 0x0000009f 0: 0x00000100 -> 0x0001ffc0 Using APIC driver default SFI: Simple Firmware Interface v0.7 http://simplefirmware.org SMP: Allowing 1 CPUs, 0 hotplug CPUs No local APIC present or hardware disabled APIC: disable apic facility APIC: switched to apic NOOP PM: Registered nosave memory: 000000000009f000 - 00000000000a0000 PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000 PM: Registered nosave memory: 00000000000f0000 - 0000000000100000 Allocating PCI resources starting at 1ffe0000 (gap: 1ffe0000:e0020000) setup_percpu: NR_CPUS:32 nr_cpumask_bits:32 nr_cpu_ids:1 nr_node_ids:1 PERCPU: Embedded 14 pages/cpu @c2400000 s34648 r0 d22696 u4194304 pcpu-alloc: s34648 r0 d22696 u4194304 alloc=1*4194304 pcpu-alloc: [0] 0 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 129887 Kernel command line: auto BOOT_IMAGE=Linux ro root=801 console=tty0 console=ttyS0,115200 PID hash table entries: 2048 (order: 1, 8192 bytes) Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) Initializing CPU#0 Initializing HighMem for node 0 (00000000:00000000) Memory: 504408k/524032k available (9560k kernel code, 18916k reserved, 3111k data, 636k init, 0k highmem) virtual kernel memory layout: fixmap : 0xffd57000 - 0xfffff000 (2720 kB) pkmap : 0xff400000 - 0xff800000 (4096 kB) vmalloc : 0xe07c0000 - 0xff3fe000 ( 492 MB) lowmem : 0xc0000000 - 0xdffc0000 ( 511 MB) .init : 0xc1c61000 - 0xc1d00000 ( 636 kB) .data : 0xc19561c0 - 0xc1c60004 (3111 kB) .text : 0xc1000000 - 0xc19561c0 (9560 kB) Checking if this processor honours the WP bit even in supervisor mode...Ok. SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 Hierarchical RCU implementation. NR_IRQS:1280 Console: colour dummy device 80x25 console [tty0] enabled console [ttyS0] enabled Fast TSC calibration using PIT Detected 365.208 MHz processor. Calibrating delay loop (skipped), value calculated using timer frequency.. 730.41 BogoMIPS (lpj=365208) Security Framework initialized Mount-cache hash table entries: 512 Performance Events: Checking 'hlt' instruction... OK. SMP alternatives: switching to UP code Freeing SMP alternatives: 29k freed ftrace: converting mcount calls to 66 66 66 66 90 ftrace: allocating 33446 entries in 66 pages weird, boot CPU (#0) not listed by the BIOS. SMP motherboard not detected. Local APIC not detected. Using dummy APIC emulation. SMP disabled Brought up 1 CPUs Total of 1 processors activated (730.41 BogoMIPS). devtmpfs: initialized xor: measuring software checksum speed 8regs : 280.000 MB/sec 8regs_prefetch: 236.000 MB/sec 32regs : 160.000 MB/sec 32regs_prefetch: 140.000 MB/sec pII_mmx : 460.000 MB/sec p5_mmx : 480.000 MB/sec xor: using function: p5_mmx (480.000 MB/sec) NET: Registered protocol family 16 PCI: PCI BIOS revision 2.10 entry at 0xfc75b, last bus=0 PCI: Using configuration type 1 for base access bio: create slab <bio-0> at 0 ACPI: Interpreter disabled. vgaarb: loaded SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb raid6: int32x1 19 MB/s raid6: int32x2 31 MB/s raid6: int32x4 35 MB/s raid6: int32x8 39 MB/s raid6: mmxx1 42 MB/s raid6: mmxx2 70 MB/s raid6: sse1x1 46 MB/s raid6: sse1x2 74 MB/s raid6: using algorithm sse1x2 (74 MB/s) PCI: Probing PCI hardware pci 0000:00:0f.0: default IRQ router [1022:2090] Switching to clocksource tsc pnp: PnP ACPI: disabled NET: Registered protocol family 2 IP route cache hash table entries: 4096 (order: 2, 16384 bytes) TCP established hash table entries: 16384 (order: 5, 131072 bytes) TCP bind hash table entries: 16384 (order: 5, 131072 bytes) TCP: Hash tables configured (established 16384 bind 16384) TCP reno registered UDP hash table entries: 256 (order: 1, 8192 bytes) UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) NET: Registered protocol family 1 RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. platform rtc_cmos: registered platform RTC device (no PNP device found) audit: initializing netlink socket (disabled) type=2000 audit(1392680058.624:1): initialized VFS: Disk quotas dquot_6.5.2 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) DLM (built May 12 2010 22:42:00) installed Installing knfsd (copyright (C) 1996 okir(a)monad.swb.de). NTFS driver 2.1.29 [Flags: R/W]. ROMFS MTD (C) 2007 Red Hat, Inc. JFS: nTxBlock = 3943, nTxLock = 31547 SGI XFS with ACLs, security attributes, large block/inode numbers, no debug enabled SGI XFS Quota Management subsystem OCFS2 1.5.0 ocfs2: Registered cluster interface o2cb ocfs2: Registered cluster interface user OCFS2 Node Manager 1.5.0 OCFS2 DLM 1.5.0 OCFS2 DLMFS 1.5.0 OCFS2 User DLM kernel interface loaded Btrfs loaded Slow work thread pool: Starting up Slow work thread pool: Ready GFS2 (built May 12 2010 22:42:42) installed msgmni has been set to 985 alg: No test for cipher_null (cipher_null-generic) alg: No test for ecb(cipher_null) (ecb-cipher_null) alg: No test for digest_null (digest_null-generic) alg: No test for compress_null (compress_null-generic) alg: No test for fcrypt (fcrypt-generic) alg: No test for stdrng (krng) async_tx: api initialized (async) Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) pci_hotplug: PCI Hot Plug PCI Core version: 0.5 isapnp: Scanning for PnP cards... Clocksource tsc unstable (delta = 96032313 ns) Switching to clocksource pit isapnp: No Plug & Play device found Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled ÿserial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a NS16550A floppy0: no floppy controllers found brd: module loaded loop: module loaded Compaq SMART2 Driver (v 2.6.0) HP CISS Driver (v 3.6.20) input: Macintosh mouse button emulation as /devices/virtual/input/input0 Loading iSCSI transport class v2.0-870. fnic: Cisco FCoE HBA Driver, ver 1.0.0.1121 Adaptec aacraid driver 1.1-5[24702]-ms aic94xx: Adaptec aic94xx SAS/SATA driver version 1.0.3 loaded scsi: <fdomain> Detection failed (no card) sym53c416.c: Version 1.0.0-ac qlogicfas: no cards were found, please specify I/O address and IRQ using iobase= and irq= options QLogic Fibre Channel HBA Driver: 8.03.01-k10 iscsi: registered transport (qla4xxx) QLogic iSCSI HBA Driver Emulex LightPulse Fibre Channel SCSI driver 8.3.7 Copyright(c) 2004-2009 Emulex. All rights reserved. Brocade BFA FC/FCOE SCSI driver - version: 2.0.0.0 Failed initialization of WD-7000 SCSI card! DC390: clustering now enabled by default. If you get problems load with "disable_clustering=1" and report to maintainers megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006) megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006) megasas: 00.00.04.12-rc1 Thu Sep. 17 11:41:51 PST 2009 mpt2sas version 03.100.03.00 loaded GDT-HA: Storage RAID Controller Driver. Version: 3.05 3ware Storage Controller device driver for Linux v1.26.02.002. 3ware 9000 Storage Controller device driver for Linux v2.26.02.013. LSI 3ware SAS/SATA-RAID Controller device driver for Linux v3.26.02.000. ipr: IBM Power RAID SCSI Device Driver version: 2.4.3 (June 10, 2009) RocketRAID 3xxx/4xxx Controller driver v1.6 (090910) stex: Promise SuperTrak EX Driver version: 4.6.0000.4 st: Version 20081215, fixed bufsize 32768, s/g segs 256 scsi2 : pata_amd scsi3 : pata_amd ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x1ca0 irq 14 ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x1ca8 irq 15 I2O subsystem v1.325 i2o: max drivers = 8 I2O Configuration OSM v1.323 I2O Bus Adapter OSM v1.317 I2O Block Device OSM v1.325 I2O SCSI Peripheral OSM v1.316 I2O ProcFS OSM v1.316 Fusion MPT base driver 3.04.13 Copyright (c) 1999-2008 LSI Corporation Fusion MPT SPI Host driver 3.04.13 Fusion MPT FC Host driver 3.04.13 Fusion MPT SAS Host driver 3.04.13 Fusion MPT misc device (ioctl) driver 3.04.13 mptctl: Registered with Fusion MPT base driver mptctl: /dev/mptctl @ (major,minor=10,220) Fusion MPT LAN driver 3.04.13 ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci_hcd 0000:00:0f.5: guessed PCI INT D -> IRQ 10 ehci_hcd 0000:00:0f.5: sharing IRQ 10 with 0000:00:0f.4 ehci_hcd 0000:00:0f.5: EHCI Host Controller ehci_hcd 0000:00:0f.5: new USB bus registered, assigned bus number 1 ehci_hcd 0000:00:0f.5: irq 10, io mem 0xfebfb000 ehci_hcd 0000:00:0f.5: USB 2.0 started, EHCI 1.00 usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb1: Product: EHCI Host Controller usb usb1: Manufacturer: Linux 2.6.33.4-smp ehci_hcd usb usb1: SerialNumber: 0000:00:0f.5 hub 1-0:1.0: USB hub found hub 1-0:1.0: 4 ports detected 116x: driver isp116x-hcd, 03 Nov 2005 driver isp1362-hcd, 2005-04-04 ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver ohci_hcd 0000:00:0f.4: guessed PCI INT D -> IRQ 10 ohci_hcd 0000:00:0f.4: sharing IRQ 10 with 0000:00:0f.5 ohci_hcd 0000:00:0f.4: OHCI Host Controller ohci_hcd 0000:00:0f.4: new USB bus registered, assigned bus number 2 ohci_hcd 0000:00:0f.4: irq 10, io mem 0xfebfa000 ata1.00: CFA: CF 8GB, 20080820, max UDMA/66 ata1.00: 15662304 sectors, multi 0: LBA ata1.00: configured for UDMA/66 scsi 2:0:0:0: Direct-Access ATA CF 8GB 2008 PQ: 0 ANSI: 5 sd 2:0:0:0: [sda] 15662304 512-byte logical blocks: (8.01 GB/7.46 GiB) sd 2:0:0:0: [sda] Write Protect is off sd 2:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA sda: sda1 sda2 usb usb2: New USB device found, idVendor=1d6b, idProduct=0001 usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb2: Product: OHCI Host Controller usb usb2: Manufacturer: Linux 2.6.33.4-smp ohci_hcd usb usb2: SerialNumber: 0000:00:0f.4 sd 2:0:0:0: [sda] Attached SCSI disk hub 2-0:1.0: USB hub found hub 2-0:1.0: 4 ports detected uhci_hcd: USB Universal Host Controller Interface driver sl811: driver sl811-hcd, 19 May 2005 r8a66597_hcd: driver r8a66597_hcd, 2009-05-26 Initializing USB Mass Storage driver... usbcore: registered new interface driver usb-storage USB Mass Storage support registered. usbcore: registered new interface driver ums-alauda usbcore: registered new interface driver ums-cypress usbcore: registered new interface driver ums-datafab usbcore: registered new interface driver ums-freecom usbcore: registered new interface driver ums-isd200 usbcore: registered new interface driver ums-jumpshot usbcore: registered new interface driver ums-karma usbcore: registered new interface driver ums-onetouch usbcore: registered new interface driver ums-sddr09 usbcore: registered new interface driver ums-sddr55 usbcore: registered new interface driver ums-usbat PNP: No PS/2 controller found. Probing ports directly. i8042.c: No controller found. mice: PS/2 mouse device common for all mice md: linear personality registered for level -1 md: raid0 personality registered for level 0 md: raid1 personality registered for level 1 md: raid10 personality registered for level 10 md: raid6 personality registered for level 6 md: raid5 personality registered for level 5 md: raid4 personality registered for level 4 md: multipath personality registered for level -4 device-mapper: uevent: version 1.0.3 device-mapper: ioctl: 4.17.0-ioctl (2010-03-05) initialised: dm-devel(a)redhat.com cpuidle: using governor ladder cpuidle: using governor menu TCP cubic registered Initializing XFRM netlink socket NET: Registered protocol family 17 Using IPI No-Shortcut mode registered taskstats version 1 md: Waiting for all devices to be available before autodetect md: If you don't use raid, use raid=noautodetect md: Autodetecting RAID arrays. md: Scanned 0 and added 0 devices. md: autorun ... md: ... autorun DONE. kjournald starting. Commit interval 5 seconds EXT3-fs (sda1): mounted filesystem with ordered data mode VFS: Mounted root (ext3 filesystem) readonly on device 8:1. devtmpfs: mounted Freeing unused kernel memory: 636k freed Write protecting the kernel text: 9564k Write protecting the kernel read-only data: 2448k INIT: version 2.86 booting proc on /proc type proc (rw) sysfs on /sys type sysfs (rw) usb 2-4: new low speed USB device using ohci_hcd and address 2 usb 2-4: New USB device found, idVendor=1c4f, idProduct=0002 usb 2-4: New USB device strings: Mfr=1, Product=2, SerialNumber=0 usb 2-4: Product: USB Keykoard usb 2-4: Manufacturer: USB udev: starting version 153 Triggering udev events: /sbin/udevadm trigger --action=add pci 0000:00:0f.0: allocated PCI BAR #1: base 0x1400 pci 0000:00:0f.0: cs5535-gpio: GPIO support successfully loaded. sd 2:0:0:0: Attached scsi generic sg0 type 0 AMD Geode RNG detected 8139too Fast Ethernet driver 0.9.28 8139too 0000:00:0e.0: guessed PCI INT A -> IRQ 11 eth0: RealTek RTL8139 at 0x1000, 00:80:64:90:3b:31, IRQ 11 pci 0000:00:0f.0: allocated PCI BAR #2: base 0x1c00 pci 0000:00:0f.0: cs5535-mfgpt: 2 MFGPT timers available usbcore: registered new interface driver hiddev input: USB USB Keykoard as /devices/pci0000:00/0000:00:0f.4/usb2/2-4/2-4:1.0/input/input1 generic-usb 0003:1C4F:0002.0001: input,hidraw0: USB HID v1.10 Keyboard [USB USB Keykoard] on usb-0000:00:0f.4-4/input0 Geode LX AES 0000:00:01.2: enabling device (0000 -> 0002) Geode LX AES 0000:00:01.2: can't find IRQ for PCI INT A; please try using pci=biosirq alg: cipher: Test 1 failed on encryption for geode-aes 00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff alg: skcipher: Test 1 failed on encryption for ecb-aes-geode 00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff geode-aes: GEODE AES engine enabled. udev: renamed network interface eth0 to eth1 rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0 rtc0: alarms up to one day, 114 bytes nvram cs5535audio 0000:00:0f.3: guessed PCI INT B -> IRQ 5 drivers/hid/usbhid/hid-core.c: usb_submit_urb(ctrl) failed generic-usb 0003:1C4F:0002.0002: timeout initializing reports input: USB USB Keykoard as /devices/pci0000:00/0000:00:0f.4/usb2/2-4/2-4:1.1/input/input2 generic-usb 0003:1C4F:0002.0002: input,hidraw1: USB HID v1.10 Device [USB USB Keykoard] on usb-0000:00:0f.4-4/input1 usbcore: registered new interface driver usbhid usbhid: USB HID core driver Adding 479800k swap on /dev/sda2. Priority:-1 extents:1 across:479800k Setting system time from the hardware clock (localtime). Testing root filesystem status: read-only filesystem Checking root filesystem: fsck from util-linux-ng 2.17.2 Remounting root device with read-write enabled. EXT3-fs (sda1): using internal journal /dev/sda1 on / type ext3 (rw) Running /etc/rc.d/rc.modules-2.6.33.4-smp: Module dependencies up to date (no new kernel modules found). ppdev: user-space parallel port driver lp: driver loaded but no devices found Linux agpgart interface v0.103 Checking non-root filesystems: fsck from util-linux-ng 2.17.2 usbfs on /proc/bus/usb type usbfs (rw) Mounting non-root local filesystems: tmpfs on /dev/shm type tmpfs (rw) Using /etc/random-seed to initialize /dev/urandom. INIT: Entering runlevel: 3 Going multiuser... Updating shared library links: /sbin/ldconfig & cannot (un)set powersave mode Starting sysklogd daemons: /usr/sbin/syslogd /usr/sbin/klogd -c 3 -x Triggering udev events: /sbin/udevadm trigger --type=failed Starting Internet super-server daemon: /usr/sbin/inetd Starting OpenSSH SSH daemon: /usr/sbin/sshd Starting system message bus: /usr/bin/dbus-uuidgen --ensure ; /usr/bin/dbus-daemon --system Loading /usr/share/kbd/keymaps/i386/qwerty/uk.map.gz Welcome to Linux 2.6.33.4-smp (ttyS0) raedwald login: > Hi Andrew, > > busy day, but I have now finally found some time to send you the VSA file > that I compiled on my Win2000 machine! I have done nothing to the source > code, just compiled what I downloaded from the laptop.org site. > > I figure it is better to just mail this to you directly, as I'm not sure > binary attachments are working on the mailing list. > > I'll reply to your other comments back on the list when I get a chance, > probably tomorrow. > > -Jamie > > On Feb 17, 2014, at 14:27 , andrew(a)cogman.info wrote: >> >> Would you be willing to send me a copy of the VSA you compiled so I can >> see if that works? I think all the Sx0-02L versions are the same so >> hopefully it should work on any of them. > >

4 years, 7 months

8
17
0 / 0

Re: [coreboot] [RFC] board_status: Add serial log to `serial_console.txt`

by Vladimir 'φ-coder/phcoder' Serbinenko

On 10.02.2014 23:47, David Hendricks wrote: > On Sun, Feb 9, 2014 at 4:50 AM, Paul Menzel > <paulepanter(a)users.sourceforge.net > <mailto:paulepanter@users.sourceforge.net>> wrote: > > Dear coreboot folks, > > > currently no coreboot messages are stored for boards not supporting > CBMEM console (or where this option is disabled (currently by default)) > or no coreboot *romstage* messages are stored for boards, where the data > cannot be preserved (passed to ramstage). > > Using the serial (or USB) console all these messages can be captured > with no problem, so I propose to just add these captured messages into > the file `serial_console.txt`. Of course this file probably contains > also the payload and (Linux) kernel log, but I think that is fine. > > SeaBIOS’ `readserial.py` should be used for capturing the messages as it > adds time stamps. > > Scripting this is going to be hard, as the log is captured on a > different system. So for now I propose to add it manually. > > > I don't think the script itself should be responsible for collecting > serial output. Instead, how about adding an argument to override the > default behavior of running "cbmem -c" on the target so that the user > can pass in a filename? The user will simply capture the serial output > using whatever tool they like, dump the output to a text file, and run > the script with an argument to use the file instead of calling "cbmem > -c". Here is a proof-of-concept: http://review.coreboot.org/#/c/5191 . > This requires user to do right manipulations. While keyboard and chair are usually fine, the space between them exhibits strong bug-inducing properties. The idea of the script is to reduce a possibility of user error creating strange reports. In this case the common erro I expect is using a stale file fom some other version. It's a particularly nasty one as at first glance in may look fine but would be almost useless to track how details changed from one submit to the next. If we let user supply files at all, it should be added to report, not replace files, and it should have some prefix to clearly indicate that user was involved in creating them. E.g. user_serial_log.txt > But in general I think I agree with Vladimir. CBMEM console should be > supported and if not then that should be fixed. > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > >

4 years, 10 months

6
14
0 / 0

EHCI debug port finder

by Carl-Daniel Hailfinger

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

4 years, 12 months

5
13
0 / 0

#201: Error building coreboot for Samsung Exynos5 Google Snow

by coreboot

#201: Error building coreboot for Samsung Exynos5 Google Snow -------------------------------------------+------------------------------- Reporter: Pete <bluestore.logmein@…> | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patch Status: there is no | patch -------------------------------------------+------------------------------- Hi, I am trying to compile a coreboot rom for the Samsung chromebook Series 3 - Exynos5, i followed the instructions at http://www.coreboot.org/Exynos5 to compile the armv7a-eabi toolchain and evertyhing went ok. At the menuconfig i selected Google MainBoard, model Snow, exit and save. It starts to compile until it returns this error: GEN generated/romstage.ld LINK cbfs/fallback/romstage.debug build/ec/google/chromeec/ec.romstage.o: In function `google_chromeec_early_init': /home/suporte/coreboot/src/ec/google/chromeec/ec.c:117: undefined reference to `recovery_mode_enabled' collect2: error: ld returned 1 exit status make: *** [build/cbfs/fallback/romstage.debug] Error 1 Am i missing something? Also tried make clean and make crossgcc, and even the built went fine, when i run make always returns this error. Thank you, Pete -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/201> coreboot <http://www.coreboot.org/>

5 years

1
1
0 / 0

IMB-A180E H coreboot won't boot

by Mark C. Mason

I'm new to coreboot, and I'm working to use it with an ASROCK IMB-A180, the H version with the LVDS port. I've read previous posts regarding the "IMB-A180 won't boot" on this group, and tried the .config that was posted, but the result is the same. The debugging output shows things progressing until agesawwrapper_amdinitmid is called, then the boot restarts, then stops cold at the same point: PCI: 00:18.4 PCI: 00:18.5 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1095130 exit 0 POST: 0x74 Enabling resources... Fam16 - domain_enable_resources: AmdInitMid. agesawrapper_amdinitmid ^@^@^@^@§H¨Hh½É<95><89>½½Ñµ4.0-5169-g9d1d740 Tue Feb 4 16:46:38 PST 2014 starting... Any help with this would be greatly appreciated. Full serial debug output then .config are attached below. Best regards, Mark Mason Engineering Design Team

5 years

2
1
0 / 0

Re: [coreboot] [announce] coreboot for the 21st century

by Patrick Georgi

I took the discussion to IRC, to avoid endless back-and-forth by mail. In summary: The plan is to enable us to write romstage code with the expectation that at least some RAM (through CAR) is available. (while bootblock is expected to work without RAM of any kind, and ramstage has the full RAM available) If someone wants to use romcc for romstage, that means working without other object files (since romcc never emits a "call" instruction, except when hand-assembled). Thus reusing other .c files in romcc means "#include *.c" as it always did. Proposal: If someone goes that route, and things break due to the .c files of the coreboot core being too complex for romcc to handle, they get to keep the pieces - it's unsupported. I expect special cases like Vortex (or old chipsets like Via C3, if someone has the interest and time to do the port) to have a simple enough RAM initialization that they can be implemented as standalone C code. That's still _much_ more comfortable than writing assembly, and it'll work: it has one entry-point (like CAR code), one exit point (calling into common C code to load the next stage), and everything inbetween is compiled by romcc to work without RAM. Should we find out that all the hundred ancient ram inits we get contributed reimplement the same things over and over, we can still consider moving those parts to src/lib/romcc, neatly separated from regular romstage code. Regards, Patrick

5 years, 1 month

2
1
0 / 0

Re: [coreboot] [announce] coreboot for the 21st century

by Patrick Georgi

Am 2014-03-27 14:00, schrieb Andrew Wu: > So if I want to get rid of romcc, maybe I have to write DRAM init code > in assembly, That is not very easy. :( If you can make it compile in romcc without relying on coreboot base libraries, we could keep Vortex86 RAM init building via romcc. As I understand Stefan, his main motivation for this push is to clean out all the romcc related special cases in coreboot's core. Patrick

5 years, 1 month

4
4
0 / 0

ThinkPad T60p coreboot config file

by Thom Lauret

Hi all, I have a ThinkPad T60p 2007-CTO. Does anyone know the flash chip used and have a known working config file ? I know this model has been successfully flashed. Don't want to have to disassemble my laptop. That disassembly is required to identify the flash chip is going to slow coreboot adoption. Thom

5 years, 1 month

3
2
0 / 0

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coreboot March 2014