December 2016 - coreboot - mail.coreboot.org

Lenovo T410 Coreboot
by A. Veek Dec. 14, 2018

Dec. 14, 2018

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Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett Sept. 12, 2017

Sept. 12, 2017

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

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CPU Turbo [KGPE-D16]
by Taiidan＠gmx.com March 16, 2017

March 16, 2017

I am wondering as to: * Why 6274 cpu refuses to turbo to the second turbo state with half of the cores in use (it stops around 100mhz before the first turbo state) * Is it possible to force enable second turbo state for all cpu cores, assuming adequate cooling? Or is it controlled on the CPU itself? Off topic but would rather not make another thread: * Does NUMA ram alignment matter performance wise with only one physical CPU? (RAM being split half and half per core set at the moment) * Does anyone know where I could get a reasonably priced 6287SE or 6284SE? or (even better) an engineering model of 62xx?

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ASUS KCMA-D8 workstation board port offer
by Timothy Pearson Jan. 20, 2017

Jan. 20, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 All, After reviewing some of the comments on the ASUS KGPE-D16 being essentially too large of a system and too expensive for many people, and the fact that modern, blob-free systems are not really available in the mid-range arena, Raptor Engineering would like to offer to create a native initalization blob-free port for the ASUS KCMA-D8, which is essentially the KGPE-D16's ATX-compatible "little brother". We would be asking $15,000 for the port, including upstreaming to the master coreboot tree. We already have extensive experience with these Family 10h/15h boards, and would be able to create a port of similar quality to the existing KGPE-D16 source in terms of both code quality and overall functionality. If this is something you might be interested in please let me know. We are able to accept multiple payments from various sources for the same project (within limits), so if this is something your local Linux groups or similar might be interested in we should be able to keep the cost on any one individual or organization to a reasonable level. Thank you for your consideration, - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) http://www.raptorengineeringinc.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJWQROpAAoJEK+E3vEXDOFbR2cH/3FTqGFH+cU/HVrBUPcoKjii h9OC7SGeXdyoLZvob/YayG+g47Yppkg2um4pAC7dmGl/OXtkGh13hlsrQ8BNiYcz g0kQUdNKYh9dmBC3YnlxU6a7psh473TdyuLILrl7/8WgI8DZnRtjy62Oo5k6XAKW jfYb/bGC8I3tArYrgQDmFxz2dOejuTZit56I+mbWNtvbuQov2BDmrPPMLRuEvG3M QHCAo/Pjaajzl4rmtrgu0GHcxHsgAnJcnrcPkFYeSDKt7QxSTNOB6NqhcnYdh1SY RiA5Z/3enuDs+XNhS+6qMeKOcrEuf+Ccs7sGsgq5tWm20JA+bBoByvrXhHqVUxU= =DKfR -----END PGP SIGNATURE-----

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Minifree Libreboot D16 server/workstation launched
by Leah Rowe Jan. 9, 2017

Jan. 9, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Hi all, Minifree has launched a new freedom-friendly computer. Two, in fact. Desktop/workstation version: https://minifree.org/product/libreboot-d16/ Server version: https://minifree.org/product/libreboot-d16-server/ This is a high-end AMD server platform, being sold in server and extended ATX (desktop/workstation) form factor. It comes with Debian and Libreboot preinstalled. This is the first modern commercial system available today that can be configured to run entirely free software; first Debian, the OS, and then libreboot, a free/libre BIOS implementation. With Debian and Libreboot, this is a fully free system containing zero binary blobs of any kind. This has positive implications for security in terms of audability, and therefore privacy in general (no backdoors!). It's also free software friendly, so there are zero binary blobs and zero proprietary software running on it in the OS or BIOS. You have all of the four freedoms over each part of the boot process, which means that you the user are in full control. For the first time ever, it is possible for companies to use libreboot-enabled hardware. The problem so far with Libreboot and Minifree is that it only focussed on low-end hardware. The launch of the D16 Server and D16 Desktop changes that. With this hardware you can: * do actual, serious work e.g. programming or 3D modeling. Software development nowadays requires powerful computers, because software becomes more complex. The sheer amount of time to build from source can be a problem on its own. The D16 can support up to 16 fast AMD Opteron cores per CPU, and 2 CPUs are possible so 32 cores in total. This is ideal for software development. * provide professional hosting services for paying clients, and run a small ISP * provide servers inside organisations * play modern games (libre ones) * etc (anything that requires a fast computer, basically) Spread the word! - -- Leah Rowe Libreboot developer Use free software. Free as in freedom. https://en.wikipedia.org/wiki/Free_software Use a free operating system, GNU+Linux. https://libreboot.org/docs/distros/ Or BSD: https://libreboot.org/docs/bsd/ Use a free BIOS. https://libreboot.org/ Support computer user freedom. https://peers.community/ Minifree Ltd, trading as Ministry of Freedom | Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK | Web: https://minifree.org/ -----BEGIN PGP SIGNATURE----- iQEcBAEBCAAGBQJYZmzjAAoJEP9Ft0z50c+UEikIAIITYZYamKacnYffR9Tw1VGA 2c4qD9u2hiAZb9/9CEaF0sFd6Z0GQdxfbvCWccBQqoR9WVa27jPUW7MgFm+wXYlJ r7nPm3q4MxWodHKFUdu/3mzxH7W/W1QUeCOoqXRHe2uUHoWT/pID/eXrhbjo62ZP Cuci4mMTHBrHt81nwQ+nO5COJXMJDVGs1h9RpJjbhKiyZP0lVIe4mD4ZNgu8eCI2 FW5dJS4NS8i63Zu3B8hCkHEvYE2pdiEBUraHmlUu57L8rxI9rM4kFFChFYvoNZnp Sl+mGfPk3GQPH009DzsaekEj44C1/zKGNbPAj3t1telRCu1Ffh0poWhzxuChrFU= =Cnub -----END PGP SIGNATURE-----

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Re: [coreboot] F2A-85M: Different VGA BIOS needed after CPU Upgrade?
by Daniel Kulesz Jan. 8, 2017

Jan. 8, 2017

Hi John, > It sounds to me as though the PCI id's of the graphics card for the > upgraded CPU may be different (I could be totally wrong about that, so I > defer to others on the list if I'm barking up the wrong tree) and your > coreboot image may need to be updated accordingly. Of course, it could > also be the video BIOS that's the problem as you've suggested. Thank you for the hint. I inspected that, but the PCI-IDs actually look the same: 00:01.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Trinity [Radeon HD 7480D] [1002:9993] (A4-5300) and 00:01.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Richland [Radeon HD 8670D] (prog-if 00 [VGA controller]) (A10-6700) Looks like the VGA BIOS is really different: # diff vgabios_a4-5300.bin vgabios_a10_6700.bin Binary files vgabios_a4-5300.bin and vgabios_a10_6700.bin differ Guess I will have to to "update" the VGA BIOS then. Cheers, Daniel > > Hi Daniel, > > > Kind Regards, > > John. > > > On 28/06/16 09:24, Daniel Kulesz via coreboot wrote: > > Hi folks, > > > > I upgraded the CPU in my F2A-85M from a A4-5300 (Trinity) to a A10-6700 (Richland). The board had Coreboot installed before with the VGA BIOS extracted from the A4-5300. However, I did not get any video output when trying to boot after the upgrade, so I replaced the flash chip with a backup with the vendor BIOS that works. > > > > Is it likely that the A10-6700 needs a different VGA BIOS or does this this rather look like a different issue? I don't want to experiment too much because the BIOS chips are hardware-wise pretty fragile (even when using the extractor tool). > > > > Cheers, Daniel > >

1 1

Offering Gigabyte GA-890FXA-UD5 for porting
by Merlin Büge Jan. 1, 2017

Jan. 1, 2017

Hey all, I have a nice Gigabyte mainboard which I don't need/use anymore: A Gigabyte GA-890FXA-UD5 (rev. 2.0 or 2.1) http://www.gigabyte.de/products/product-page.aspx?pid=3519 Since I like libre-friendly computing hardware, I'd find it nice to see libreboot running on it. I'm not sure, but from what I see, it should be libreboot compatible? Could someone more knowledged than me confirm this? If someone is interested in porting this board to coreboot, and if there are no big foreseeable obstacles to porting it to lireboot, I'd be happy donating that board together with a Phenom II 965 and 4G RAM, preferrable to someone in Germany or within the EU (shipping costs). Regards, Merlin -- Merlin Büge <toni(a)bluenox07.de>

4 6

Re: [coreboot] How does intelmetool's support for Skylake?
by Zoran Stojsavljevic Dec. 30, 2016

Dec. 30, 2016

Shawn, I did the following (for other purposes, but it will also serve to this email thread cause): took another 160 GB SSD, which is sitting with me/in the drawer about 3 years now. I installed dual-boot UEFI machine: WIN10 64 Pro and bare Fedora 25 Server Edition on my HP EliteBook 840 G1 i5-4300U (HSW ULT) HW as test machine, I just put away my real Samsung 500GB SSD. I needed to solve several obstacles, and address some more issues. But now everything works. In other words, I have REAL F25 Server Edition with GNOME + Xfce DT FGXes working seamlessly/ported on bare HW. Tomorrow I'll try to run intelmetool from the latest Coreboot on the real HW, and see how it behaves. Please, stay tuned! Zoran On Fri, Dec 30, 2016 at 11:25 AM, Shawn <citypw(a)gmail.com> wrote: > This is a work around patch( I think?): > https://github.com/hardenedlinux/intelmetool/commit/ > ad778fc347b2bb0494abe2186632a072b8ad1a11 > > ./intelmetool -s > RCBA at 0x00000000 > MEI not hidden on PCI, checking if visible > MEI found: [8086:9d3a] Sunrise Point-LP CSME HECI > > ME Status : 0xa0000245 > ME Status 2 : 0x86110306 > > ME: FW Partition Table : OK > ME: Bringup Loader Failure : NO > ME: Firmware Init Complete : YES > ME: Manufacturing Mode : NO > ME: Boot Options Present : NO > ME: Update In Progress : NO > ME: Current Working State : Normal > ME: Current Operation State : M0 with UMA > ME: Current Operation Mode : Normal > ME: Error Code : No Error > ME: Progress Phase : Clean Moff->Mx wake > ME: Power Management Event : Pseudo-global reset > ME: Progress Phase State : Unknown 0x11 > > PCI READ [bc] : 0x000000bc > ME: Extend Register not valid > > ME seems okay on this board > WRITE [00] : CB: 0x80040007 > WRITE [00] : CB: 0x000002ff > READ [08] : CB: 0x801c0007 > READ [08] : CB: 0x000082ff > READ [08] : CB: 0x000b0000 > READ [08] : CB: 0x0000049c > READ [08] : CB: 0x000b0000 > READ [08] : CB: 0x0000049c > READ [08] : CB: 0x000b0000 > READ [08] : CB: 0x0000049c > ME: Firmware Version 11.0.1180.0 (code) 11.0.1180.0 (recovery) > 11.0.1180.0 (fitc) > WRITE [00] : CB: 0x80080007 > WRITE [00] : CB: 0x00000203 > WRITE [00] : CB: 0x00000000 > READ [08] : CB: 0x800d0007 > READ [08] : CB: 0x00008203 > READ [08] : CB: 0x00000000 > READ [08] : CB: 0x111a4004 > READ [08] : CB: 0x00000031 > ME Capability: Full Network manageability : OFF > ME Capability: Regular Network manageability : OFF > ME Capability: Manageability : OFF > ME Capability: Small business technology : OFF > ME Capability: Level III manageability : OFF > ME Capability: IntelR Anti-Theft (AT) : OFF > ME Capability: IntelR Capability Licensing Service (CLS) : ON > ME Capability: IntelR Power Sharing Technology (MPC) : OFF > ME Capability: ICC Over Clocking : ON > ME Capability: Protected Audio Video Path (PAVP) : ON > ME Capability: IPV6 : OFF > ME Capability: KVM Remote Control (KVM) : OFF > ME Capability: Outbreak Containment Heuristic (OCH) : OFF > ME Capability: Virtual LAN (VLAN) : ON > ME Capability: TLS : OFF > ME Capability: Wireless LAN (WLAN) : OFF > exiting > > On Fri, Dec 30, 2016 at 11:04 AM, Shawn <citypw(a)gmail.com> wrote: > > Hi Zoran, > > > > Thanks for the info. I added my Device ID into the intelmetool.h: > > > > diff --git a/intelmetool.h b/intelmetool.h > > index d79d6b0..16ca43a 100644 > > --- a/intelmetool.h > > +++ b/intelmetool.h > > @@ -225,6 +225,7 @@ > > #define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 > > #define PCI_DEVICE_ID_INTEL_ICH9R 0x2916 > > #define PCI_DEVICE_ID_INTEL_ICH9 0x2918 > > +#define PCI_DEVICE_ID_INTEL_SUNRISE 0x9d3a > > > > #define PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(x) ( \ > > ( (x) == PCI_DEVICE_ID_INTEL_ICH8 ) || \ > > @@ -232,6 +233,7 @@ > > ( (x) == PCI_DEVICE_ID_INTEL_ICH9DH ) || \ > > ( (x) == PCI_DEVICE_ID_INTEL_ICH9DO ) || \ > > ( (x) == PCI_DEVICE_ID_INTEL_ICH9R ) || \ > > + ( (x) == PCI_DEVICE_ID_INTEL_SUNRISE ) || \ > > ( (x) == PCI_DEVICE_ID_INTEL_ICH9 )) > > > > // Not sure at all > > > > This one should be the ME? > > +-16.0 Intel Corporation Sunrise Point-LP CSME HECI [8086:9d3a] > > > > #./intelmetool -s > > Not sure if ME hardware is present because you have a `Sunrise > > Point-LP CSME HECI`, but it is possible to disable it if you do, > > continuing... > > RCBA at 0x00000000 > > MEI not hidden on PCI, checking if visible > > MEI device not found, huh? > > exiting > > > > > > > > On Thu, Dec 29, 2016 at 12:50 AM, Zoran Stojsavljevic > > <zoran.stojsavljevic(a)gmail.com> wrote: > >>>> I'm not sure if intelmetool support Skylake as well. > >> > >> Investigated more. The coreboot intelmetool is the latest one, as I > >> understood (comparing one from github and coreboot). > >> > >> And Sunrise Point is NOT supported (look into latest coreboot's > >> coreboot/util/intelmetool/intelmetool.h). You can try to add it (as > Device > >> ID), manually, peek around the C code, and see if this can help you. > >> > >> Zoran > >> > >> On Wed, Dec 28, 2016 at 5:26 PM, Zoran Stojsavljevic > >> <zoran.stojsavljevic(a)gmail.com> wrote: > >>> > >>> Hello Shawn, > >>> > >>> Please, follow my CLI transcript from my Future Fedora 26 VM over WIN10 > >>> (now rawhide) with Fedora 4.8.15 kernel implanted (kernel 4.10.0-rc0 > gives > >>> me lot of griefs, I do not trust it, so I eliminated it for now): > >>> > >>> [zoran@localhost ~]$ cd projects/ > >>> [zoran@localhost projects]$ mkdir intelmetool > >>> [zoran@localhost projects]$ cd intelmetool/ > >>> [zoran@localhost intelmetool]$ pwd > >>> /home/zoran/projects/intelmetool > >>> [zoran@localhost intelmetool]$ uname -r > >>> 4.8.15-300.fc25.x86_64 > >>> [zoran@localhost intelmetool]$ git clone > >>> https://github.com/zamaudio/intelmetool.git > >>> Cloning into 'intelmetool'... > >>> remote: Counting objects: 214, done. > >>> remote: Total 214 (delta 0), reused 0 (delta 0), pack-reused 214 > >>> Receiving objects: 100% (214/214), 72.42 KiB | 0 bytes/s, done. > >>> Resolving deltas: 100% (125/125), done. > >>> [zoran@localhost intelmetool]$ ls -al > >>> total 12 > >>> drwxrwxr-x. 3 zoran zoran 4096 Dec 28 17:06 . > >>> drwxrwxr-x. 10 zoran zoran 4096 Dec 28 17:05 .. > >>> drwxrwxr-x. 3 zoran zoran 4096 Dec 28 17:06 intelmetool > >>> [zoran@localhost intelmetool]$ cd intelmetool/ > >>> [zoran@localhost intelmetool]$ ls -al > >>> total 100 > >>> drwxrwxr-x. 3 zoran zoran 4096 Dec 28 17:06 . > >>> drwxrwxr-x. 3 zoran zoran 4096 Dec 28 17:06 .. > >>> drwxrwxr-x. 8 zoran zoran 4096 Dec 28 17:06 .git > >>> -rw-rw-r--. 1 zoran zoran 16 Dec 28 17:06 .gitignore > >>> -rw-rw-r--. 1 zoran zoran 8956 Dec 28 17:06 intelmetool.c > >>> -rw-rw-r--. 1 zoran zoran 9783 Dec 28 17:06 intelmetool.h > >>> -rw-rw-r--. 1 zoran zoran 532 Dec 28 17:06 LICENSE > >>> -rw-rw-r--. 1 zoran zoran 351 Dec 28 17:06 Makefile > >>> -rw-rw-r--. 1 zoran zoran 16810 Dec 28 17:06 me.c > >>> -rw-rw-r--. 1 zoran zoran 10622 Dec 28 17:06 me.h > >>> -rw-rw-r--. 1 zoran zoran 7246 Dec 28 17:06 me_status.c > >>> -rw-rw-r--. 1 zoran zoran 1109 Dec 28 17:06 mmap.c > >>> -rw-rw-r--. 1 zoran zoran 224 Dec 28 17:06 mmap.h > >>> -rw-rw-r--. 1 zoran zoran 90 Dec 28 17:06 README.md > >>> [zoran@localhost intelmetool]$ su -m > >>> Password: > >>> [root@localhost intelmetool]# make > >>> gcc -Wall -O0 -g -I. -c me_status.c -o me_status.o > >>> gcc -Wall -O0 -g -I. -c me.c -o me.o > >>> me.c: In function ‘mei_dump’: > >>> me.c:63:18: warning: variable ‘csr’ set but not used > >>> [-Wunused-but-set-variable] > >>> struct mei_csr *csr; > >>> ^~~ > >>> gcc -Wall -O0 -g -I. -c mmap.c -o mmap.o > >>> mmap.c: In function ‘map_physical_exact’: > >>> mmap.c:11:26: warning: passing argument 1 of ‘mmap’ makes pointer from > >>> integer without a cast [-Wint-conversion] > >>> virt_addr = mmap(mapto, len, PROT_WRITE | PROT_READ, > >>> MAP_SHARED|MAP_FIXED, > >>> ^~~~~ > >>> In file included from mmap.h:4:0, > >>> from mmap.c:1: > >>> /usr/include/sys/mman.h:57:14: note: expected ‘void *’ but argument is > of > >>> type ‘uint64_t {aka long unsigned int}’ > >>> extern void *mmap (void *__addr, size_t __len, int __prot, > >>> ^~~~ > >>> gcc -Wall -O0 -g -I. -o intelmetool intelmetool.o me_status.o me.o > mmap.o > >>> -lpci > >>> [root@localhost intelmetool]# date > >>> Wed Dec 28 17:07:26 CET 2016 > >>> [root@localhost intelmetool]# ls -al > >>> total 228 > >>> drwxrwxr-x. 3 zoran zoran 4096 Dec 28 17:07 . > >>> drwxrwxr-x. 3 zoran zoran 4096 Dec 28 17:06 .. > >>> drwxrwxr-x. 8 zoran zoran 4096 Dec 28 17:06 .git > >>> -rw-rw-r--. 1 zoran zoran 16 Dec 28 17:06 .gitignore > >>> -rwxr-xr-x. 1 root root 47008 Dec 28 17:07 intelmetool > >>> -rw-rw-r--. 1 zoran zoran 8956 Dec 28 17:06 intelmetool.c > >>> -rw-rw-r--. 1 zoran zoran 9783 Dec 28 17:06 intelmetool.h > >>> -rw-rw-r--. 1 zoran zoran 22144 Dec 28 17:06 intelmetool.o > >>> -rw-rw-r--. 1 zoran zoran 532 Dec 28 17:06 LICENSE > >>> -rw-rw-r--. 1 zoran zoran 351 Dec 28 17:06 Makefile > >>> -rw-rw-r--. 1 zoran zoran 16810 Dec 28 17:06 me.c > >>> -rw-rw-r--. 1 zoran zoran 10622 Dec 28 17:06 me.h > >>> -rw-r--r--. 1 root root 28984 Dec 28 17:07 me.o > >>> -rw-rw-r--. 1 zoran zoran 7246 Dec 28 17:06 me_status.c > >>> -rw-r--r--. 1 root root 15704 Dec 28 17:07 me_status.o > >>> -rw-rw-r--. 1 zoran zoran 1109 Dec 28 17:06 mmap.c > >>> -rw-rw-r--. 1 zoran zoran 224 Dec 28 17:06 mmap.h > >>> -rw-r--r--. 1 root root 7648 Dec 28 17:07 mmap.o > >>> -rw-rw-r--. 1 zoran zoran 90 Dec 28 17:06 README.md > >>> [root@localhost intelmetool]# ./intelmetool > >>> ME is not present on your board because we found a `82371AB/EB/MB PIIX4 > >>> ISA`, you are safe, exiting > >>> [root@localhost intelmetool]# > >>> _______ > >>> > >>> Do NOT forget: I run Fedora rawhide on VMWorkstation 12.5.2 Type 2 HYP > on > >>> the top of WIN10 64 Pro! > >>> > >>> Please, do the same on Mint18 distro on raw HW, and see if this will > give > >>> you some different results then what you have presently? > >>> > >>> Please, let us know! > >>> > >>> Zoran > >>> > >>> On Wed, Dec 28, 2016 at 11:06 AM, Shawn <citypw(a)gmail.com> wrote: > >>>> > >>>> Hi Zoran, > >>>> > >>>> I created hwdb.bin via: > >>>> > >>>> # udevadm hwdb --update > >>>> > >>>> The result is still "segfault". dmesg: > >>>> > >>>> [ 972.044664] intelmetool[5055]: segfault at 16 ip 000000000040169e > >>>> sp 000072ed96a44680 error 4 in intelmetool[400000+6000] > >>>> [ 972.044674] grsec: Segmentation fault occurred at 0000000000000016 > >>>> in /usr/local/bin/intelmetool[intelmetool:5055] uid/euid:0/0 > >>>> gid/egid:0/0, parent /bin/bash[bash:4332] uid/euid:0/0 gid/egid:0/0 > >>>> [ 972.044685] grsec: denied resource overstep by requesting 4096 for > >>>> RLIMIT_CORE against limit 0 for > >>>> /usr/local/bin/intelmetool[intelmetool:5055] uid/euid:0/0 > >>>> gid/egid:0/0, parent /bin/bash[bash:4332] uid/euid:0/0 gid/egid:0/0 > >>>> > >>>> > >>>> On Mon, Dec 26, 2016 at 9:49 PM, Zoran Stojsavljevic > >>>> <zoran.stojsavljevic(a)gmail.com> wrote: > >>>> > Not sure if your strace log has anything to do with intelmetool. > >>>> > > >>>> > I did on your strace log the following (and in RED is possible > cause of > >>>> > your > >>>> > problems): > >>>> > > >>>> > [zoran@localhost projects]$ cat crash.log | grep ENOENT > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > open("/usr/share/misc/pci.ids.gz", O_RDONLY) = -1 ENOENT (No such > file > >>>> > or > >>>> > directory) > >>>> > connect(4, {sa_family=AF_LOCAL, sun_path="/var/run/nscd/socket"}, > 110) > >>>> > = -1 > >>>> > ENOENT (No such file or directory) > >>>> > connect(4, {sa_family=AF_LOCAL, sun_path="/var/run/nscd/socket"}, > 110) > >>>> > = -1 > >>>> > ENOENT (No such file or directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > access("/etc/ld.so.nohwcap", F_OK) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > open("/root/.pciids-cache", O_RDONLY) = -1 ENOENT (No such file or > >>>> > directory) > >>>> > open("/etc/systemd/hwdb/hwdb.bin", O_RDONLY|O_CLOEXEC) = -1 ENOENT > (No > >>>> > such > >>>> > file or directory) > >>>> > open("/etc/udev/hwdb.bin", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such > >>>> > file or > >>>> > directory) > >>>> > open("/usr/lib/systemd/hwdb/hwdb.bin", O_RDONLY|O_CLOEXEC) = -1 > ENOENT > >>>> > (No > >>>> > such file or directory) > >>>> > open("/lib/systemd/hwdb/hwdb.bin", O_RDONLY|O_CLOEXEC) = -1 ENOENT > (No > >>>> > such > >>>> > file or directory) > >>>> > [zoran@localhost projects]$ > >>>> > > >>>> > I guess, you have one very important missing file in your Linux > >>>> > configuration, this one: /etc/systemd/hwdb/hwdb.bin... > >>>> > /etc/udev/hwdb.bin ?! > >>>> > > >>>> > Here is good read: > >>>> > https://www.freedesktop.org/software/systemd/man/hwdb.html > >>>> > > >>>> > http://www.dsm.fordham.edu/cgi-bin/man-cgi.pl?topic= > systemd-hwdb&ampsect=8 > >>>> > > >>>> > Have no idea who is creating this file, but you can check your Linux > >>>> > distro > >>>> > / tree with the following paths to find hwdb.bin: > >>>> > > >>>> > /etc/systemd/hwdb/hwdb.bin > >>>> > /etc/udev/hwdb.bin <<======= In my Fedora > rawhide VM > >>>> > (future Fedora 26) I have here hwdb.bin ======= > >>>> > /usr/lib/systemd/hwdb/hwdb.bin > >>>> > /lib/systemd/hwdb/hwdb.bin > >>>> > > >>>> > If you don't have in any, please, create one with the following > link: > >>>> > > >>>> > http://www.dsm.fordham.edu/cgi-bin/man-cgi.pl?topic= > systemd-hwdb&ampsect=8 > >>>> > > >>>> > Please, let us know! > >>>> > > >>>> > Zoran > >>>> > > >>>> > On Mon, Dec 26, 2016 at 3:42 PM, Shawn <citypw(a)gmail.com> wrote: > >>>> >> > >>>> >> Hi, > >>>> >> > >>>> >> intelmetool occurs "segfault" on my laptop running Mint 18 with > >>>> >> PaX/Grsecurity 4.7.10. The PCI info: > >>>> >> > >>>> >> -[0000:00]-+-00.0 Intel Corporation Sky Lake Host Bridge/DRAM > >>>> >> Registers [8086:1904] > >>>> >> +-02.0 Intel Corporation Sky Lake Integrated Graphics > >>>> >> [8086:1916] > >>>> >> +-04.0 Intel Corporation Skylake Processor Thermal > >>>> >> Subsystem [8086:1903] > >>>> >> +-14.0 Intel Corporation Sunrise Point-LP USB 3.0 xHCI > >>>> >> Controller [8086:9d2f] > >>>> >> +-14.2 Intel Corporation Sunrise Point-LP Thermal > >>>> >> subsystem [8086:9d31] > >>>> >> +-15.0 Intel Corporation Sunrise Point-LP Serial IO I2C > >>>> >> Controller [8086:9d60] > >>>> >> +-15.1 Intel Corporation Sunrise Point-LP Serial IO I2C > >>>> >> Controller [8086:9d61] > >>>> >> +-16.0 Intel Corporation Sunrise Point-LP CSME HECI > >>>> >> [8086:9d3a] > >>>> >> +-1c.0-[01]----00.0 NVIDIA Corporation GM107M [GeForce > GTX > >>>> >> 960M] [10de:139b] > >>>> >> +-1c.4-[02]----00.0 Samsung Electronics Co Ltd NVMe SSD > >>>> >> Controller [144d:a802] > >>>> >> +-1c.6-[03]----00.0 Qualcomm Atheros Killer E2400 > Gigabit > >>>> >> Ethernet Controller [1969:e0a1] > >>>> >> +-1c.7-[04]----00.0 Qualcomm Atheros QCA6174 802.11ac > >>>> >> Wireless Network Adapter [168c:003e] > >>>> >> +-1d.0-[05]----00.0 Samsung Electronics Co Ltd NVMe SSD > >>>> >> Controller [144d:a802] > >>>> >> +-1d.2-[06-3e]-- > >>>> >> +-1f.0 Intel Corporation Sunrise Point-LP LPC > Controller > >>>> >> [8086:9d48] > >>>> >> +-1f.2 Intel Corporation Sunrise Point-LP PMC > [8086:9d21] > >>>> >> +-1f.3 Intel Corporation Sunrise Point-LP HD Audio > >>>> >> [8086:9d70] > >>>> >> \-1f.4 Intel Corporation Sunrise Point-LP SMBus > >>>> >> [8086:9d23] > >>>> >> > >>>> >> The crash log was attached! I'm not sure if intelmetool support > >>>> >> Skylake as well. One tiny feature of PaX/Grsecurity prevent the > ioperm > >>>> >> for killing the potential threats in case which > >>>> >> the adversary re-flash the SPI ROM once they get the root priv. It > >>>> >> does affect flashrom but intelmetool. I also ran intelmetool on the > >>>> >> distro( Mint 18) kernel and got the same result. > >>>> >> > >>>> >> > >>>> >> -- > >>>> >> GNU powered it... > >>>> >> GPL protect it... > >>>> >> God blessing it... > >>>> >> > >>>> >> regards > >>>> >> Shawn > >>>> >> > >>>> >> -- > >>>> >> coreboot mailing list: coreboot(a)coreboot.org > >>>> >> https://www.coreboot.org/mailman/listinfo/coreboot > >>>> > > >>>> > > >>>> > >>>> > >>>> > >>>> -- > >>>> GNU powered it... > >>>> GPL protect it... > >>>> God blessing it... > >>>> > >>>> regards > >>>> Shawn > >>> > >>> > >> > > > > > > > > -- > > GNU powered it... > > GPL protect it... > > God blessing it... > > > > regards > > Shawn > > > > -- > GNU powered it... > GPL protect it... > God blessing it... > > regards > Shawn >

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Re: [coreboot] How to add a new SuperIO ?
by Agrain Patrick Dec. 30, 2016

Dec. 30, 2016

Hello all, Thanks to all that took time to review the first set of patch concerning the support of the Exar XR28V382. Console log messages are now fine. The error lies in the ‘end’ tag of the LPC pci device inside the devicetree.cb file. Now, console messages looks as following: <…> PCI: 00:1f.0 [8086/1f38] enabled PCI: 00:1f.3 [8086/1f3c] enabled PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [10ee/7011] enabled PCIE CLK PM is not supported by endpointASPM: Enabled None scan_bus: scanning of bus PCI: 00:02.0 took 5054 usecs PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.8 disabled <…> PCI: 01:00.0 init ... OXE: Set Bus Master on FPGA. PCI: 01:00.0 init finished in 2148 usecs PNP: 002e.0 init ... EXAR: Enter init() EXAR: Get Device ID 0xffff PNP: 002e.0 init finished in 2841 usecs Devices initialized <…> Now, I have to see why Device ID is returned with a wrong value. Best regards, Patrick Agrain De : coreboot [mailto:coreboot-bounces@coreboot.org] De la part de Agrain Patrick Envoyé : jeudi 29 décembre 2016 13:49 À : coreboot(a)coreboot.org Objet : Re: [coreboot] How to add a new SuperIO ? Hello all, I’ve pushed the code to support the EXAR SuperIO XR28V382. It is marked “[WIP]” with “XR28V382” in the title. Can anybody have a look at it and meaby point me to a bug, missing configuration or other… that could explain the messages on the console displayed below ? Thanks. Patrick Agrain De : coreboot [mailto:coreboot-bounces@coreboot.org] De la part de Agrain Patrick Envoyé : jeudi 29 décembre 2016 09:43 À : ron minnich; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Objet : Re: [coreboot] How to add a new SuperIO ? Hi Ron, Thanks for the advice. It would be the first time that I will push code into a GIT project with Gerrit. Therefore, let me a few moment to gather all required information to perform this without disturbance for others. For the moment, I pulled the Coreboot project and add/modify the required files. Platform build is OK. Now, the push… if you have any checklist to follow, it could be helpful. Best regards, Patrick Agrain De : ron minnich [mailto:rminnich@gmail.com] Envoyé : vendredi 16 décembre 2016 19:18 À : Agrain Patrick; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Objet : Re: [coreboot] How to add a new SuperIO ? it's way easier if you push your changes to gerrit marked as a WIP. People can see the code and will likely spot any problems very quickly. On Fri, Dec 16, 2016 at 12:40 AM Agrain Patrick <patrick.agrain(a)al-enterprise.com<mailto:patrick.agrain@al-enterprise.com>> wrote: Hi all, I'm trying to add a new superIO chip to the source tree. The chip is an EXAR XR28V932. I tried to take example of the existing superIO chips, like the i3100 and it8716 to compose a correct source tree as following: [agrain1@frilldlin059 coreboot]$ ls -als ./src/superio/exar/xr28v382/ total 10 1 drwxr-xr-x 2 agrain1 dhs2 512 Dec 16 09:03 . 1 drwxr-xr-x 3 agrain1 dhs2 512 Dec 15 09:41 .. 1 -rw-r--r-- 1 agrain1 dhs2 687 Dec 15 09:34 Makefile.inc 3 -rw-r--r-- 1 agrain1 dhs2 2614 Dec 16 09:03 superio.c 2 -rw-r--r-- 1 agrain1 dhs2 1287 Dec 15 16:28 xr28v382.h I modified the devicetree.cb of my board (based on an Intel Mohon Peak) as following: device pci 1f.0 on end # LPC bridge chip superio/exar/xr28v382 # Super I/O device pnp 2e.0 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.1 off # Com2 end device pnp 2e.8 off # Watchdog end end device pci 1f.3 on end # SMBus 0 Now the output of the console log (DEBUG level): <...> PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1f0f] enabled PCI: Static device PCI: 00:01.0 not found, disabling it. child PNP: 002e.0 not a PCI device child PNP: 002e.1 not a PCI device child PNP: 002e.8 not a PCI device child PNP: 002e.0 not a PCI device child PNP: 002e.1 not a PCI device child PNP: 002e.8 not a PCI device child PNP: 002e.0 not a PCI device child PNP: 002e.1 not a PCI device child PNP: 002e.8 not a PCI device child PNP: 002e.0 not a PCI device <...> PCI: 00:1f.0 [8086/1f38] enabled child PNP: 002e.0 not a PCI device child PNP: 002e.1 not a PCI device child PNP: 002e.8 not a PCI device child PNP: 002e.0 not a PCI device child PNP: 002e.1 not a PCI device child PNP: 002e.8 not a PCI device child PNP: 002e.0 not a PCI device child PNP: 002e.1 not a PCI device child PNP: 002e.8 not a PCI device PCI: 00:1f.3 [8086/1f3c] enabled child PNP: 002e.0 not a PCI device <...> PCI: Left over static devices: PNP: 002e.0 PNP: 002e.1 PNP: 002e.8 PCI: Check your devicetree.cb. PCI: pci_scan_bus for bus 01 <...> DOMAIN: 0000 (Intel Rangeley Northbridge) PCI: 00:00.0 (Intel Rangeley Northbridge) PCI: 00:01.0 (Intel Rangeley Northbridge) PCI: 00:02.0 (Intel Rangeley Northbridge) PCI: 00:03.0 (Intel Rangeley Northbridge) PCI: 00:04.0 (Intel Rangeley Northbridge) PCI: 00:0b.0 (Intel Rangeley Southbridge) PCI: 00:0e.0 (Intel Rangeley Southbridge) PCI: 00:13.0 (Intel Rangeley Southbridge) PCI: 00:14.0 (Intel Rangeley Southbridge) PCI: 00:14.1 (Intel Rangeley Southbridge) PCI: 00:14.2 (Intel Rangeley Southbridge) PCI: 00:14.3 (Intel Rangeley Southbridge) PCI: 00:16.0 (Intel Rangeley Southbridge) PCI: 00:17.0 (Intel Rangeley Southbridge) PCI: 00:18.0 (Intel Rangeley Southbridge) PCI: 00:1f.0 (Intel Rangeley Southbridge) PNP: 002e.0 (EXAR XR28V382 Super I/O) PNP: 002e.1 (EXAR XR28V382 Super I/O) PNP: 002e.8 (EXAR XR28V382 Super I/O) PCI: 00:1f.3 (Intel Rangeley Southbridge) PCI: 00:0f.0 (unknown) PCI: 01:00.0 (unknown) I guess that the "" are not normal, isn't it ? And so the " Check your devicetree.cb." ? Moreover, I put a printk() in the init function of the chip and do not see it in the log. What particular point should I also check to be sure that I do not miss anything ? Thanks for your help. Best regards, Patrick Agrain -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot

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Removing ME on G45 desktop chipset - same as GM45 mobile?
by Taiidan＠gmx.com Dec. 30, 2016

Dec. 30, 2016

I am wondering if the procedure for removing ME on a GM45 mobile chipset motherboard would work on its desktop siblings, has anyone done this before? I have a G45FC from Intel which has an X4500HD graphics chipset and ICH10R southbridge.

2 1