coreboot July 2022

coreboot@coreboot.org

33 participants
36 discussions

QEMU x86 i440fx/piix4 build fails for >= 32MB ROMs - Assertion IS_HOST_SPACE_ADDRESS(host_space_address) failed
by Mike Banon 21 Feb '24

21 Feb '24

If I use a default config for i440fx/piix4, building a 16MB ROM works fine, but 32MB or 64MB doesn't work anymore: ... CC postcar/southbridge/intel/common/rtc.o LINK cbfs/fallback/postcar.debug OBJCOPY cbfs/fallback/romstage.elf CREATE build/mainboard/emulation/qemu-i440fx/cbfs-file.vqaXlP.out (from /home/my_custom_path_to/coreboot/.config) CC+STRIP src/lib/cbfs_master_header.c OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.elf OBJCOPY bootblock.raw.bin Created CBFS (capacity = 33553892 bytes) BOOTBLOCK CBFS cbfs_master_header CBFS fallback/romstage cbfstool: /home/my_custom_path_to/coreboot/util/cbfstool/cbfstool.c:1145: cbfstool_convert_mkstage: Assertion `IS_HOST_SPACE_ADDRESS(host_space_address)' failed. make: *** [Makefile.inc:1116: build/coreboot.pre] Aborted -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

6 11

[coreboot - Bug #392] (New) Coreboot 4.16 & 4.17 - SeaBios Windows 10 BSOD "ACPI Error"
by Pawel Radomychelski 15 Jan '23

15 Jan '23

Issue #392 has been reported by Pawel Radomychelski. ---------------------------------------- Bug #392: Coreboot 4.16 & 4.17 - SeaBios Windows 10 BSOD "ACPI Error" https://ticket.coreboot.org/issues/392 * Author: Pawel Radomychelski * Status: New * Priority: High * Category: board support * Target version: 4.17 * Start date: 2022-06-18 * Affected versions: 4.16, 4.17, master * Affected hardware: Lenovo ThinkPad X230 Tablet * Affected OS: Windows 10 ---------------------------------------- Since CoreBoot 4.16 my Windows 10 cant boot from SeaBios, i get BSOD with "ACPI Error" very early. Don't know which commit exactly brakes ACPI, but i can say, that in my CoreBoot 4.15 Image from 11/09/2021 Windows 10 is booting just fine from SeaBIOS. Some time later under CoreBoot 4.16 i saw that windows is BSODing. Tried yesterday with CoreBoot 4.17 and its still broken. I think, since CB4.16 there is something broken in ACPI. As i read, the problem is, that ACPI reserves some memory area, which in Windows is reserved for the system. This [[https://ticket.coreboot.org/issues/327]] seems to be a similar problem, but the guy is using TianoCore instead of SeaBIOS. Changing the line OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) to OperationRegion (OPRG, SystemMemory, ASLS, 0x1000) doesnt fix it for SeaBios, but fix it for TianoCore. ---Files-------------------------------- dmesg_cb415.txt (78.9 KB) dmesg_cb417.txt (79.9 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

7 31

[coreboot - Bug #386] (New) ASUS P8Z77-V LX2 - Raminit issue at second boot with two 8GiB DIMMs - bootloop
by gzz5f gzz5f 15 Jan '23

15 Jan '23

Issue #386 has been reported by gzz5f gzz5f. ---------------------------------------- Bug #386: ASUS P8Z77-V LX2 - Raminit issue at second boot with two 8GiB DIMMs - bootloop https://ticket.coreboot.org/issues/386 * Author: gzz5f gzz5f * Status: New * Priority: High * Category: board support * Target version: master * Start date: 2022-06-05 * Affected versions: master * Needs backport to: none * Affected hardware: ASUS P8Z77-V LX2 * Affected OS: all ---------------------------------------- I build coreboot today for the ASUS P8Z77-V LX2 and used the latest coreboot master code. The 2 8GiB DIMMs are working fine at first boot. You can start computer, install from a live media the OS and so on. But at the second boot it failes boot forever and its bootooping. It does not make a change if i boot for a second until SeaBIOS output and then turn off the computer or use the computer for longer time. The second boot is always broken. Workaround 1: Remove one of the two 8GiB DIMMs. Then the computer also starts fine after a reboot. Workaround 2: Install two 4GiB DIMMs instead of two 8GiB DIMMs. Then the computer also starts fine after reboot. Workaround 3: At every boot boot for a second with one DIMM. Turn off the computer, insert the second DIMM and start it again. kmalkki told me to rebuid the image with DEBUG_RAM_SETUP=y I then build a second image, with DEBUG_RAM_SETUP=y. The logfile contains the first successfull boot (created with Workaround 3), the poweroff and the poweron with the bootloop. I have let it bootloop few times before turned off the PSU. ---Files-------------------------------- coreboot_logfie.txt (197 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

3 3

[coreboot - Support #387] (New) Support Framework Laptop
by Jun Aruga 15 Jan '23

15 Jan '23

Issue #387 has been reported by Jun Aruga. ---------------------------------------- Support #387: Support Framework Laptop https://ticket.coreboot.org/issues/387 * Author: Jun Aruga * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2022-06-05 * Affected hardware: Framework Laptop ---------------------------------------- Dear coreboot developers, I am a user of Framework Laptop[1][2]. Thank you for working to make coreboot work on Framework Laptop! This ticket is to track the task, as I didn't see any other issue tickets about Framework Laptop here. According to the Framework founder's comment[3] below, Framework provided Framework Laptops to the coreboot community. > We've handed three systems that can boot unsigned bootloaders to folks in the coreboot community. Our plan in the near term is to help them create a shim loader that can be signed to run on any Framework Laptop, which then enables anyone to do further coreboot development. Then I saw Matthew's try to make the coreboot work on Framework Laptop,[4] but unfortunately it didn't work at that time.[5] How is the current status? What prevents coreboot from working on the Framework Laptop? How can we, people in the Framework community, help you? As a reference, there is a coreboot specific thread on the Framework community forum.[6] ## References * [1] https://frame.work/ * [2] Framework Computer - Wikipedia - https://en.wikipedia.org/wiki/Framework_Computer * [3] Framework Laptop Mainboard, Hacker News, April 20, 2022 - https://news.ycombinator.com/item?id=31097434 * [4] Matthew tries to port Coreboot to the Framework laptop - February 27, 2022 - https://www.youtube.com/watch?v=Jf_6xW-8tfQ * [5] Matthew Garrett on Twitter, February 27, 2022 - https://twitter.com/mjg59/status/1497788538212917250 * [6] Free the EC! and Coreboot Only - https://community.frame.work/t/free-the-ec-and-coreboot-only/791 -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

7 15

Cisco Meraki use coreboot in some MX products and will not provide the source code
by Hal Martin 22 Dec '22

22 Dec '22

Hello, Several Cisco Meraki products (MX84, MX250) are using the coreboot bootloader. Meraki are also distributing coreboot builds for these products via their update mechanism. In October 2021, I requested the corresponding coreboot source code for the MX84 from open-source(a)meraki.com. Another individual requested the coreboot source code for the MX250 around the same time. We own the devices in quesiton. To date, Meraki have not provided the source code or provided an explanation as to the delay in providing the source code. The last reply I received was in January, and they have not replied to any of my follow up requests. As coreboot is GPL licensed software, I wanted to inform the coreboot community that I believe Cisco Meraki are not acting in good faith and are, in my opinion, violating the GPL by not providing the coreboot source code upon request. Kind regards, Hal Martin

4 4

[coreboot - Bug #401] (New) edk2 hangs indefiniately
by Sean Rhodes 19 Oct '22

19 Oct '22

Issue #401 has been reported by Sean Rhodes. ---------------------------------------- Bug #401: edk2 hangs indefiniately https://ticket.coreboot.org/issues/401 * Author: Sean Rhodes * Status: New * Priority: Normal * Assignee: Arthur Heymans * Category: board support * Target version: none * Start date: 2022-07-08 * Affected versions: master * Affected hardware: Everything * Affected OS: Doesn't matter ---------------------------------------- Since CB:63555, edk2 will no longer boot and hangs indefiniately Various forks disable MTRR programming in edk2 (such as https://github.com/MrChromebox/edk2/commit/d641ea6920737fd9b9a94210e9a2e763…) but this shouldn't be done as it breaks spec. Workarounds are to revert CB:64804, CB:63550, CB:64803 and CB:63555. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

7 11

Intel sandybridge northbridge with ibexpeak southbridge?
by Hal Martin 18 Aug '22

18 Aug '22

Hello, I have a platform (Advantech NAMB-3250MB, used in some Riverbed appliances) which uses Sandy/Ivy Bridge CPUs, but has a DH89xxCC southbridge which according to ifdtool is Ibex Peak. [3] The ME firmware version from the vendor firmware is 6.0.50.1244 which also corresponds to Ibex Peak (Series 5) and not Cougar Point (Series 6). [1] I did not know it was possible to pair a Series 5 chipset with Sandy/Ivy Bridge, since the DH89xxCC only supports DMI 1 (intel-communications-chipset-89xx-series-datasheet.pdf page 5) and Sandy/Ivy Bridge support DMI 2.0 [2] It would appear that using northbridge/intel/sandybridge with southbridge/intel/ibexpeak in coreboot is not supported: /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/early_dmi.o: in function `early_init_dmi': /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:175: undefined reference to `early_pch_init_native_dmi_pre' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:215: undefined reference to `early_pch_init_native_dmi_post' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/raminit.o: in function `init_dram_ddr3': /opt/coreboot/src/northbridge/intel/sandybridge/raminit.c:322: undefined reference to `early_pch_init_native' src/arch/x86/Makefile.inc:185: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1 There is no early_pch_init_native_* in src/southbridge/intel/ibexpeak Is it safe to assume that IronLake northbridge is not applicable to Sandy/Ivy Bridge CPUs? In which case, I guess the only way this platform could ever be supported is if the missing early_pch_init_native_* functions are implemented for IbexPeak? Kind regards, Hal Martin [1] https://en.wikichip.org/wiki/intel/management_engine [2] https://www.intel.com/content/www/us/en/products/platforms/details/crystal-… [3] ./ifdtool dump.bin PCH Revision: 5 series Ibex Peak FLMAP0: 0x02040002 NR: 2 FRBA: 0x40 NC: 1 FCBA: 0x20 FLMAP1: 0x10100206 ISL: 0x10 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00000120 PSL: 0x0001 FMSBA: 0x200 FLUMAP1: 0x000002ef Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000ef0 ME VSCC table: JID0: 0x004b25bf SPI Component Vendor ID: 0xbf SPI Component Device ID 0: 0x25 SPI Component Device ID 1: 0x4b VSCC0: 0x20092009 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: Yes Lower Write Granularity: 1 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: Yes Upper Write Granularity: 1 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x07ff0400 Flash Region 1 (BIOS): 00400000 - 007fffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x0010001c Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 20MHz Write/Erase Clock Frequency: 20MHz Fast Read Clock Frequency: 20MHz Fast Read Support: supported Read Clock Frequency: 20MHz Component 2 Density: 4MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0 : 0x00205602 PCHSTRP1 : 0x0000010f PCHSTRP2 : 0x90000000 PCHSTRP3 : 0x00000000 PCHSTRP4 : 0x00c8e000 PCHSTRP5 : 0x00000000 PCHSTRP6 : 0x00000000 PCHSTRP7 : 0x00000000 PCHSTRP8 : 0x00000000 PCHSTRP9 : 0x00000000 PCHSTRP10 : 0x00010044 PCHSTRP11 : 0x99000097 PCHSTRP12 : 0x00000000 PCHSTRP13 : 0x00000000 PCHSTRP14 : 0x00000000 PCHSTRP15 : 0x0000000e AltMeDisable bit is not set Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0xffff0000 (Intel ME) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0xffff0118 (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 Found Processor Strap Section ????: 0x00000000 ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff

2 1

DDR4 detection issue in the Memory Down approach on the intel Denverton board
by Somanna Ankaiah 18 Aug '22

18 Aug '22

Greetings . We are working on intel c508 intel denverton board . It has a soldered 4GB DDR4 connected to Channel 0 , Dimm 0 . Below are the changes made : 1. We are using harcuvar board as a reference . I have selected * Enable Memory down option in menu config 2. Added spd values file in src/mainboard/intel/harcuvar/spd/spd_filename.hex 3. spd.bn getting generated in CBFS FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 43844 none cpu_microcode_blob.bin 0xac40 microcode 11264 none fallback/ramstage 0xd8c0 stage 71762 none config 0x1f180 raw 1353 none revision 0x1f740 raw 694 none spd.bin 0x1fa40 spd 512 none fallback/dsdt.aml 0x1fc80 raw 7791 none fallback/postcar 0x21b40 stage 23808 none fallback/payload 0x27880 simple elf 656810 none (empty) 0xc7e80 null 6651672 none fspt.bin 0x71fdc0 fsp 4096 none (empty) 0x720e00 null 3992 none fspm.bin 0x721dc0 fsp 589824 none (empty) 0x7b1e00 null 3992 none fsps.bin 0x7b2dc0 fsp 102400 none (empty) 0x7cbe00 null 114584 none bootblock 0x7e7dc0 bootblock 32768 none COREBOOT-4.13 PrivateBuild:saurabh Thu Jun 30 18:39:22 IST 2022 bootblock starting FSP TempRamInit successful... Timestamp - end of bootblock: 47603172 FMAP: Found "FLASH" version 1.1 at 0x810000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 4 FMAP: area COREBOOT found @ 810200 (8322560 bytes) CBFS DEBUG: Looking for next file @0x0... CBFS DEBUG: Found CBFS header @0x0 (type 2, attr +0x0, data +0x38, length 0x20) CBFS DEBUG: File name: 'cbfs master header' CBFS DEBUG: Looking for next file @0x58... CBFS DEBUG: Found CBFS header @0x80 (type 16, attr +0x0, data +0x64, length 0xab44) CBFS DEBUG: File name: 'fallback/romstage' CBFS: Found 'fallback/romstage' @0x80 size 0xab44 Timestamp - starting to load romstage: 136192248 Timestamp - finished loading romstage: 143418624 BS: bootblock times (exec / console): total (unknown) / 74 ms 4. Tried giving 512 values CONFIG_DIMM_SPD_SIZE=512 5. Using 4GB DDR4 module. MT40A512M16LY-062E IT:E We are using Fitc tool to generate full FW image, getting below error and got stuck after loading the build ====================================================================================== COREBOOT-4.13 PrivateBuild:saurabh Thu Jun 30 18:39:22 IST 2022 romstage starting FSP TempRamInit was successful... Board ID: 0x52. GPIO table: 0xff81a144, entry num: 0x1! Changing GpioPad PID: c2 Offset: 0x400 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! TCO base address set to 0x400! FMAP: area COREBOOT found @ 810200 (8322560 bytes) CBFS DEBUG: Looking for next file @0x0... CBFS DEBUG: Found CBFS header @0x0 (type 2, attr +0x0, data +0x38, length 0x20) CBFS DEBUG: File name: 'cbfs master header' CBFS DEBUG: Looking for next file @0x58... CBFS DEBUG: Found CBFS header @0x80 (type 16, attr +0x0, data +0x64, length 0xab44) CBFS DEBUG: File name: 'fallback/romstage' CBFS DEBUG: Looking for next file @0xac28... CBFS DEBUG: Found CBFS header @0xac40 (type 83, attr +0x38, data +0x50, length 0x2c00) CBFS DEBUG: File name: 'cpu_microcode_blob.bin' CBFS DEBUG: Looking for next file @0xd890... CBFS DEBUG: Found CBFS header @0xd8c0 (type 16, attr +0x0, data +0x38, length 0x11853) CBFS DEBUG: File name: 'fallback/ramstage' CBFS DEBUG: Looking for next file @0x1f14b... CBFS DEBUG: Found CBFS header @0x1f180 (type 80, attr +0x28, data +0x38, length 0x549) CBFS DEBUG: File name: 'config' CBFS DEBUG: Looking for next file @0x1f701... CBFS DEBUG: Found CBFS header @0x1f740 (type 80, attr +0x28, data +0x38, length 0x2b6) CBFS DEBUG: File name: 'revision' CBFS DEBUG: Looking for next file @0x1fa2e... CBFS DEBUG: Found CBFS header @0x1fa40 (type 171, attr +0x28, data +0x38, length 0x200) CBFS DEBUG: File name: 'spd.bin' CBFS DEBUG: Looking for next file @0x1fc78... CBFS DEBUG: Found CBFS header @0x1fc80 (type 80, attr +0x38, data +0x48, length 0x1e6f) CBFS DEBUG: File name: 'fallback/dsdt.aml' CBFS DEBUG: Looking for next file @0x21b37... CBFS DEBUG: Found CBFS header @0x21b40 (type 16, attr +0x0, data +0x38, length 0x5d00) CBFS DEBUG: File name: 'fallback/postcar' CBFS DEBUG: Looking for next file @0x27878... CBFS DEBUG: Found CBFS header @0x27880 (type 32, attr +0x0, data +0x38, length 0xa05aa) CBFS DEBUG: File name: 'fallback/payload' CBFS DEBUG: Looking for next file @0xc7e62... CBFS DEBUG: Found CBFS header @0xc7e80 (type -1, attr +0x0, data +0x28, length 0x657f18) CBFS DEBUG: Looking for next file @0x71fdc0... CBFS DEBUG: Found CBFS header @0x71fdc0 (type 96, attr +0x28, data +0x40, length 0x1000) CBFS DEBUG: File name: 'fspt.bin' CBFS DEBUG: Looking for next file @0x720e00... CBFS DEBUG: Found CBFS header @0x720e00 (type -1, attr +0x0, data +0x28, length 0xf98) CBFS DEBUG: Looking for next file @0x721dc0... CBFS DEBUG: Found CBFS header @0x721dc0 (type 96, attr +0x28, data +0x40, length 0x90000) CBFS DEBUG: File name: 'fspm.bin' CBFS: Found 'fspm.bin' @0x721dc0 size 0x90000 Spec version: v2.0 Revision: 0.0.1, Build Number 18 Type: release/test image ID: DNV-FSP0, base 0xfff32000 + 0x90000 Config region 0x18c + 0x200 Memory init offset 0x450 Timestamp - before RAM initialization: 2111263908 FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' bootmode is set to: 0 Relaxing the Security Config for SPI. mupd->FspmConfig.RelaxSecConfig FMAP: area COREBOOT found @ 810200 (8322560 bytes) CBFS DEBUG: Looking for next file @0x0... CBFS DEBUG: Found CBFS header @0x0 (type 2, attr +0x0, data +0x38, length 0x20) CBFS DEBUG: File name: 'cbfs master header' CBFS DEBUG: Looking for next file @0x58... CBFS DEBUG: Found CBFS header @0x80 (type 16, attr +0x0, data +0x64, length 0xab44) CBFS DEBUG: File name: 'fallback/romstage' CBFS DEBUG: Looking for next file @0xac28... CBFS DEBUG: Found CBFS header @0xac40 (type 83, attr +0x38, data +0x50, length 0x2c00) CBFS DEBUG: File name: 'cpu_microcode_blob.bin' CBFS DEBUG: Looking for next file @0xd890... CBFS DEBUG: Found CBFS header @0xd8c0 (type 16, attr +0x0, data +0x38, length 0x11853) CBFS DEBUG: File name: 'fallback/ramstage' CBFS DEBUG: Looking for next file @0x1f14b... CBFS DEBUG: Found CBFS header @0x1f180 (type 80, attr +0x28, data +0x38, length 0x549) CBFS DEBUG: File name: 'config' CBFS DEBUG: Looking for next file @0x1f701... CBFS DEBUG: Found CBFS header @0x1f740 (type 80, attr +0x28, data +0x38, length 0x2b6) CBFS DEBUG: File name: 'revision' CBFS DEBUG: Looking for next file @0x1fa2e... CBFS DEBUG: Found CBFS header @0x1fa40 (type 171, attr +0x28, data +0x38, length 0x200) CBFS DEBUG: File name: 'spd.bin' CBFS: Found 'spd.bin' @0x1fa40 size 0x200 SPD spd_data[i] 23 SPD spd_data[i] 11 SPD spd_data[i] c SPD spd_data[i] 3 SPD spd_data[i] 56 SPD spd_data[i] 21 SPD spd_data[i] 0 SPD spd_data[i] 8 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 3 SPD spd_data[i] 2 SPD spd_data[i] b SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 8 SPD spd_data[i] d SPD spd_data[i] fc SPD spd_data[i] ab SPD spd_data[i] ae SPD spd_data[i] 0 SPD spd_data[i] 78 SPD spd_data[i] 78 SPD spd_data[i] 78 SPD spd_data[i] 11 SPD spd_data[i] 8 SPD spd_data[i] 80 SPD spd_data[i] f0 SPD spd_data[i] a SPD spd_data[i] 20 SPD spd_data[i] 8 SPD spd_data[i] 0 SPD spd_data[i] 5 SPD spd_data[i] 0 SPD spd_data[i] f0 SPD spd_data[i] 2b SPD spd_data[i] 34 SPD spd_data[i] 2b SPD spd_data[i] 0 SPD spd_data[i] 78 SPD spd_data[i] 0 SPD spd_data[i] 14 SPD spd_data[i] 3c SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] c SPD spd_data[i] 2b SPD spd_data[i] 2d SPD spd_data[i] 4 SPD spd_data[i] 16 SPD spd_data[i] 35 SPD spd_data[i] 23 SPD spd_data[i] d SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 2c SPD spd_data[i] b SPD spd_data[i] 3 SPD spd_data[i] 24 SPD spd_data[i] 35 SPD spd_data[i] c SPD spd_data[i] 3 SPD spd_data[i] 2d SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] ec SPD spd_data[i] 9c SPD spd_data[i] b4 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] e7 SPD spd_data[i] c1 SPD spd_data[i] a9 SPD spd_data[i] 4d SPD spd_data[i] f SPD spd_data[i] 11 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 38 SPD spd_data[i] 41 SPD spd_data[i] 54 SPD spd_data[i] 46 SPD spd_data[i] 35 SPD spd_data[i] 31 SPD spd_data[i] 32 SPD spd_data[i] 36 SPD spd_data[i] 34 SPD spd_data[i] 48 SPD spd_data[i] 5a SPD spd_data[i] 2d SPD spd_data[i] 32 SPD spd_data[i] 47 SPD spd_data[i] 31 SPD spd_data[i] 41 SPD spd_data[i] 32 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 32 SPD spd_data[i] 80 SPD spd_data[i] 2c SPD spd_data[i] 41 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 SPD spd_data[i] 0 Memory Down function is enabled! 0x0000000000000d0a: IA32_MTRRCAP: SMRR, WC, FIX, 10 variable MTRRs 0x0000000000000800: IA32_MTRR_DEF_TYPE: E, UC 0x0000000000000000: IA32_MTRR_FIX64K_00000 0x00000000 - 0x0007ffff: UC 0x0000000000000000: IA32_MTRR_FIX16K_80000 0x00080000 - 0x0009ffff: UC 0x0000000000000000: IA32_MTRR_FIX16K_A0000 0x000a0000 - 0x000bffff: UC 0x0000000000000000: IA32_MTRR_FIX4K_C0000 0x000c0000 - 0x000c7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_C8000 0x000c8000 - 0x000cffff: UC 0x0000000000000000: IA32_MTRR_FIX4K_D0000 0x000d0000 - 0x000d7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_D8000 0x000d8000 - 0x000dffff: UC 0x0000000000000000: IA32_MTRR_FIX4K_E0000 0x000e0000 - 0x000e7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_E8000 0x000e8000 - 0x000effff: UC 0x0000000000000000: IA32_MTRR_FIX4K_F0000 0x000f0000 - 0x000f7fff: UC 0x0000000000000000: IA32_MTRR_FIX4K_F8000 0x000f8000 - 0x000fffff: UC 0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB 0x0000007ffff00800: PHYMASK0: Length = 0x0000000000100000, Valid 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP 0x0000007fff000800: PHYMASK1: Length = 0x0000000001000000, Valid 0x0000000000000000: PHYBASE2 0x0000000000000000: PHYMASK2: Disabled 0x0000000000000000: PHYBASE3 0x0000000000000000: PHYMASK3: Disabled 0x0000000000000000: PHYBASE4 0x0000000000000000: PHYMASK4: Disabled 0x0000000000000000: PHYBASE5 0x0000000000000000: PHYMASK5: Disabled 0x0000000000000000: PHYBASE6 0x0000000000000000: PHYMASK6: Disabled 0x0000000000000000: PHYBASE7 0x0000000000000000: PHYMASK7: Disabled 0x0000000000000000: PHYBASE8 0x0000000000000000: PHYMASK8: Disabled 0x0000000000000000: PHYBASE9 0x0000000000000000: PHYMASK9: Disabled Architectural UPD values for MemoryInit at: 0xfef0fce0 0x01: Revision 0x00000000: NvsBufferPtr 0xfefb0000 --> 0xfef60100: StackBase 0x0004ff00: StackSize 0x00000000 --> 0x00002000: BootLoaderTolumSize 0x00000000: BootMode UPD values for MemoryInit: 0x02: PcdSmmTsegSize 0x00: PcdFspDebugPrintErrorLevel 0xa0: PcdSpdSmbusAddress_0_0 0xa2: PcdSpdSmbusAddress_0_1 0xa4: PcdSpdSmbusAddress_1_0 0xa6: PcdSpdSmbusAddress_1_1 0x00: PcdMrcRmtSupport 0x0c: PcdMrcRmtCpgcExpLoopCntValue 0x06: PcdMrcRmtCpgcNumBursts 0x00: PcdMemoryPreservation 0x01: PcdFastBoot 0x01: PcdEccSupport 0x00: PcdHsuartDevice 0x00 --> 0x01: PcdMemoryDown 0x01: PcdEnableSATA0 0x01: PcdEnableSATA1 0x01: PcdEnableIQAT 0x00: PcdSmbusSpdWriteDisable 0x00: PcdEnableMeShutdown 0x01: PcdEnableXhci 0x06: PcdDdrFreq 0x00: PcdMmioSize 0x01: PcdMeHeciCommunication 0x14: PcdHsioLanesNumber 0x00000000: PcdFiaMuxConfigPtr 0x00: PcdHalfWidthEnable 0x01: PcdTclIdle 0x03: PcdInterleaveMode 0x00: PcdMemoryThermalThrottling 0x00: PcdSkipMemoryTest 0x08: PcdUsb2Port1Pin 0x08: PcdUsb2Port2Pin 0x08: PcdUsb2Port3Pin 0x08: PcdUsb2Port4Pin 0x08: PcdUsb3Port1Pin 0x08: PcdUsb3Port2Pin 0x08: PcdUsb3Port3Pin 0x08: PcdUsb3Port4Pin 0x00: PcdIOxAPIC0_199 0x00: PcdDmapX16 0xfef0fcc0: 44 4e 56 55 50 44 5f 4d 01 00 00 00 00 00 00 00 DNVUPD_M........ 0xfef0fcd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0xfef0fce0: 01 00 00 00 00 00 00 00 00 01 f6 fe 00 ff 04 00 ................ 0xfef0fcf0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 . .............. 0xfef0fd00: 02 00 a0 a2 a4 a6 00 0c 06 00 01 01 00 01 00 10 ................ 0xfef0fd10: f1 fe 01 01 01 00 00 01 06 00 01 14 00 00 00 00 ................ 0xfef0fd20: 76 65 72 73 69 6f 6e 20 78 78 78 00 00 00 00 00 version xxx..... 0xfef0fd30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0xfef0fd40: 00 01 03 00 00 00 00 00 00 08 08 08 08 08 08 08 ................ 0xfef0fd50: 08 00 00 01 01 00 00 00 00 00 00 00 00 00 00 00 ................ 0xfef0fd60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... 0xfef0feb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa 55 ...............U Calling FspMemoryInit: 0xfff32450 0xfef0fcc0: raminit_upd 0xfef10f6c: &hob_list_ptr Timestamp - calling FspMemoryInit: 4524096604 Any help on this is highly appreciated . Thanks Somanna Ankaiah

2 3

RFC: Deprecating VBOOT_VBNV_CMOS
by Yu-Ping Wu 15 Aug '22

15 Aug '22

Hi, There's an ongoing effort to expand vboot nvdata (nvstorage) from 16 to 64 bytes [issue <https://issuetracker.google.com/issues/172342278>]. To reduce unnecessary complexity of our firmware code accessing nvdata, we'd like to drop 16-byte nvdata support from the firmware codebase (crossystem still needs to support both though). One obstacle is the CMOS nvdata backend (VBOOT_VBNV_CMOS). We're not sure if there would be enough CMOS space for all boards using that. In addition, because CMOS loses state when the battery is removed, newer boards usually select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH to backup nvdata to flash. Considering that, this seems like a good opportunity to migrate CMOS to flash nvdata [issue <https://issuetracker.google.com/issues/235293589>]. One problem we faced is that many old platforms such as broadwell don't support writing to the flash in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES). Therefore it looks like we'd need to drop vboot support on them (for example CB:65782 <https://review.coreboot.org/c/coreboot/+/65782>). An alternative would be to keep the CMOS backend around as "deprecated" and not allow 64-byte nvdata for it, but that would at best be a transitory solution for a couple of years, not forever. If there's any concern, please let me know. We have firmware branches for ChromeOS devices, so modifying ToT code wouldn't affect old devices in any way. However, I'm not sure how non-ChromeOS boards (such as mainboard/lenovo/haswell) would be affected by this. Please cc more people if needed. -- Yu-Ping Wu | Software Engineer | yupingso(a)google.com | +886 937 057 080

2 4

Heads up: Allocator changes
by Nico Huber 10 Aug '22

10 Aug '22

Hi coreboot fellows, after two years with the new resource allocator it's time again for some changes[1]. Much less invasive than last time, but again there will be changes in the pattern where resources are placed. So once more this may uncover bugs in case fixed resources are not reserved properly. Reasons for the changes are somewhat the same as always: we haven't finished the support for 64-bit resources. Currently one has to opt in for a placement above 4G with a resource flag, and even this has its limitations. For instance, reserved space for hot-pluggable de- vices can be placed above 4G with a Kconfig setting, but there's no rule what should happen with the resources of cold-plugged devices. In the worst case, allocation for those can fail. Another reason are approaching changes to support multiple PCI host bridges and multiple resource windows per domain. I digress... So everybody is invited to test the patch train. There is a new Kconfig option RESOURCE_ALLOCATION_TOP_DOWN. The default y should work fine, though in case of regressions it would be nice to have it tested with both settings. Cheers, Nico [1] https://review.coreboot.org/q/topic:allocator+status:open

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coreboot July 2022