June 2019 - coreboot - mail.coreboot.org

by Vinzenz Vietzke

Hi, maybe some of you have already seen it in common Linux online media. We are currently looking for Coreboot developers. You should bring along: - Knowledge of C and C++ - Already experience with the development of kernel modules - Enjoy testing new hardware - Experience in driver development - Knowledge of LVFS and fwupd advantageous - Ideally already busy with Coreboot, EFI or similar. More about this also at: https://www.tuxedocomputers.com/en/Infos/Jobs/Software-Developers-for-Cor... So if someone is interested or knows someone here, please contact us! If you have any questions, please contact me directly! -- Mit freundlichen Grüßen / Kind regards Vinzenz Vietzke Produktmanagement -- TUXEDO Computers GmbH Zeppelinstr. 3 ~ D-86343 Königsbrunn -- Tel: +49 (0) 8231 / 99 19 000 Fax: +49 (0) 8231 / 99 19 009 E-Mail: vv(a)tuxedocomputers.com -- www.TuxedoComputers.com ~ www.Linux-Onlineshop.de -- Amtsgericht Augsburg: HRB 27755 ~ USt-IdNr.: DE815420876 Geschäftsführer: Herbert Feiler

4 days, 12 hours

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ASUS KCMA-D8 RAM issues

by up6IfzRzvQCyv9AK4XvYirxDa8

Hello, I bought the motherboard ASUS KCMA-D8 to set up a coreboot + Qubes OS workstation. However, I don't find a combination of coreboot + CPU + RAM that works. I have also tried the latest libreboot and it works in most cases, but does not provide microcode updates. For test purposes I tried 41xx/42xx/43xx Opterons. The error message I get in most cases on the serial null-modem port is: DIMM training FAILED! Restarting system...soft_reset() called! I following RAM modules has been used: - M391B1G73BH0-CK0 (8GB PC3L-12800 UDIMM ECC) // NOK - NT8GC72B4NB1NK-CG (8GB PC3PC3-10600 RDIMM ECC) //NOK - HMT325U7BFR8A (2GB PC3-10600 UDIMM ECC ) //OK, see https://www.raptorengineering.com/coreboot/kcma-d8-status.php There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180. Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I tried many combinations of RAM modules + CPU + coreboot versions (4.6, 4.7, 4.8, 4.9) but get the above "DIMM training FAILED..." error message in most cases. Any ideas or recommendations for RAM modules that are supported so that a workstation with 32GB or better 64GB can be built? Or why libreboot works and coreboot doesn't? Thank you. 4225 / #005.log (1x NT8GC72B4NB1NK-CG) // NOK ====================================== coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting... .. .. AutoCycTiming_D: Start mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected mct_MaxLoadFreq: More than 1 registered DIMM on 1500mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done activate_spd_rom() for node 00 enable_spd_node0() DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 24000 TrainDQSReceiverEnCyc: ErrStatus 24000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done DQSTiming_D: Restarting training on algorithm request SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0004 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2205 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done activate_spd_rom() for node 00 enable_spd_node0() DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSReceiverEnCyc_D_Fam15: lane 0 failed to train! Training for receiver 2 on DCT 0 aborted TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 44000 TrainDQSReceiverEnCyc: ErrStatus 44000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done DIMM training FAILED! Restarting system...soft_reset() called! 4180 #002.log (1x NT8GC72B4NB1NK-CG) // OK ==================================== coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting... .. .. AutoCycTiming_D: Start mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected mct_MaxLoadFreq: 1 registered DIMM on 1500mV channel; limiting to DDR3-1333 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00090092 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 000000a0 AutoConfig_D: DramConfigLo: 00082100 AutoConfig_D: DramConfigHi: 0f48000b mct_SetDramConfigHi_D: Start mct_SetDramConfigHi_D: DramConfigHi: 1f48010b mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done InitPhyCompensation: DCT 0: Start InitPhyCompensation: DCT 0: Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:2400000 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done activate_spd_rom() for node 00 enable_spd_node0() activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start ChangeMemClk: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 2205 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 2205 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 2205 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECC enabled on node: 00 DCTMemClr_Sync_D: Start DCTMemClr_Sync_D: Waiting for memory clear to complete..............

6 days, 22 hours

6
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Does NSA contribute to Coreboot?

by Anac

Dear all, Is it true that there's code provided by the NSA implemented in Coreboot? https://www.tomshardware.com/news/nsa-contributes-low-level-stm-coreboot,... Any thoughts? Cheers

3 weeks, 1 day

10
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Re: Debugging AGESA black box

by Jorge Fernandez Monteagudo

Hi all, I've been able to implement the 'AGESA_HOOKBEFORE_DRAM_INIT' to try to see what AGESA blob is doing and it's call 10 time before resetting the board. Any with AGESA experience could confirm this is a normal behavior? Anybody knows if there are any board using the IDS (Integrated Debug Services) of the AGESA? I would like to activate it to try to get more info about what's going on... Regards, Jorge ________________________________ De: Jorge Fernandez Monteagudo <jorgefm(a)cirsa.com> Enviado: martes, 25 de junio de 2019 8:42:57 Para: coreboot(a)coreboot.org Asunto: [coreboot] Debugging AGESA black box Hi all, I'm trying to use coreboot on a custom board based on the stoneyridge AMD SOC. I'm reusing the mainboard/amd/gardenia code. We have serial console and I've been able to trace down to 'AmdInitPost(PostParams);' called from 'src/soc/amd/common/block/pi/agesawrapper.c' to the responsible to make the board reset. Maybe we have some hardware problem related to the DIMM area. Then, there is some way to get some callback, trace, etc from the AGESA blackbox code? Any chance to use the Integrated Debug Services (IDS)? Any recommendation to solve this? Thanks!

3 weeks, 1 day

1
0
0 / 0

compiler/toolchain issue?

by mturney＠codeaurora.org

A quick look on the mailing list doesn't show this issue for anybody else so I have to assume something with my setup. For past year + I have been working with coreboot in Chromium chroot environment. Yesterday I had to go back to the standalone build environment. This is happening from tip of upstream master. It is consistent with i386, arm and aarch64 toolchain. This output is following Lesson 1 so it is from i386 with QEMU configuration. Using git blame, all of the code (cbfstool & commonlib headers) was last modified 2015 and 2017, so figure it is toolchain and/or my host, which is Ubuntu 16.04. I will add that there is an issue with chrome-ec repo access, but doubt that is contributory to this build error, but here are the messages from chrome-ec first: Cloning into '3rdparty/chromeec'... X11 forwarding request failed on channel 0 fatal: Project not found: coreboot/chrome-ec fatal: Could not read from remote repository. Please make sure you have the correct access rights and the repository exists. Clone of 'ssh://review-android.quicinc.com:29418/coreboot/chrome-ec.git' into submodule path '3rdparty/chromeec' failed And here is tail-end of coreboot build that fails: CC postcar/southbridge/intel/common/reset.o CC postcar/southbridge/intel/common/rtc.o LINK cbfs/fallback/postcar.debug IASL build/dsdt.aml Intel ACPI Component Architecture ASL+ Optimizing Compiler/Disassembler version 20190509 Copyright (c) 2000 - 2019 Intel Corporation coreboot toolchain vc15e600 2019-05-10 ASL Input: dsdt.asl - 15113 bytes 245 keywords 399 source lines AML Output: dsdt.aml - 4021 bytes 99 opcodes 146 named objects Compilation successful. 0 Errors, 0 Warnings, 0 Remarks, 234 Optimizations IASL build/dsdt.aml disassembled correctly. HOSTCC cbfstool/cbfstool.o In file included from <command-line>:0:0: /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c: In function 'cbfs_add_component': /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/compiler.h:59:2: error: first argument to '__builtin_choose_expr' not a constant __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:39:2: note: in expansion of macro '__TYPEOF_UNLESS_CONST' __TYPEOF_UNLESS_CONST(a, b) var_a = (a); \ ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:49:26: note: in expansion of macro '__CMP_SAFE' __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:546:19: note: in expansion of macro 'MAX' uint32_t size = MAX(hs, param.padding); ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/compiler.h:59:2: error: first argument to '__builtin_choose_expr' not a constant __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:40:2: note: in expansion of macro '__TYPEOF_UNLESS_CONST' __TYPEOF_UNLESS_CONST(b, a) var_b = (b); \ ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:49:26: note: in expansion of macro '__CMP_SAFE' __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:546:19: note: in expansion of macro 'MAX' uint32_t size = MAX(hs, param.padding); ^ In file included from /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/common.h:25:0, from /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:26: /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:47:25: error: first argument to '__builtin_choose_expr' not a constant #define __CMP(a, b, op) __builtin_choose_expr( \ ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:546:19: note: in expansion of macro 'MAX' uint32_t size = MAX(hs, param.padding); ^ In file included from <command-line>:0:0: /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c: In function 'cbfs_create': /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/compiler.h:59:2: error: first argument to '__builtin_choose_expr' not a constant __builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr)) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:39:2: note: in expansion of macro '__TYPEOF_UNLESS_CONST' __TYPEOF_UNLESS_CONST(a, b) var_a = (a); \ ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:49:26: note: in expansion of macro '__CMP_SAFE' __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:957:6: note: in expansion of macro 'MAX' MAX(bootblock.size, sizeof(int32_t)); ^ In file included from /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/common.h:25:0, from /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:26: /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:47:25: error: first argument to '__builtin_choose_expr' not a constant #define __CMP(a, b, op) __builtin_choose_expr( \ ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/src/commonlib/include/commonlib/helpers.h:56:19: note: in expansion of macro '__CMP' #define MAX(a, b) __CMP(a, b, >) ^ /local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot/util/cbfstool/cbfstool.c:957:6: note: in expansion of macro 'MAX' MAX(bootblock.size, sizeof(int32_t)); ^ make: *** [build/util/cbfstool/cbfstool.o] Error 1 mturney@mturney-linux:/local/mnt/workspace/mturney/gitrepos/qualcomm/chromebook/cbdc-meta/standalone/coreboot$

3 weeks, 1 day

5
5
0 / 0

More coding style change proposals

by Patrick Georgi

Hey everybody, in today's leadership meeting, the question was brought up if we want to normalize the coding style in coreboot to _always_ use braces in if, else and for statements, even if it's just one statement they're wrapping. The arguments made in favor were: 1. it's more consistent 2. it's safer: you won't accidentally add a statement that is outside the context it's supposed to run in (or even move a statement out into the parent context by inserting another statement) So instead of: if (foo) bar(); else { baz(); quux(); } we'd do: if (foo) { bar(); } else { baz(); quux(); } The attendees were generally in favor, but wanted to ask the wider community. The idea of putting it up for a vote was brought up, but we decided to discuss it first (and vote if there's disagreement, after the arguments were exchanged. makes for clearer arguments for all positions on the ballot, too) Patrick

3 weeks, 2 days

9
17
0 / 0

New on blogs.coreboot.org: [GSoC] Ghidra firmware utilities, week 5

by blogs.coreboot.org

3 weeks, 3 days

1
0
0 / 0

Debugging AGESA black box

by Jorge Fernandez Monteagudo

Hi all, I'm trying to use coreboot on a custom board based on the stoneyridge AMD SOC. I'm reusing the mainboard/amd/gardenia code. We have serial console and I've been able to trace down to 'AmdInitPost(PostParams);' called from 'src/soc/amd/common/block/pi/agesawrapper.c' to the responsible to make the board reset. Maybe we have some hardware problem related to the DIMM area. Then, there is some way to get some callback, trace, etc from the AGESA blackbox code? Any chance to use the Integrated Debug Services (IDS)? Any recommendation to solve this? Thanks!

3 weeks, 3 days

1
0
0 / 0

New on blogs.coreboot.org: [GSoC] Debug Bootblock Stage for ARMv8 on QEMU

by blogs.coreboot.org

3 weeks, 4 days

1
0
0 / 0

Re: AM1I-A and other 16h Jaguar boards cant have a working IOMMU

by Sirsquishy

This has been an issue since before AM2+, but AM2+ is when I first started to deal with it. For AMD IOMMU does not fully work behind the DMI. If you break out IOMMU from the CPU lanes You can generally get it working anyway you want. But if you try and break out DMI attached devices (PCIE, Onboard, other) the Groups are generally broken and do not work. Have tried this with many HyperVisors and some will just give up the ghost after a while due to sharing violations. So this is not exactly new and I wouldnt expect a proper fix.

4 weeks

2
1
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coreboot June 2019