Lenovo T410 Coreboot
by A. Veek
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Hash: SHA256
Hi @ all,
is there a Coroboot for the Lenovo T410 Laptop?
Greetings
Alex Veek
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1 month
Re: [coreboot] On Intel Boot Guard
by Alexander Couzens
Hi Iru,
we aren't still sure which boards use Intel Boot Guard and which doesn't use it. But we expect most board use it,
because it's "recommended" by intel - as we dont recommend it.
Also there isn't yet a test script for Intel Boot Guard.
Can you post a link to that forum post?
I would like to look into a x240 flash image. If you have such board it would be nice
if you can send me a copy of the flash image via private mail.
Cheers,
lynxis
--
Alexander Couzens
mail: lynxis(a)fe80.eu
jabber: lynxis(a)jabber.ccc.de
mobile: +4915123277221
2 years, 9 months
coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)
by Timothy Pearson
All,
I have successfully ported coreboot to the relatively modern ASUS
KGPE-D16 server board (dual AMD socket G34, 16 DDR3 DIMMs,
https://www.asus.com/us/Commercial_Servers_Workstations/KGPED16/)! This
port uses native Family 10h initialization (_not_ AGESA or CIMX).
The Libreboot folks will be interested to know that this board can run
blob-free and still retain full functionality!
Port specifications:
CPU: Dual AMD G34 Magny-Cours (Family 10h)
RAM: 16 DDR3 DIMM slots with ECC support (tested with x4 4G DDR3-1333
unbuffered DIMMs)
Peripherals:
PCIe slots: all functional
PCI slot: functional
RS-232: functional
PS/2: expected to function, not tested (on SuperIO)
ASpeed VGA device: functional (text mode, see below)
IEEE1394: functional
On-board USB: functional
On-board NICs: functional
ASUS PIKE SAS controller: functional
PCIe ROMs: functional
Power management:
DDR3 voltage set: functional
ACPI/APIC: functional
Suspend/resume: broken
Other:
cbmem console: partial support (log truncated)
cbmem timestamps: functional
nvram: functional
BIOS recovery jumper: functional
ASpeed VGA:
The ASpeed VGA device initialises in text mode via its (new) coreboot
driver, however this initialisation is incomplete, leading to distorted
but quite usable VGA output. When Linux boots and engages the graphical
framebuffer all distortion disappears.
This port was not trivial. Almost every device used was broken and
required debugging/repair, with the notable exception of the SuperIO
chip. The AMD DDR3 controller was severely broken to the point where
large rewrites were needed in order to bring it in line with the BKDG.
Even after the various component drivers were repaired
Due to the labor-intensive nature of the port and the extensive changes
throughout the entire source tree, it is not economically feasible to
merge this port upstream at this time (I estimate upward of 30
independent patches would be required just to get the board booting!).
Raptor Engineering will, however, be continuing to maintain this port
internally, and I am currently looking into adding native Family 15h
support on top of this internal tree. Additionally, while it was not a
priority for the initial port, I will be attempting to enable
suspend/resume functionality as I have time.
If there is sufficient interest from the community in adding this board
to coreboot I would consider merging the changes in exchange for a
one-time contract payment in the vicinity of $35,000 USD. When
considering this offer please bear in mind that this is a fully
functional blobless board with a wide range of peripherals and expansion
options available, and that once these large changes are merged I will
continue to enhance coreboot functionality as before (e.g. with the
KFSN4-DRE and the T400). I would also be willing to add this board to
the test stand as the only fully supported 4-way Opteron board (socket
G34 Magny-Cours CPUs contain two separate CPUs in one package, making
this 2-socket board a 4-way system from a HyperTransport perspective).
Please let me know if you have any questions!
--
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645
http://www.raptorengineeringinc.com
3 years, 3 months
[Mohon Peak] Memtest86+
by Patrick Agrain
Hello,
I try to perform some memory test on the Mohon Peak CRB with memtest86+.
I downloaded memtest86+ v5.01 and compile it. So far, so good.
Following the thread:
http://www.coreboot.org/pipermail/coreboot/2015-January/079143.html
concerning this topic, I modified the given values, so that now:
[root@localhost memtest86+-5.01]# readelf -e memtest1modified
ELF Header:
Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, little endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: EXEC (Executable file)
Machine: Intel 80386
Version: 0x1
Entry point address: 0x10000
Start of program headers: 52 (bytes into file)
Start of section headers: 151580 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 1
Size of section headers: 40 (bytes)
Number of section headers: 3
Section header string table index: 2
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk
Inf Al
[ 0] NULL 00000000 000000 000000 00
0 0 0
[ 1] .data PROGBITS 00010000 001000 024008 00 WA
0 0 1
[ 2] .shstrtab STRTAB 00000000 025008 000011 00
0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings)
I (info), L (link order), G (group), x (unknown)
O (extra OS processing required) o (OS specific), p (processor specific)
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x010000 0x00010000 0x00010000 0x24008 0x24008 RW
0x200000
Section to Segment mapping:
Segment Sections...
00 .shstrtab
[root@localhost memtest86+-5.01]#
What gives the same scheme as in the previously mentionned thread.
Now the logs of the booting Mohon Peak (from begin of Seabios):
SeaBIOS (version
rel-1.8.0-12-ga1ac886-dirty-20150402_003540-localhost.localdomain)
init usb
EHCI init on dev 00:16.0 (regs=0xdfe89420)
set_address 0x7fd41b80
config_usb: 0x7fd41a50
device rev=0200 cls=09 sub=00 proto=01 size=64
init serial
Found 2 legacy serial ports
init hard drives
init ahci
AHCI controller at 17.0, iobase dfe88000, irq 15
AHCI: cap 0xc720ff03, ports_impl 0x0
AHCI controller at 18.0, iobase dfe88800, irq 0
AHCI: cap 0xc3309f01, ports_impl 0x1
AHCI/0: probing
AHCI/0: link up
AHCI/0: ... finished, status 0x51, ERROR 0x4
Searching bootorder for: /pci@i0cf8/*@18/drive@0/disk@0
AHCI/0: registering: "AHCI/0: ST500DM002-1BD142 ATA-8 Hard-Disk (465
GiBytes)"
Registering bootable: AHCI/0: ST500DM002-1BD142 ATA-8 Hard-Disk (465
GiBytes) (type:2 prio:103 data:f3ef0)
Searching bootorder for: /rom@img/Memtest86+
Registering bootable: Payload [Memtest86+] (type:32 prio:9999 data:ffe23240)
Scan for option roms
Attempting to init PCI bdf 00:00.0 (vd 8086:1f08)
Attempting to init PCI bdf 00:01.0 (vd 8086:1f10)
Attempting to init PCI bdf 00:03.0 (vd 8086:1f12)
Attempting to init PCI bdf 00:0e.0 (vd 8086:1f14)
Attempting to init PCI bdf 00:0f.0 (vd 8086:1f16)
Attempting to init PCI bdf 00:13.0 (vd 8086:1f15)
Attempting to init PCI bdf 00:14.0 (vd 8086:1f41)
Attempting to init PCI bdf 00:14.1 (vd 8086:1f41)
Attempting to init PCI bdf 00:16.0 (vd 8086:1f2c)
Attempting to init PCI bdf 00:17.0 (vd 8086:1f22)
Attempting to init PCI bdf 00:18.0 (vd 8086:1f32)
Attempting to init PCI bdf 00:1f.0 (vd 8086:1f38)
Attempting to init PCI bdf 00:1f.3 (vd 8086:1f3c)
Attempting to init PCI bdf 01:00.0 (vd 1415:c158)
Attempting to init PCI bdf 02:00.0 (vd 10b5:8624)
Attempting to init PCI bdf 03:04.0 (vd 10b5:8624)
Attempting to init PCI bdf 03:05.0 (vd 10b5:8624)
Attempting to init PCI bdf 03:08.0 (vd 10b5:8624)
Attempting to init PCI bdf 05:00.0 (vd 8086:1528)
Attempting to init PCI bdf 05:00.1 (vd 8086:1528)
Press ESC for boot menu.
Select boot device:
1. AHCI/0: ST500DM002-1BD142 ATA-8 Hard-Disk (465 GiBytes)
2. Payload [Memtest86+]
Searching bootorder for: HALT
Mapping hd drive 0x000f3ef0 to 0
drive 0x000f3ef0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
s=976773168
finalize PMM
malloc finalize
Space available for UMB: c1000-ee800, f0000-f3ef0
Returned 258048 bytes of ZoneHigh
e820 map has 8 items:
0: 0000000000000000 - 000000000009f800 = 1 RAM
1: 000000000009f800 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000007fd89000 = 1 RAM
4: 000000007fd89000 - 000000007fe00000 = 2 RESERVED
5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED
6: 00000000fee00000 - 00000000fee01000 = 2 RESERVED
7: 0000000100000000 - 0000000180000000 = 1 RAM
Jump to int19
enter handle_19:
NULL
Booting from CBFS...
Run img/Memtest86+
Segment 464c457f 16777216@0xffe23268 -> 256@0x02000300
No support for compression type 10101
enter handle_18:
NULL
Booting from 0000:7c00
GRUB Loading stage2. Output on the SERIAL line..
enter handle_12:
a=00000000 b=00000000 c=00000000 d=00000080 ds=0000 es=0000 ss=0000
si=0000811e di=00028da8 bp=00001ff0 sp=00001ff4 cs=0000 ip=8a82 f=0297
no switch back.
GRUB version 0.5.96 (638K lower / 2093604K upper memory)
+-------------------------------------------------------------------------+
| Boot GNU/Linux
[ll-ttyS1-115K2] |
| Boot GNU/Linux
[xx-ttyS1-115K2] |
| Boot GNU/Linux
[xx-ttyS1-115K2] |
| Boot GNU/Linux
[default] |
| Install GRUB into the hard
disk |
| |
| |
| |
| |
| |
| |
| |
+-------------------------------------------------------------------------+
Use the ^ and v keys to select which entry is highlighted.
Press enter to boot the selected OS, 'e' to edit the
commands before booting, or 'c' for a command-line.
After pressing 'ESC' and select '2', I'm not able to boot memtest86+,
and fall back to the hard drive.
Has anyone already faced this behavior.
Thanks in advance.
Best regards,
Patrick Agrain
3 years, 5 months
Re: [coreboot] Fwd: Coreboot T-shirts
by Vladimir 'φ-coder/phcoder' Serbinenko
Good news: now it's possible to have them in black as well.
I received up to now only one request to which I replied by personal
mail. If you didn't receive any reply, please resend your request.
Please specify in request the size, color (white, black, few other
colors if someone is interested), quantity and if you want it single or
double-sided printing.
Please tell me until Friday.
@Carl-Daniel: Still waiting for that PDF.
On 21.05.2015 15:41, Vladimir 'phcoder' Serbinenko wrote:
> Apparently original mail didn't make it to the list. Resent
>
>
> ---------- Forwarded message ----------
> From: Vladimir 'phcoder' Serbinenko <phcoder(a)gmail.com>
> Date: Thu, May 21, 2015 at 2:29 PM
> Subject: Re: [coreboot] Coreboot T-shirts
> To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
> Cc: coreboot <coreboot(a)coreboot.org>
>
>
>
> Le 21 mai 2015 13:01, "Carl-Daniel Hailfinger"
> <c-d.hailfinger.devel.2006(a)gmx.net> a écrit :
>>
>> On 21.05.2015 12:51, Vladimir 'phcoder' Serbinenko wrote:
>>> A contact of mine proposes to print coreboot T-shirts for the community.
>>> Black printing on white T-shirt. Expected price is 30€-35€ + shipping from
>>> CH or DE, double-sided printing, one-sided is 5-8€ less. It will be printed
>>> in Russia.
>>
>> Please note that the coreboot T-Shirt I am wearing is black, with the
>> logo being a white plastic foil melted/glued to the t-shirt.
>> Could you ask your contact whether such a variant would be possible as
>> well? The foil variant is extremely durable and IMHO a black T-Shirt
>> fits a bit better with all the other hacker culture T-Shirts.
>>
> I already did. Unfortunately it's not possible at this point
>>> I need to know who wants one and sizes by June 5th. For payment
>>> I accept paypal and bank wiring.
>>> It will be available in ~August. Do we have some kind of dev meeting in
>>> autumn where I could bring them?
>>> @carldani: could you give me the file used for printing?
>>
>> Sure.
>>
>> Regards,
>> Carl-Daniel
>
>
3 years, 7 months
coreboot community chat
by Stefan Reinauer
Hi coreboot community!
In order to have more face time and a more personal connection with each
other than it is possible on the coreboot IRC channel, I would like to
invite you to participate in a monthly video conference to discuss the
up and coming projects, ideas and issues that all of us are involved in.
We suggest to have these meetings via Google Hangouts, as we have
figured out in the past that other alternatives like Mumble didn’t work
as well for us.
So I would like to invite interested contributors of the community to
join us. The first video conference will be on Thursday, May 21th at
9:15am Pacific Time (16:15 UTC). The meeting can be joined by clicking
on this link: http://goo.gl/SD6t3G. If, for some reason you can not
access Hangouts, we can try and call you (no promises). Please let me
know ahead of time if you need assistance!
The agenda for the first meeting is available here: http://goo.gl/7E0zYz
Looking forward to seeing y’all!
Stefan
3 years, 7 months
Re: [coreboot] SPD CRC failed
by Michael Gerlach
Okay here we go...
I memtested the modules again and as expected no defect was found. So i
retried latest master today and quite unusually it just boots up.
It does not reach payload-state still, but ram and frequency is detected
correctly. Fan is turning on and backlight gets activated but no output
is displayed. Besides it seems to die at unpredictable states. I
attached 3 different boot logs..
The only assumption could be a defect in some piece of hardware, but i
do not had any trouble with this x230 yet..
On the other hand _this_ build was compiled on the x230 itself, while
the other builds were compiled on a x201 with an identical bootstrapped
toolchain..
Any idea what possibly cause a similar behavior too?
Best regards,
n3ph
On 05/20/15 23:45, David Hendricks wrote:
>
>
> On Wed, May 20, 2015 at 1:13 PM, Michael Gerlach <n3ph(a)terminal21.de
> <mailto:n3ph@terminal21.de>> wrote:
>
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> I forgot to mention that somehow the ram frequency is not detected
> correctly...
>
> PLL busy...done
> PLL didn't lock. Retrying at lower frequency
> PLL busy...done
> PLL didn't lock. Retrying at lower frequency
> PLL busy...done
> PLL didn't lock. Retrying at lower frequency
> PLL busy...done
> PLL didn't lock. Retrying at lower frequency
> No lock frequency found
>
>
> The SPD data should be read via SMBus long before PLL locking for the
> DRAM itself takes place.
>
> If you're unable to successfully read the SPDs, then it makes sense that
> later init would fail.
>
> --
> David Hendricks (dhendrix)
> Systems Software Engineer, Google Inc.
--
Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard
3 years, 7 months
Re: [coreboot] Cbfstool compilation error with gcc 5.1
by ron minnich
who knows, but we do things to keep gcc happy anyway.
just set phdr to null in the declaration.
ron
On Sat, May 30, 2015 at 11:50 PM Anatol Pomozov <anatol.pomozov(a)gmail.com>
wrote:
> Hi
>
> I am trying to compile coreboot cbfstool on Arch where gcc 5.1 is used.
> And I see following compilation error. I wonder if it is coreboot or gcc
> issue.
>
> ==> Starting build()...
> make: Entering directory
> '/home/anatol/sources/archpackages/coreboot-utils-git/src/coreboot/util/cbfstool'
> mkdir -p ./
> cc -D_FORTIFY_SOURCE=2 -D_DEFAULT_SOURCE -D_POSIX_C_SOURCE=200809L
> -Iflashmap -march=x86-64 -mtune=generic -O2 -pipe -fstack-protector-strong
> --param=ssp-buffer-size=4 -g3 -std=c99 -Werror -Wall -Wextra -Wcast-qual
> -Wmissing-prototypes -Wredundant-decls -Wshadow -Wstrict-prototypes
> -Wwrite-strings -c -o rmodule.o rmodule.c
> rmodule.c: In function ‘rmodule_create’:
> rmodule.c:286:29: error: ‘phdr’ may be used uninitialized in this function
> [-Werror=maybe-uninitialized]
> (phdr->p_vaddr + phdr->p_memsz))) {
> ^
> rmodule.c:203:14: note: ‘phdr’ was declared here
> Elf64_Phdr *phdr;
> ^
> cc1: all warnings being treated as errors
> Makefile:55: recipe for target 'rmodule.o' failed
> make: *** [rmodule.o] Error 1
> make: Leaving directory
> '/home/anatol/sources/archpackages/coreboot-utils-git/src/coreboot/util/cbfstool'
> ==> ERROR: A failure occurred in build().
> --
> coreboot mailing list: coreboot(a)coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
3 years, 7 months
