May 2015 - coreboot - mail.coreboot.org

by Zaolin

Hi, do the following: 0) Get the PCI ID via lspci -vnn of the Intel Graphics Device. 1) Get the UEFITool https://github.com/LongSoft/UEFITool 2) Extract with the flashrom ich_descriptor_tool your UEFI Firmware (BIOS). -> ich_descriptor_tool -f bios.bin -d 3) Open the UEFI Image with the UEFITool go under search -> text and disable UTF-8 support. 4) Enter for intel graphic devices "VGA Compatible BIOS" and you will find one more matching entries by scrolling down the log. For Nvidia use "VGA Compatible". 5) Extract all entries with "Extract body". Correct Oproms should have for Intel around 65k size. If it's only one entry then you can stop here and use it as vgabios. 6) Get rom-parser https://github.com/awilliam/rom-parser and run it on the files. You will get printed some infos including the pci id. If the id matches with your graphics device use the it as vgabios. Regards Zaolin > Dear Michael, > > > Am Samstag, den 23.05.2015, 04:28 +0200 schrieb Michael Gerlach: > > > Uhm - I do not explicitly compressed it. I just added it to config.. > > > > Extracted it via > > > > echo 1 > /sys/devices/pci0000\:00/0000\:00\:02.0/rom > > cp /sys/devices/pci0000\:00/0000\:00\:02.0/rom vgabios.bin > > > > How to check if it's compressed? > > The *file` command should help you. > > For my AMD Video BIOS from the ASRock E350M1 I get the following. > > $ file vgabios.bin > vgabios.rom: BIOS (ia32) ROM Ext. IBM comp. Video (113*512) > > If the method you used, did not work, please report a bug to the Intel > graphics folks [1]. > > > Thanks, > > Paul > > > [1] https://01.org/linuxgraphics/documentation/how-report-bugs > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] x230 - vgabios

by Michael Gerlach

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 > Extracted it via > > echo 1 > /sys/devices/pci0000\:00/0000\:00\:02.0/rom cp > /sys/devices/pci0000\:00/0000\:00\:02.0/rom vgabios.bin > >> That's your problem. ROM needs to be extracted, not dumped. You >> can workaround immediate problem by disabling checksum in SeaBIOS >> but dumped oprom for intel is not fully functional, i.a. LCD >> stays black with windows. I already experienced buffer artifacts and wrong colors - quite unusable .. As written in docs[1] i assumed this should work this way.. :-/ What is the difference between dumped and extracted vbios? What is the correct way to extract a fully working oprom? Via bios-extract i just get: Using file "bios-dump.rom" (4096kB) Error: Unable to detect BIOS Image type. [1] http://www.coreboot.org/VGA_support#Retrieval_via_Linux_kernel Best regards, n3ph - -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBAgAGBQJVYHclAAoJEE1l5S41evqaamAH/RcxHLhsQOhcKNjp8Yn6vWoJ 2dVXbVk8PPF3LdtjGjkVgXEuslB2wH984BQ09/Lm5FUhHN4k1jfJQlDauQxAVWWr AbEK08tBy+60UiKYFfQzkF6CuqSqhjF+gw0MfTqCZLLAscKGq7R+FoO/HIeRJRZI S1QBSlQPvrJDJRTI58mmgah6ggYDFlxyGDz6ww7DgjWXxL56fjyNSzpyygPcKUNr hYgpaeVSAGZAX4mJKd3n/HlYLKq0e5V8pt22xpUeEuwM07SCqGvbX0yxYi0tgTmW NJ1k1o2mWf/z8MBHJo1ltORh5lLFn9ZFJDeCJ1iK+68lTD6SiYiG20Mi+ib4PbQ= =BK2J -----END PGP SIGNATURE-----

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x230 - vgabios

by Michael Gerlach

Greetings, i am trying to get coreboot running on x230 and have some trouble regarding the execution of the vga option rom. As far as i understand seabios should load all option roms existing in cbfs, but it won't. Only if i set CONFIG_VGA_ROM_RUN=y vga option rom gets loaded but whether coreboot nor seabios output is displayed. Only a blinking cursor idles until boot continues. coreboot.rom: 12288 kB, bootblocksize 1936, romsize 12582912, offset 0xb00000 alignment: 64 bytes, architecture: x86 Name Offset Type Size cmos.default 0xb00000 cmos_default 256 cmos_layout.bin 0xb00140 cmos_layout 1984 pci8086,0166.rom 0xb00940 optionrom 65536 cpu_microcode_blob.bin 0xb10980 microcode 22528 config 0xb16200 raw 5457 revision 0xb17780 raw 570 (empty) 0xb17a00 null 34136 fallback/romstage 0xb1ff80 stage 73116 fallback/ramstage 0xb31d80 stage 74814 fallback/payload 0xb44200 payload 55077 pci8086,1502.rom 0xb51980 raw 61952 bootsplash.jpg 0xb60bc0 raw 59966 (empty) 0xb6f640 null 461144 mrc.cache 0xbdffc0 mrc_cache 65536 (empty) 0xbf0000 null 63512 Any idea what is going wrong here? Best regards, n3ph -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard

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Fwd: Coreboot T-shirts

by Vladimir 'phcoder' Serbinenko

Apparently original mail didn't make it to the list. Resent ---------- Forwarded message ---------- From: Vladimir 'phcoder' Serbinenko <phcoder(a)gmail.com> Date: Thu, May 21, 2015 at 2:29 PM Subject: Re: [coreboot] Coreboot T-shirts To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Cc: coreboot <coreboot(a)coreboot.org> Le 21 mai 2015 13:01, "Carl-Daniel Hailfinger" <c-d.hailfinger.devel.2006(a)gmx.net> a écrit : > > On 21.05.2015 12:51, Vladimir 'phcoder' Serbinenko wrote: > > A contact of mine proposes to print coreboot T-shirts for the community. > > Black printing on white T-shirt. Expected price is 30€-35€ + shipping from > > CH or DE, double-sided printing, one-sided is 5-8€ less. It will be printed > > in Russia. > > Please note that the coreboot T-Shirt I am wearing is black, with the > logo being a white plastic foil melted/glued to the t-shirt. > Could you ask your contact whether such a variant would be possible as > well? The foil variant is extremely durable and IMHO a black T-Shirt > fits a bit better with all the other hacker culture T-Shirts. > I already did. Unfortunately it's not possible at this point > > I need to know who wants one and sizes by June 5th. For payment > > I accept paypal and bank wiring. > > It will be available in ~August. Do we have some kind of dev meeting in > > autumn where I could bring them? > > @carldani: could you give me the file used for printing? > > Sure. > > Regards, > Carl-Daniel -- Regards Vladimir 'phcoder' Serbinenko

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Re: [coreboot] Coreboot T-shirts

by Carl-Daniel Hailfinger

On 21.05.2015 12:51, Vladimir 'phcoder' Serbinenko wrote: > A contact of mine proposes to print coreboot T-shirts for the community. > Black printing on white T-shirt. Expected price is 30€-35€ + shipping from > CH or DE, double-sided printing, one-sided is 5-8€ less. It will be printed > in Russia. Please note that the coreboot T-Shirt I am wearing is black, with the logo being a white plastic foil melted/glued to the t-shirt. Could you ask your contact whether such a variant would be possible as well? The foil variant is extremely durable and IMHO a black T-Shirt fits a bit better with all the other hacker culture T-Shirts. > I need to know who wants one and sizes by June 5th. For payment > I accept paypal and bank wiring. > It will be available in ~August. Do we have some kind of dev meeting in > autumn where I could bring them? > @carldani: could you give me the file used for printing? Sure. Regards, Carl-Daniel

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Coreboot T-shirts

by Vladimir 'phcoder' Serbinenko

A contact of mine proposes to print coreboot T-shirts for the community. Black printing on white T-shirt. Expected price is 30€-35€ + shipping from CH or DE, double-sided printing, one-sided is 5-8€ less. It will be printed in Russia. I need to know who wants one and sizes by June 5th. For payment I accept paypal and bank wiring. It will be available in ~August. Do we have some kind of dev meeting in autumn where I could bring them? @carldani: could you give me the file used for printing?

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Re: [coreboot] SPD CRC failed

by Michael Gerlach

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS... Unfortunately I do not have any other DDR3 modules to test. Best regards, n3ph On 05/20/15 19:20, Vadim Bendebury wrote: > SPD is some data saved on the memory module, available to the > processor to read to find out memory properies. These data are > protected by a check code (CRC) which allows the CPU to verify > that it read the data correctly. Apparently this check is failing > in your case. > > Some likely reasons could be a noisy i2c interface (used to read > SPD) or someone writing the SPD storage on memory module(s) and > corrupteding it. > > --vb > > > On Wed, May 20, 2015 at 8:51 AM, Michael Gerlach > <n3ph(a)terminal21.de> wrote: Hi all, > > i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like > there are some issues regarding the size of the modules.. > > http://pastebin.com/mLcS6vhQ > > Best regards, > > > n3ph >> >> -- coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > - -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBAgAGBQJVXMh0AAoJEE1l5S41evqarKYIALphxsdF9WcQ4g+p561oG6TK VM0c3uRZF+TtISKZ+9h4zbBEISezcYWae0Fyvw6dm3xNzNn6u70aAsYvCXHFHgnu kk/hWxxSN8wIjWha4DZOmHxRxczMJF5cXsPIEWazIU1ftgnid37Ce2JEViDtGMX5 LGB+yKY5L32hkWzUo2g/Ob1A5TdX80ESsAWlxHaWbqRCn0j7BC1o7UT48DfaKAuv wi5mQnW4L+X8r+q9t1f0nv2mGHeGRlU8rXmJ0d+dExAwdPZz+EW4NPHY2brMBT3a 1xh+OVAKkaJXL4ZI1TyaaODRltHDRrZ63g3laVOJR4k6+sA2rI6Q+1DUznhFB6k= =Qthr -----END PGP SIGNATURE-----

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SPD CRC failed

by Michael Gerlach

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like there are some issues regarding the size of the modules.. http://pastebin.com/mLcS6vhQ Best regards, n3ph -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBAgAGBQJVXK2LAAoJEE1l5S41evqaCa8IAMqXBkzXdd72Vsi4mJ6MT73e V3SMLABBJZ/IdEtea1HixhaTYVgyhghMsNsw3rgPSugN0bPKCutL647xz8xORv2r hHQWDO0VF4KScPtGH1cG6YgtZuVB+IJZusM2SqR5WRikGqAV3jn0q1EQbW2CFG4K JzaqhVHUYta/iDi3utvT66CmlJuzr6A+PneB2NvrWc61inHzT8sLM/r55J6zyBH3 4IOw15wJTwPkogHrGeN5artKt7qeKgdUv8VrZZPWtO86qW8QroexQND5mlc+yqyq IQBQ0uzm8FkBkI8WeYQvMCLnfd6iW57pGnxQysf+soDy8+1+/c7xAqkXp5nn3b8= =QBlQ -----END PGP SIGNATURE-----

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Re: [coreboot] New post published at blog.coreboot.org on May 19, 2015 at 4:43 am

by Naman Govil

On Tue, May 19, 2015 at 1:51 PM, Julius Werner <jwerner(a)chromium.org> wrote: > Hi Naman, > > > Presently, arm64 isn’t a supported architecture for coreboot in > emulation, mainly due to the fact that the port we have runs in 32-bit for > bootblock and romstage stages. I would work to re-structure this and get > these stages running in 64-bit. > > Just wanted to make sure you know that we were also planning to rework > the whole bootblock and romstage mess on ARM64 in the near future for > a Chromium project. When you get to that part in your project please > let me know what you're planning to do so we can avoid doing the same > thing twice and stepping on each other's toes. > Sure. > > (Also, not sure if you know this already but we did use to have an > emulation/foundation-armv8 port already that I think even somewhat > booted as some point. It just fell into disrepair with latter changes > but it might still be a useful starting point.) > I didn't know about this. I guess you mean : https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo… Indeed, this would be helpful for a start. Thanks!

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New post published at blog.coreboot.org on May 19, 2015 at 4:43 am

by WordPress

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coreboot May 2015