February 2025 - coreboot - mail.coreboot.org

[coreboot - Bug #548] (New) Computer Fails To Recognize Upgraded WiFi Card
by Jeremy Brown May 17, 2025

May 17, 2025

Issue #548 has been reported by Jeremy Brown. ---------------------------------------- Bug #548: Computer Fails To Recognize Upgraded WiFi Card https://ticket.coreboot.org/issues/548 * Author: Jeremy Brown * Status: New * Priority: Normal * Target version: none * Start date: 2024-07-15 ---------------------------------------- I am running coreboot 24.05 on my Lenovo X201. I decided to upgrade my WiFi card from an Intel Centrino Advanced-N 6205 to an Intel Wireless-AC 7260; since I selected the option to support Intel PCIe cards in my build config I expected everything to work but my computer fails to recognize the new card. The old card is still recognized if I reinstall it so I know I didn't mess up the socket somehow; I've read reports of the 7260 [working with a modded factory BIOS](https://richbits.rbarnes.org/installing-the-intel-7260-in-the-thinkpa… so I don't think there's an electrical issue. I've attached lspci data from both chips, lmk if additional information is needed. ---Files-------------------------------- 6205_lspci_tree.txt (1.63 KB) 7260_lspci_tree.txt (1.57 KB) 6205_lspci.txt (12.8 KB) 7260_lspci.txt (12.2 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #552] (New) X201 not booting with edk2 payload
by Maya Matuszczyk May 17, 2025

May 17, 2025

Issue #552 has been reported by Maya Matuszczyk. ---------------------------------------- Bug #552: X201 not booting with edk2 payload https://ticket.coreboot.org/issues/552 * Author: Maya Matuszczyk * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2024-08-18 * Affected hardware: x201 ---------------------------------------- Hello, I tried to update my x201 with a new version of coreboot(I lost the working one). After building(using default config + set to x201 + bigger cbfs + linear high-res framebuffer) with latest release I couldn't get anything with edk2 to boot on it. I've tried changing `RESOURCE_ALLOCATION_TOP_DOWN` and using newer/older tags of MrChromebox's edk2 fork. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #415] (New) RESOURCE_ALLOCATION_TOP_DOWN breaks edk2
by Sean Rhodes May 2, 2025

May 2, 2025

Issue #415 has been reported by Sean Rhodes. ---------------------------------------- Bug #415: RESOURCE_ALLOCATION_TOP_DOWN breaks edk2 https://ticket.coreboot.org/issues/415 * Author: Sean Rhodes * Status: New * Priority: Low * Target version: none * Start date: 2022-09-07 * Affected versions: master ---------------------------------------- CB:41957 enabled RESOURCE_ALLOCATION_TOP_DOWN by default, which stopped edk2 from booting. The commit has been reverted, so this ticket is just to post logs. ---Files-------------------------------- resource_allocatorv4.txt (94 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #569] (New) coreinfo: i386-elf-gcc-ar: Cannot find binary 'i386-elf-ar'
by Matthias Brugger March 28, 2025

March 28, 2025

Issue #569 has been reported by Matthias Brugger. ---------------------------------------- Bug #569: coreinfo: i386-elf-gcc-ar: Cannot find binary 'i386-elf-ar' https://ticket.coreboot.org/issues/569 * Author: Matthias Brugger * Status: New * Priority: Normal * Target version: none * Start date: 2024-11-14 * Affected versions: master * Related links: https://doc.coreboot.org/tutorial/part1.html ---------------------------------------- Hi, when trying to compile the qemu example with latest branch, I get the following error: ``` ~/src/coreboot/$ make -C payloads/coreinfo/ Makefile:358: warning: overriding recipe for target '/home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/arch/x86/exec.libc.o' Makefile:358: warning: ignoring old recipe for target '/home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/arch/x86/exec.libc.o' AR /home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/libpci.a /home/mbrugger/src/coreboot/payloads/libpayload/../../util/crossgcc/xgcc/bin/i386-elf-gcc-ar: Cannot find binary 'i386-elf-ar' make[1]: *** [Makefile.mk:116: /home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/libpci.a] Error 1 make: *** [../libpayload/Makefile.payload:153: /home/mbrugger/src/coreboot/payloads/coreinfo/libpayload/libpayload.a] Error 2 ``` I double checked and ./util/crossgcc/xgcc/bin/i386-elf-ar exists. I suppose it's a problem in the cross compilation of i386-elf-gcc-ar -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Re: PC with coreboot - boot menu locked
by Paul Menzel Feb. 28, 2025

Feb. 28, 2025

Dear Andrea, Welcome to coreboot. Please do not send messages over 500 kB (definitely not more than 1 MB) to mailing lists. Am 16.02.25 um 18:30 schrieb Andrea Battelli: > I have an embedded system that I want to reuse but the bios is locked up > and when I press the f12 key, it shows only a boot option (payload). How > can I disassemble the bios or rebuild another one? > > Attached is the dump of the rom and the screenshot of the boot menu It’d be great if you just copied the text output from the payload. SeaBIOS (version SageBIOS-20161017_085144-ttyree-dev-gtk-gtech-com) Select boot device: 1. Payload [igt_secure] Sage Engineering [1] *was* a company offering coreboot development a long time ago. No idea, if they upstreamed this board, or how to get the source code. What board is it exactly? Anyway, your attached dump has a coreboot image (CBFS – coreboot file system), you can dump with `cbfstool`: ``` $ ~/src/coreboot/util/cbfstool/cbfstool bios_igt_orig.bin print FMAP REGION: COREBOOT bios_igt_orig.bin: 16384 kB, bootblocksize 1024, romsize 16777216, offset 0xc00000 alignment: 64 bytes, architecture: x86 Name Offset Type Size Comp roothashes 0xc00000 (unknown) 192 none fallback/romstage 0xc00100 stage 60241 none fallback/ramstage 0xc0ecc0 stage 94548 none fallback/payload 0xc25e80 simple elf 49158 none bootsplash.jpg 0xc31ec0 bootsplash 48411 none etc/boot-menu-wait 0xc3dc40 raw 8 none (empty) 0xc3dc80 null 4888 none keyupdate 0xc3efc0 mma 8192 none (empty) 0xc41000 null 3992 none keystore 0xc41fc0 mrc 131072 none img/igt_secure 0xc62000 simple elf 83362 none vgaroms/videobios.rom 0xc76600 optionrom 65536 none (empty) 0xc86640 null 51544 none bootorder 0xc92fc0 raw 4096 none (empty) 0xc94000 null 2604952 none cpu_microcode_blob.bin 0xf0ffc0 microcode 38912 none (empty) 0xf19800 null 157592 none mrc.cache 0xf3ffc0 mrc_cache 65536 none (empty) 0xf50000 null 65432 none fsp.bin 0xf5ffc0 spd 524288 none (empty) 0xfe0000 null 12248 none bootorder_sata 0xfe3000 raw 4096 none bootorder_usb 0xfe4040 raw 4096 none bootorder_sec 0xfe5080 raw 4096 none (empty) 0xfe60c0 null 24 none rootpub 0xfe6100 fsp 2064 none (empty) 0xfe6940 null 103000 none ``` It does not seem to contain the build configuration, but you might be able to boot from a USB device. From there you should be able to read the logs with `cbmem` and find out the coreboot version and board name. Maybe that brings you further. I have never heard of `igt_secure`. As you can access the dump, you can at least build the payload yourself, and replace `fallback/payload` or add it under `img/`. Maybe that works. No idea if the keys/hashes verify anything from this. Anyway, the above should get you going. Kind regards, Paul [1]: https://se-eng.com/ [2]:

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[p8x7x port] Realtek loses its mind & Marvell not going with times.
by Keith Hui Feb. 28, 2025

Feb. 28, 2025

(Catchy subject eh? There's some truth to both.) My coreboot port to Asus P8Z77-V LE PLUS is almost ready, but I still have two outstanding problems. The board is losing its MAC address, partly because it doesn't have an EEPROM for vital product data. I enabled the rtl8168 driver in coreboot so I can configure the LEDs and MAC address. Lights work great, but the MAC address always revert to 00:00:00:00:00:05 by the time Linux kernel sees it. I would then have to reassign its proper MAC address using "ip link change eno0 address <mac>". I added a debug read back in the rtl81xx driver and the device appears to be taking the MAC I programmed. Board also has a Marvell 88SE9120 for two extra SATA ports. It came up in legacy mode and pata_marvell driver isn't able to operate it. I find no documentation on how to switch to AHCI mode like ASM1061. Needless to say those two ports are currently useless. Ideas? I'm hoping to get this and a few supporting patches in for next release. https://review.coreboot.org/c/coreboot/+/86172 Thanks Keith

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Re: PC with coreboot - boot menu locked
by p db Feb. 27, 2025

Feb. 27, 2025

This is NOT free hardware, that is, tying people to solutions: "Digital Restricted Management", when people will understand that they will have to start relying on free hardware solutions, as usual, it will always be too late. Best Regards, Paolo Del Bene Il Gio 27 Feb 2025, 19:57 Andrea Battelli <battelli2(a)gmail.com> ha scritto: > Hi, > > I have an embedded system that I want to reuse but the bios is locked up > and when I press the f12 key, it shows only a boot option (payload). How > can I disassemble the bios or rebuild another one? > > Attached is the dump of the rom and the screenshot of the boot menu > > Thanks > Andrea > > PS: I don't how if it helps but the cpu is a Intel Core i3 4010U > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org > To unsubscribe send an email to coreboot-leave(a)coreboot.org >

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2025_02_26 coreboot Group Review Sesssion
by mina＠coreboot.org Feb. 24, 2025

Feb. 24, 2025

Hello coreboot! Our upcoming biweekly group review meeting is scheduled for Wednesday, February 26. https://meet.google.com/kpu-yozw-gtt Please check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html As usual, we'll begin by reviewing a few patches together, then switch to individual reviews. However, everyone will still be available if you have questions about the patch you're reviewing. Here is the link to the list of patches to be reviewed this week: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…) Kindly add any specific patches you'd like the group to review to the top of the sheet. Thank you. Best regards, Mina.

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Change in coreboot leadership
by David Hendricks Feb. 22, 2025

Feb. 22, 2025

Hi everyone, After six years on the coreboot leadership team I've decided it's time to pass the torch. I joined the leadership team in 2019 while on a mission to get coreboot back on servers and am pleased with the progress that's been made. Now it's time for me to focus on family and other things and make room for somebody more hands-on with the day-to-day activities of the entire community. I'm happy to announce that Martin Roth will be taking over my spot on the leadership team. Though there are several strong contributors in our community, the leadership team has unanimously selected Martin for this position based on his exceptional qualifications: * Over 26 years of combined firmware development experience, including 13 years in the coreboot community and 13 years of BIOS development prior, mostly at Cyrix/National Semiconductor and AMD. * Significant technical contributions through thousands of patches and thoughtful code reviews, along with mentoring several community members. * Martin has maintained coreboot infrastructure for many years, working behind the scenes to keep the whole project going on a shoestring budget. This included years of maintaining our build infrastructure on servers in his basement. * Extensive experience working with (or at) silicon vendors on the foundational components needed to enable coreboot on bleeding-edge x86 platforms (FSP, AGESA, OpenSIL). * Experience at a variety of companies serving various market segments, ranging from embedded systems at National Semiconductor and Sage, to laptops at AMD and Google, and servers at AMD. * Strong commitment to open-source principles combined with technical expertise to achieve the best possible outcomes in our challenging industry. I'll continue in an advisory role and am also ramping up on some administrative tasks to lighten Martin's load so that he has more time to focus on the codebase. Thanks everyone, and congratulations to Martin!

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2025-02-19 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org Feb. 20, 2025

Feb. 20, 2025

# 2025-02-19 - coreboot Leadership Meeting ## Attendees Felix Singer, Andre, Martin Roth, David Hendricks, Alicja Michalska, Julius Werner, Werner Zeh, Matt DeVillier, Andy Ebrahiem, Mina Asante, Karthik Ramasubramanian, Jeremy Compostella. ## Open Action Items * 2024-11-27 * [Open] Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * [Open] Add clarification to docs, “do not use gerrit change-id or CB: format in reference to already-merged patches”. * 2024-10-16 * [Open] Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * [Open] Jon: Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * [Open] Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian (?) * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * [Open] Daniel: Look at how we want to localize (non-console) strings for coreboot. Long term project. ## Minutes ### [Werner] Update on Intel’s plans around signing their FSP binaries * Currently not POR for API-mode binary, only for dispatch mode * It should not impact the coreboot flow. However, NDA customers need to keep an eye on it since if it does impact coreboot then that will be a drastic change. * Doc #830299 and #827444 ### [David] Change in coreboot leadership * Martin Roth will take my spot ### [Martin] AMD releasing Phoenix and Turin OpenSIL * Hopefully in February or early March * Somewhat more detail: (https://github.com/openSIL/openSIL/issues/24) * It'll be a while before releasing another one as they switch from proof-of-concept (POC) to plan-of-record (POR), migrating from AGESA to OpenSIL on next-gen SOCs. * Limits of POC * No graphics init, but could use the GOP driver with some effort in creating a wrapper. * Graphics init will be done in GOP driver (UEFI-specific) moving forward * coreboot needs a way to deal with this * We have yabel, x86emu, etc. for legacy graphics init. * uGOP or previous efforts? * AMD doesn't do graphics init before memory is up. * uGOP replaced open-source graphics init, which is the cause of the earlier pushback. * [Alicja] u-boot might have a workable solution? * Need to see what the current status is and potentially borrow parts of it to deal with graphics init. * Linux might be able to init graphics, but AtomBIOS tables still need to be filled in for kernel drivers to read. * [Alicja] On Intel side, there are video BIOS tables as well that fills in things like ports present. Alicja has gotten this working with coreboot + EDK2 by using GOP driver. * [Martin] Another option is to run GOP driver once in the tianocore payload to generate AtomBIOS tables, store the info, and then skip GOP driver on subsequent boots. * It's just a 64KiB chunk of data. * People with AMD NDA support can get a customized AtomBIOS table for their platform. Workarounds to run the GOP driver are more for the community to use. # Next Leadership Meeting * March 5, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course, items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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