coreboot January 2006

coreboot@coreboot.org

38 participants
64 discussions

by Ken Fuchs

> On Wed, Aug 03, 2005 at 11:59:20AM +0900, Jun OKAJIMA wrote: > > Probably, most guys here use BIOS Saver. > > And it works well? > > In mine, RD1 for PLCC gets not being writable suddenly. > > I mean, it seems writable but # flash_rom -v fails. > > I solved this problem by a quick hack. > > > > How about yours? You can write RD1 or W49F002U well? > > Any problem happen? Johnathan McDowell wrote: > Even after that it's sometimes a bit flakey and I have to erase, then > write it. I've put the board's original BIOS in the RD1 and am writing > to the SST 39SF020A instead, which works without problems. I've read posts about the RD1 that suggest its integrated flash device is low quality and it may take 10 or more flash attempts to get a good flash update to the RD1 flash device. As a result, many RD1 BIOS Savior users will flash the commercial BIOS image (or other known good BIOS image) into the RD1 integrated flash device as many times as needed to get an image that boots. Then use the original BIOS device to flash test BIOS image (usually LinuxBIOS images among this group), since the original BIOS device usually flashes OK on the first attempt. I've used the RD1 in the above fashion with great success on the Tyan S2885 mainboard. The same RD1 would not work on the nVidia CK8-04 CRB mainboard. I think the CK8-04 CRB requires a flash device that the RD1 does not support. However, the RD1 worked well as an "do nothing" adapter which allowed swapping the BIOS flash device between my flash burner and the mainboard without any wear to the mainboard's BIOS socket. BTW, my flash burner is an older Enhanced Willem Universal Programmer. I got mine for only $60 US over a year ago. I've seen it for less than $40 on eBay a few weeks ago. The newest model is going for about $50 US. It does a LinuxBIOS flash in about 5 minutes; not bad for a $60 burner. However, it does require changing DIP switches to match an image for each device it can program. Great for the amateur or professional with a small budget. > > BTW, a cable of your RD1 is not broken? > > I needed soldering to fix it. > Mine was fine out of the box. Mine cable and switch worked fine out of the box as well. Sincerely, Ken Fuchs <kfuchs(a)winternet.com> ami-mac-sun

14 years, 7 months

[LinuxBIOS] LinuxBIOS support for nvidia CK804 northbridge?

by Carl-Daniel Hailfinger

Hi, in the process of trying to find any motherboard with more than 3 PCI-Express slots and LinuxBIOS support, I failed miserably. It seems such boards only exist with nVidia CK804 northbridges for which I couldn't find any code in the LinuxBIOS source code. Section 2.9 of the LinuxBIOS FAQ suggests to send lspci -vvv to this list for closer inspection. One of those systems with 4 PCIe slots is the Asus K8N-SLI Deluxe. The lspci below contains four PCIe gigabit ethernet controllers at 0000:01:00.0, 0000:02:00.0, 0000:03:00.0 and 0000:04:00.0. It's the only motherboard with this northbridge I have access to at the moment. switch:~ # lspci -vvv 0000:00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [44] #08 [01e0] Capabilities: [e0] #08 [a801] 0000:00:01.0 ISA bridge: nVidia Corporation: Unknown device 0050 (rev a3) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 0000:00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at e400 [size=32] Region 4: I/O ports at 4c00 [size=64] Region 5: I/O ports at 4c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 201 Region 0: Memory at d3004000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a3) (prog-if 20 [EHCI]) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 177 Region 0: Memory at d3005000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] #0a [2098] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:04.0 Multimedia audio controller: nVidia Corporation CK804 AC'97 Audio Controller (rev a2) Subsystem: ASUSTeK Computer Inc.: Unknown device 812a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (500ns min, 1250ns max) Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at dc00 [size=256] Region 1: I/O ports at e000 [size=256] Region 2: Memory at d3003000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev a2) (prog-if 8a [Master SecP PriP]) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Region 4: I/O ports at f000 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 177 Region 0: I/O ports at 09f0 [size=8] Region 1: I/O ports at 0bf0 [size=4] Region 2: I/O ports at 0970 [size=8] Region 3: I/O ports at 0b70 [size=4] Region 4: I/O ports at d800 [size=16] Region 5: Memory at d3002000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc.: Unknown device 815a Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 185 Region 0: I/O ports at 09e0 [size=8] Region 1: I/O ports at 0be0 [size=4] Region 2: I/O ports at 0960 [size=8] Region 3: I/O ports at 0b60 [size=4] Region 4: I/O ports at c400 [size=16] Region 5: Memory at d3001000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=128 I/O behind bridge: 0000a000-0000afff Memory behind bridge: ce000000-d0ffffff Prefetchable memory behind bridge: c0000000-c7ffffff BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- 0000:00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3) Subsystem: ASUSTeK Computer Inc.: Unknown device 8141 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 193 Region 0: Memory at d3000000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b000 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, cache line size 08 Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 00009000-00009fff Memory behind bridge: cc000000-cdffffff Prefetchable memory behind bridge: 00000000fff00000-0000000000000000 BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, cache line size 08 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00008000-00008fff Memory behind bridge: ca000000-cbffffff Prefetchable memory behind bridge: 00000000fff00000-0000000000000000 BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, cache line size 08 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00007000-00007fff Memory behind bridge: c8000000-c9ffffff Prefetchable memory behind bridge: 00000000fff00000-0000000000000000 BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0, cache line size 08 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00006000-00006fff Memory behind bridge: d1000000-d2ffffff Prefetchable memory behind bridge: 00000000fff00000-0000000000000000 BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] #08 [a800] Capabilities: [80] #10 [0141] 0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] 0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 0000:01:00.0 Ethernet controller: SysKonnect SK-9Exx 10/100/1000Base-T Adapter (rev 10) Subsystem: SysKonnect SK-9E21D 10/100/1000Base-T Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- Latency: 0, cache line size 08 Interrupt: pin A routed to IRQ 233 Region 0: Memory at d2000000 (64-bit, non-prefetchable) [size=16K] Region 2: I/O ports at 6000 [size=256] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [5c] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [e0] #10 [0011] 0000:02:00.0 Ethernet controller: SysKonnect SK-9Exx 10/100/1000Base-T Adapter (rev 10) Subsystem: SysKonnect SK-9E21D 10/100/1000Base-T Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- Latency: 0, cache line size 08 Interrupt: pin A routed to IRQ 225 Region 0: Memory at c9000000 (64-bit, non-prefetchable) [size=16K] Region 2: I/O ports at 7000 [size=256] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [5c] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [e0] #10 [0011] 0000:03:00.0 Ethernet controller: SysKonnect SK-9Exx 10/100/1000Base-T Adapter (rev 10) Subsystem: SysKonnect SK-9E21D 10/100/1000Base-T Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- Latency: 0, cache line size 08 Interrupt: pin A routed to IRQ 217 Region 0: Memory at cb000000 (64-bit, non-prefetchable) [size=16K] Region 2: I/O ports at 8000 [size=256] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [5c] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [e0] #10 [0011] 0000:04:00.0 Ethernet controller: SysKonnect SK-9Exx 10/100/1000Base-T Adapter (rev 10) Subsystem: SysKonnect SK-9E21D 10/100/1000Base-T Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- Latency: 0, cache line size 08 Interrupt: pin A routed to IRQ 209 Region 0: Memory at cd000000 (64-bit, non-prefetchable) [size=16K] Region 2: I/O ports at 9000 [size=256] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [5c] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [e0] #10 [0011] 0000:05:06.0 VGA compatible controller: nVidia Corporation NV18 [GeForce4 MX 4000 AGP 8x] (rev c1) (prog-if 00 [VGA]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (1250ns min, 250ns max) Interrupt: pin A routed to IRQ 12 Region 0: Memory at ce000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at c0000000 (32-bit, prefetchable) [size=128M] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:05:0b.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) (prog-if 10 [OHCI]) Subsystem: ASUSTeK Computer Inc.: Unknown device 808b Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (500ns min, 1000ns max), cache line size 08 Interrupt: pin A routed to IRQ 12 Region 0: Memory at d0008000 (32-bit, non-prefetchable) [size=2K] Region 1: Memory at d0000000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:05:0c.0 Ethernet controller: Marvell Technology Group Ltd. Gigabit Ethernet Controller (rev 13) Subsystem: ASUSTeK Computer Inc. Marvell 88E8001 Gigabit Ethernet Controller (Asus) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (5750ns min, 7750ns max), cache line size 08 Interrupt: pin A routed to IRQ 209 Region 0: Memory at d0004000 (32-bit, non-prefetchable) [size=16K] Region 1: I/O ports at a000 [size=256] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data The only references to something similar were a post archived at http://www.mail-archive.com/linuxbios@openbios.org/msg00792.html but the thread seemed to end inconclusive and another post at http://www.mail-archive.com/linuxbios@openbios.org/msg01023.html Is there any support for that nvidia northbridge underway? Regards, Carl-Daniel

15 years, 9 months

[LinuxBIOS] bus 0 dev 0 and fidvid change

by Lu, Yinghai

Please check the issue 41, I make K8 MB can be compiled, and It include bus0/dev0 and fidvid change enhancement HT_CHAIN_UNITID_BASE Default is 1, and if it is 6, then amd8131 will be from 6, also if it is 0, will assume ht chain only have one HT device... HT_CHAIN_END_UNITID_BASE Default is 0x20 --- mean do not use that, if it is 0, the amd8111 will be dev0 SB_HT_CHAIN_UNITID_OFFSET_ONLY Default is 1, so if HT_CHAIN_UNITID_BASE!=1, will only offset unitid of SB CHAIN. K8_SB_HT_CHAIN_ON_BUS0 Deault is 0, if it is 1, will put sb chain on bus 0, even for S2885 sb ht is on link2, it will put on bus0. K8_SET_FIDVID in cache_as_ram_auto.c or auto.c Fidvid change to sync the fid on 4 way or more system with different cpu installed.... Put following sequence in your cache_as_ram_auto.c after ht is set. enable_fid_change(); enable_fid_change_on_sb(); init_fidvid_bsp(bsp_apicid); please check init_cpus.c and fidvid.c and amd8111_early_ctrl.c for detail.... YH

15 years, 9 months

[LinuxBIOS] I'm back

by Ronald G Minnich

I am going to start trying to catch up our svn info. Will those of you have a mobo working, please send me: the mobo name the xvn revision so I can fill out the table. ron

15 years, 11 months

[LinuxBIOS] VIA EPIA-ML6000EA VGA Problem and Kernel Panic

by Daniel Parthey

Dear List Members, I tried to get LinuxBIOS Rev 2163 running on an VIA EPIA-ML6000EA Board using the EPIA-M target. The kernel is on /dev/hda1 of an IDE harddisk. After building the rom image vgabios+linuxbios[filo] I did the following: Boot factory BIOS Remove BIOS chip Insert Test chip Write linuxbios.rom image to flash Reboot, it booted, network worked, but vga output failed Reboot, it booted, network worked, but vga output failed Switched off power Switched on power Graphic output totally fails and kernel panic occurs, my LinuxBIOS.rom does not boot on its own anymore. Maybe this has something to do with the VGA Bios, but I don't know what the reason could be? I extracted the VGA Bios from the running system with original BIOS with the following command and get an video.bios.bin with the 55 aa in the first two bytes: dd if=/dev/mem of=/video.bios.bin bs=65536 count=1 skip=12 At some other location I read something about other weird dd parameters. The resulting vga image from /dev/mem looked as follows: $ ls -l video.bios.bin -rw-r--r-- 1 pada pada 65536 2006-01-23 10:31 video.bios.bin $ file video.bios.bin video.bios.bin: BIOS (ia32) ROM Ext. IBM comp. Video (118*512) $ hd video.bios.bin | head 00000000 55 aa 76 e9 ac 89 90 1b 82 ea 74 8d 00 00 00 00 |Uv....t.....| 00000010 00 00 00 00 00 00 00 00 44 00 a5 37 c5 00 49 42 |........D.7.IB| 00000020 4d 20 43 4f 4d 50 41 54 49 42 4c 45 42 43 50 4f |M COMPATIBLEBCPO| 00000030 53 54 00 00 18 00 30 34 2f 30 38 2f 30 34 00 09 |ST....04/08/04..| 00000040 00 c0 c6 00 50 43 49 52 06 11 22 31 00 00 18 00 |..PCIR.."1....| 00000050 00 00 00 03 40 00 51 01 00 80 00 00 00 01 20 20 |....@.Q....... | 00000060 20 56 49 41 20 54 65 63 68 2e 20 49 6e 63 2e 20 | VIA Tech. Inc. | 00000070 56 54 33 31 32 33 20 20 20 4d 6f 62 69 6c 65 20 |VT3123 Mobile | 00000080 20 56 54 31 36 32 32 90 c2 00 40 56 65 72 34 30 | VT1622..@Ver40| 00000090 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 00 | ....| Is this VGA Bios Image correct? I hacked the Makefile to prepend vga.bios.bin to the bios image (as described in the VIA EPIA-M howto) Now I get a kernel panic with the following output on ttyS0 and the system hangs. And Ideas what I could try to prevent the kernel panic? Here's the full console output from null modem connection on ttyS0: LinuxBIOS-1.1.8.0Fallback Mon Jan 23 11:24:51 CET 2006 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 02 Total Memory (*16 Mb) 20 CAS Supported 2.5 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)00 Cycle time at CL X-1 (nS)00 Starting at CAS 2.5 tRP 48 tRCD 48 tRAS 28 Low Bond 00 High Bondc3 Setting DQS delay82vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 20 20 20 00 00 60:02 ff 00 30 e6 32 01 24 42 2d 43 58 84 55 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 12 02 80:0f 64 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 48 00 00 04 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 01 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.8.0Fallback Mon Jan 23 11:24:51 CET 2006 booting... clocks_per_usec: 1495 Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled Disabling static device: PCI: 00:0a.0 Disabling static device: PCI: 00:0a.1 In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In vt8235_enable 1106 3104. PCI: 00:10.3 [1106/3104] enabled In vt8235_enable 1106 3177. Initialising Devices PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable ffff ffff. In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=01 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: pci_scan_bus returning with max=01 done Allocating resources... Reading resources... Done reading resources. Setting resources... I would set ram size to 0x80000 Kbytes PCI: 00:10.0 20 <- [0x0000001800 - 0x000000181f] io PCI: 00:10.1 20 <- [0x0000001820 - 0x000000183f] io PCI: 00:10.2 20 <- [0x0000001840 - 0x000000185f] io PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] mem PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] io PCI: 00:11.1 20 <- [0x0000001860 - 0x000000186f] io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] io PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] mem Done setting resources. Done allocating resources. Enabling resourcess... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 147 PCI: 01:00.0 cmd <- 140 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 141 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 141 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 141 PCI: 00:10.3 subsystem <- 00/00 PCI: 00:10.3 cmd <- 142 PCI: 00:11.0 cmd <- 147 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PCI: 00:11.1 cmd <- 147 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 done. Initializing devices... Root Device init PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:11.0 init vt8235 init RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 00011040 setting firewire setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.1 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.2 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 5 to 0:10.3 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:11.5 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vga Assigning IRQ 5 to 1:0.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting pci slot setting cardbus slot setting riser slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x0 enables in reg 0x42 read back as 0x0 enables in reg 0x40 0x13 enables in reg 0x40 read back as 0x13 enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 698 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 256MB, type WB Setting variable MTRR 1, base: 256MB, range: 128MB, type WB Setting variable MTRR 2, base: 384MB, range: 64MB, type WB Setting variable MTRR 3, base: 448MB, range: 32MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 01:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 biosint: # 0x6, eax 0x5f53 ebx 0x101 ecx 0x19f88 edx 0xe093 biosint: ebp 0x19090 esp 0x39d8 edi 0xfa90 esi 0x1a539 biosint: ip 0xc763 cs 0xf000 flags 0x202 biosint: Oops, exception 6 biosint: Bailing out biosint: # 0x10, eax 0x4f14 ebx 0x18003 ecx 0x1 edx 0x0 biosint: ebp 0x19fa8 esp 0xffa edi 0x0 esi 0xffff725e biosint: ip 0x8f7e cs 0x0 flags 0x46 BIOSINT: Unsupport int #0x10 Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. ACPI: Writing ACPI tables at f0400... ACPI: * FACS ACPI: * DSDT @ 000f049e Length 3f0 ACPI: * FADT ACPI: added table 1/5 Length now 40 ACPI: done. Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000b5c checksum bcdc Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 33:stream_init() - rom_stream: 0xfffd0000 - 0xfffeffff Found ELF candiate at offset 0 New segment addr 0x100000 size 0x23fc0 offset 0xc0 filesize 0x9f48 (cleaned up) New segment addr 0x100000 size 0x23fc0 offset 0xc0 filesize 0x9f48 New segment addr 0x123fc0 size 0x48 offset 0xa020 filesize 0x48 (cleaned up) New segment addr 0x123fc0 size 0x48 offset 0xa020 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000023fc0 filesz: 0x0000000000009f48 Clearing Segment: addr: 0x0000000000109f48 memsz: 0x000000000001a078 Loading Segment: addr: 0x0000000000123fc0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x107c80 FILO version 0.4.2 (pada@vranx) Mon Jan 23 10:46:07 CET 2006 boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 hda: LBA 6499MB: IBM-DHEA-36481 hdb: ATAPI: TOSHIBA CD-ROM XM-6602B Mounted ext2fs Found Linux version 2.6.14.2static (pada@vranx) #3 Thu Jan 26 12:43:13 CET 2006 bzImage. Loading kernel... ok Jumping to entry point... Linux version 2.6.14.2static (pada@vranx) (gcc-Version 3.3.5 (Debian 1:3.3.5-13)) #3 Thu Jan 26 12:43:13 CET 2006 BIOS-provided physical RAM map: BIOS-e820: 0000000000000ba4 - 00000000000a0000 (usable) BIOS-e820: 0000000000100000 - 000000001e000000 (usable) 480MB LOWMEM available. DMI not present. ACPI: PM-Timer IO Port: 0x408 Allocating PCI resources starting at 20000000 (gap: 1e000000:e2000000) Built 1 zonelists Kernel command line: root=/dev/hda1 console=tty0 console=ttyS0,115200 No local APIC present or hardware disabled Initializing CPU#0 PID hash table entries: 2048 (order: 11, 32768 bytes) Detected 666.401 MHz processor. Using pmtmr for high-res timesource Console: colour dummy device 80x25 Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) Memory: 480144k/491520k available (4492k kernel code, 10892k reserved, 1495k data, 248k init, 0k highmem) Checking if this processor honours the WP bit even in supervisor mode... Ok. Calibrating delay using timer specific routine.. 1334.55 BogoMIPS (lpj=2669102) Mount-cache hash table entries: 512 CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line) CPU: L2 Cache: 64K (32 bytes/line) mtrr: v2.0 (20020519) CPU: Centaur VIA Nehemiah stepping 08 Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Checking 'hlt' instruction... OK. ACPI: setting ELCR to 0020 (from 0220) NET: Registered protocol family 16 ACPI: bus type pci registered Unable to handle kernel NULL pointer dereference at virtual address 00000000 printing eip: c00fa955 *pde = 00000000 Oops: 0000 [#1] CPU: 0 EIP: 0060:[<c00fa955>] Not tainted VLI EFLAGS: 00010046 (2.6.14.2static) EIP is at 0xc00fa955 eax: 49435000 ebx: 000f0000 ecx: 0400d5b4 edx: 0000a960 esi: 00000000 edi: c0675d64 ebp: 49435024 esp: c149ff32 ds: 007b es: 007b ss: 0068 Process swapper (pid: 1, threadinfo=c149e000 task=c144aa50) Stack: 54ba0046 0060c044 00010000 1b080000 000ac073 02960000 42db0000 a4a0c012 0000c00f 00000000 00000000 553f0000 5024c044 674e4943 4f6ac010 f240c010 0000c00e 00000000 00000000 00000000 00000000 00000000 007b0000 a4a00000 Call Trace: Code: 00 00 32 c0 66 9d cb 3d 24 50 43 49 77 17 0a db 75 17 bb 00 00 0f 00 ba 60 a9 00 00 b9 b4 d5 00 04 32 c0 eb 06 b0 80 eb 02 b0 81 <6e> 9d cb 87 db 87 db 87 db 87 db 66 9c fa 3c 01 75 0a e8 9c 00 <0>Kernel panic - not syncing: Attempted to kill init! Thanks for any help, Daniel

15 years, 11 months

[LinuxBIOS] Fwd: [Linux-fbdev-devel] [patch] Framebuffer driver for Geode GX

by Richard Smith

This may be of interest to some people working with the Geode GX ---------- Forwarded message ---------- From: David Vrabel <dvrabel(a)arcom.com> Date: Jan 31, 2006 12:19 PM Subject: [Linux-fbdev-devel] [patch] Framebuffer driver for Geode GX To: linux-fbdev-devel list <linux-fbdev-devel(a)lists.sourceforge.net> A framebuffer driver for the display controller in AMD Geode GX processors (Geode GX533, Geode GX500 etc.). Tested at 640x480, 800x600, 1024x768 and 1280x1024 at 8, 16, and 24 bpp with both CRT and TFT. No accelerated features currently implemented and compression remains disabled. This driver requires that the BIOS (or the SoftVG/Firmbase code in the BIOS) has created an appropriate virtual PCI header. Signed-off-by: David Vrabel <dvrabel(a)arcom.com> -- David Vrabel, Design Engineer Arcom, Clifton Road Tel: +44 (0)1223 411200 ext. 3233 Cambridge CB1 7EA, UK Web: http://www.arcom.com/ Index: linux-2.6-working/drivers/video/geode/Kconfig =================================================================== --- linux-2.6-working.orig/drivers/video/geode/Kconfig 2006-01-31 16:59:20.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/Kconfig 2006-01-31 16:59:51.000000000 +0000 @@ -8,6 +8,21 @@ Say 'Y' here to allow you to select framebuffer drivers for the AMD Geode family of processors. +config FB_GEODE_GX + tristate "AMD Geode GX framebuffer support (EXPERIMENTAL)" + depends on FB_GEODE && EXPERIMENTAL + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Framebuffer driver for the display controller integrated into the + AMD Geode GX processors. + + To compile this driver as a module, choose M here: the module will be + called gxfb. + + If unsure, say N. + config FB_GEODE_GX1 tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)" depends on FB_GEODE && EXPERIMENTAL Index: linux-2.6-working/drivers/video/geode/Makefile =================================================================== --- linux-2.6-working.orig/drivers/video/geode/Makefile 2006-01-31 16:59:20.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/Makefile 2006-01-31 16:59:51.000000000 +0000 @@ -1,5 +1,7 @@ # Makefile for the Geode family framebuffer drivers obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o +obj-$(CONFIG_FB_GEODE_GX) += gxfb.o -gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o +gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o +gxfb-objs := gxfb_core.o display_gx.o video_gx.o Index: linux-2.6-working/drivers/video/geode/display_gx.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/display_gx.c 2006-01-31 16:59:51.000000000 +0000 @@ -0,0 +1,156 @@ +/* + * Geode GX display controller. + * + * Copyright (C) 2005 Arcom Control Systems Ltd. + * + * Portions from AMD's original 2.4 driver: + * Copyright (C) 2004 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by * the + * Free Software Foundation; either version 2 of the License, or * (at your + * option) any later version. + */ +#include <linux/spinlock.h> +#include <linux/fb.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <asm/div64.h> +#include <asm/delay.h> + +#include "geodefb.h" +#include "display_gx.h" + +int gx_frame_buffer_size(void) +{ + /* Assuming 16 MiB. */ + return 16*1024*1024; +} + +int gx_line_delta(int xres, int bpp) +{ + /* Must be a multiple of 8 bytes. */ + return (xres * (bpp >> 3) + 7) & ~0x7; +} + +static void gx_set_mode(struct fb_info *info) +{ + struct geodefb_par *par = info->par; + u32 gcfg, dcfg; + int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; + int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; + + /* Unlock the display controller registers. */ + readl(par->dc_regs + DC_UNLOCK); + writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); + + gcfg = readl(par->dc_regs + DC_GENERAL_CFG); + dcfg = readl(par->dc_regs + DC_DISPLAY_CFG); + + /* Disable the timing generator. */ + dcfg &= ~(DC_DCFG_TGEN); + writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); + + /* Wait for pending memory requests before disabling the FIFO load. */ + udelay(100); + + /* Disable FIFO load and compression. */ + gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); + writel(gcfg, par->dc_regs + DC_GENERAL_CFG); + + /* Setup DCLK and its divisor. */ + par->vid_ops->set_dclk(info); + + /* + * Setup new mode. + */ + + /* Clear all unused feature bits. */ + gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE; + dcfg = 0; + + /* Set FIFO priority (default 6/5) and enable. */ + /* FIXME: increase fifo priority for 1280x1024 and higher modes? */ + gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; + + /* Framebuffer start offset. */ + writel(0, par->dc_regs + DC_FB_ST_OFFSET); + + /* Line delta and line buffer length. */ + writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH); + writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, + par->dc_regs + DC_LINE_SIZE); + + /* Enable graphics and video data and unmask address lines. */ + dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M; + + /* Set pixel format. */ + switch (info->var.bits_per_pixel) { + case 8: + dcfg |= DC_DCFG_DISP_MODE_8BPP; + break; + case 16: + dcfg |= DC_DCFG_DISP_MODE_16BPP; + dcfg |= DC_DCFG_16BPP_MODE_565; + break; + case 32: + dcfg |= DC_DCFG_DISP_MODE_24BPP; + dcfg |= DC_DCFG_PALB; + break; + } + + /* Enable timing generator. */ + dcfg |= DC_DCFG_TGEN; + + /* Horizontal and vertical timings. */ + hactive = info->var.xres; + hblankstart = hactive; + hsyncstart = hblankstart + info->var.right_margin; + hsyncend = hsyncstart + info->var.hsync_len; + hblankend = hsyncend + info->var.left_margin; + htotal = hblankend; + + vactive = info->var.yres; + vblankstart = vactive; + vsyncstart = vblankstart + info->var.lower_margin; + vsyncend = vsyncstart + info->var.vsync_len; + vblankend = vsyncend + info->var.upper_margin; + vtotal = vblankend; + + writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING); + writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING); + writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING); + + writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING); + writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING); + writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING); + + /* Write final register values. */ + writel(dcfg, par->dc_regs + DC_DISPLAY_CFG); + writel(gcfg, par->dc_regs + DC_GENERAL_CFG); + + par->vid_ops->configure_display(info); + + /* Relock display controller registers */ + writel(0, par->dc_regs + DC_UNLOCK); +} + +static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno, + unsigned red, unsigned green, unsigned blue) +{ + struct geodefb_par *par = info->par; + int val; + + /* Hardware palette is in RGB 8-8-8 format. */ + val = (red << 8) & 0xff0000; + val |= (green) & 0x00ff00; + val |= (blue >> 8) & 0x0000ff; + + writel(regno, par->dc_regs + DC_PAL_ADDRESS); + writel(val, par->dc_regs + DC_PAL_DATA); +} + +struct geode_dc_ops gx_dc_ops = { + .set_mode = gx_set_mode, + .set_palette_reg = gx_set_hw_palette_reg, +}; Index: linux-2.6-working/drivers/video/geode/display_gx.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/display_gx.h 2006-01-31 16:59:51.000000000 +0000 @@ -0,0 +1,96 @@ +/* + * Geode GX display controller + * + * Copyright (C) 2006 Arcom Control Systems Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DISPLAY_GX_H__ +#define __DISPLAY_GX_H__ + +int gx_frame_buffer_size(void); +int gx_line_delta(int xres, int bpp); + +extern struct geode_dc_ops gx_dc_ops; + +/* Display controller registers */ + +#define DC_UNLOCK 0x00 +# define DC_UNLOCK_CODE 0x00004758 + +#define DC_GENERAL_CFG 0x04 +# define DC_GCFG_DFLE 0x00000001 +# define DC_GCFG_CURE 0x00000002 +# define DC_GCFG_ICNE 0x00000004 +# define DC_GCFG_VIDE 0x00000008 +# define DC_GCFG_CMPE 0x00000020 +# define DC_GCFG_DECE 0x00000040 +# define DC_GCFG_VGAE 0x00000080 +# define DC_GCFG_DFHPSL_MASK 0x00000F00 +# define DC_GCFG_DFHPSL_POS 8 +# define DC_GCFG_DFHPEL_MASK 0x0000F000 +# define DC_GCFG_DFHPEL_POS 12 +# define DC_GCFG_STFM 0x00010000 +# define DC_GCFG_FDTY 0x00020000 +# define DC_GCFG_VGAFT 0x00040000 +# define DC_GCFG_VDSE 0x00080000 +# define DC_GCFG_YUVM 0x00100000 +# define DC_GCFG_VFSL 0x00800000 +# define DC_GCFG_SIGE 0x01000000 +# define DC_GCFG_SGRE 0x02000000 +# define DC_GCFG_SGFR 0x04000000 +# define DC_GCFG_CRC_MODE 0x08000000 +# define DC_GCFG_DIAG 0x10000000 +# define DC_GCFG_CFRW 0x20000000 + +#define DC_DISPLAY_CFG 0x08 +# define DC_DCFG_TGEN 0x00000001 +# define DC_DCFG_GDEN 0x00000008 +# define DC_DCFG_VDEN 0x00000010 +# define DC_DCFG_TRUP 0x00000040 +# define DC_DCFG_DISP_MODE_MASK 0x00000300 +# define DC_DCFG_DISP_MODE_8BPP 0x00000000 +# define DC_DCFG_DISP_MODE_16BPP 0x00000100 +# define DC_DCFG_DISP_MODE_24BPP 0x00000200 +# define DC_DCFG_16BPP_MODE_MASK 0x00000c00 +# define DC_DCFG_16BPP_MODE_565 0x00000000 +# define DC_DCFG_16BPP_MODE_555 0x00000100 +# define DC_DCFG_16BPP_MODE_444 0x00000200 +# define DC_DCFG_DCEN 0x00080000 +# define DC_DCFG_PALB 0x02000000 +# define DC_DCFG_FRLK 0x04000000 +# define DC_DCFG_VISL 0x08000000 +# define DC_DCFG_FRSL 0x20000000 +# define DC_DCFG_A18M 0x40000000 +# define DC_DCFG_A20M 0x80000000 + +#define DC_FB_ST_OFFSET 0x10 + +#define DC_LINE_SIZE 0x30 +# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff +# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0 +# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000 +# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16 +# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000 +# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24 + +#define DC_GFX_PITCH 0x34 +# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff +# define DC_GFX_PITCH_FB_PITCH_POS 0 +# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000 +# define DC_GFX_PITCH_CB_PITCH_POS 16 + +#define DC_H_ACTIVE_TIMING 0x40 +#define DC_H_BLANK_TIMING 0x44 +#define DC_H_SYNC_TIMING 0x48 +#define DC_V_ACTIVE_TIMING 0x50 +#define DC_V_BLANK_TIMING 0x54 +#define DC_V_SYNC_TIMING 0x58 + +#define DC_PAL_ADDRESS 0x70 +#define DC_PAL_DATA 0x74 + +#endif /* !__DISPLAY_GX1_H__ */ Index: linux-2.6-working/drivers/video/geode/gxfb_core.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/gxfb_core.c 2006-01-31 17:00:19.000000000 +0000 @@ -0,0 +1,423 @@ +/* + * Geode GX framebuffer driver. + * + * Copyright (C) 2006 Arcom Control Systems Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * This driver assumes that the BIOS has created a virtual PCI device header + * for the video device. The PCI header is assumed to contain the following + * BARs: + * + * BAR0 - framebuffer memory + * BAR1 - graphics processor registers + * BAR2 - display controller registers + * BAR3 - video processor and flat panel control registers. + * + * 16 MiB of framebuffer memory is assumed to be available. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <linux/tty.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/pci.h> + +#include "geodefb.h" +#include "display_gx.h" +#include "video_gx.h" + +static char mode_option[32] = "640x480-16@60"; + +/* Modes relevant to the GX (taken from modedb.c) */ +static const struct fb_videomode __initdata gx_modedb[] = { + /* 640x480-60 VESA */ + { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, + 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 640x480-75 VESA */ + { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, + 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 640x480-85 VESA */ + { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, + 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 800x600-60 VESA */ + { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 800x600-75 VESA */ + { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 800x600-85 VESA */ + { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1024x768-60 VESA */ + { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, + 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1024x768-75 VESA */ + { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1024x768-85 VESA */ + { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1280x960-60 VESA */ + { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1280x960-85 VESA */ + { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1280x1024-60 VESA */ + { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1280x1024-75 VESA */ + { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1280x1024-85 VESA */ + { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1600x1200-60 VESA */ + { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1600x1200-75 VESA */ + { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1600x1200-85 VESA */ + { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, +}; + +static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + if (var->xres > 1600 || var->yres > 1200) + return -EINVAL; + if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16) + return -EINVAL; + + if (var->bits_per_pixel == 32) { + var->red.offset = 16; var->red.length = 8; + var->green.offset = 8; var->green.length = 8; + var->blue.offset = 0; var->blue.length = 8; + } else if (var->bits_per_pixel == 16) { + var->red.offset = 11; var->red.length = 5; + var->green.offset = 5; var->green.length = 6; + var->blue.offset = 0; var->blue.length = 5; + } else if (var->bits_per_pixel == 8) { + var->red.offset = 0; var->red.length = 8; + var->green.offset = 0; var->green.length = 8; + var->blue.offset = 0; var->blue.length = 8; + } else + return -EINVAL; + var->transp.offset = 0; var->transp.length = 0; + + /* Enough video memory? */ + if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len) + return -EINVAL; + + /* FIXME: Check timing parameters here? */ + + return 0; +} + +static int gxfb_set_par(struct fb_info *info) +{ + struct geodefb_par *par = info->par; + + if (info->var.bits_per_pixel > 8) { + info->fix.visual = FB_VISUAL_TRUECOLOR; + fb_dealloc_cmap(&info->cmap); + } else { + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0); + } + + info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel); + + par->dc_ops->set_mode(info); + + return 0; +} + +static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) +{ + struct geodefb_par *par = info->par; + + if (info->var.grayscale) { + /* grayscale = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; + } + + /* Truecolor has hardware independent palette */ + if (info->fix.visual == FB_VISUAL_TRUECOLOR) { + u32 *pal = info->pseudo_palette; + u32 v; + + if (regno >= 16) + return -EINVAL; + + v = chan_to_field(red, &info->var.red); + v |= chan_to_field(green, &info->var.green); + v |= chan_to_field(blue, &info->var.blue); + + pal[regno] = v; + } else { + if (regno >= 256) + return -EINVAL; + + par->dc_ops->set_palette_reg(info, regno, red, green, blue); + } + + return 0; +} + +static int gxfb_blank(int blank_mode, struct fb_info *info) +{ + struct geodefb_par *par = info->par; + + return par->vid_ops->blank_display(info, blank_mode); +} + +static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev) +{ + struct geodefb_par *par = info->par; + int fb_len; + int ret; + + ret = pci_enable_device(dev); + if (ret < 0) + return ret; + + ret = pci_request_region(dev, 3, "gxfb (video processor)"); + if (ret < 0) + return ret; + par->vid_regs = ioremap(pci_resource_start(dev, 3), + pci_resource_len(dev, 3)); + if (!par->vid_regs) + return -ENOMEM; + + ret = pci_request_region(dev, 2, "gxfb (display controller)"); + if (ret < 0) + return ret; + par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2)); + if (!par->dc_regs) + return -ENOMEM; + + ret = pci_request_region(dev, 0, "gxfb (framebuffer)"); + if (ret < 0) + return ret; + if ((fb_len = gx_frame_buffer_size()) < 0) + return -ENOMEM; + info->fix.smem_start = pci_resource_start(dev, 0); + info->fix.smem_len = fb_len; + info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); + if (!info->screen_base) + return -ENOMEM; + + dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n", + info->fix.smem_len / 1024, info->fix.smem_start); + + return 0; +} + +static struct fb_ops gxfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = gxfb_check_var, + .fb_set_par = gxfb_set_par, + .fb_setcolreg = gxfb_setcolreg, + .fb_blank = gxfb_blank, + /* No HW acceleration for now. */ + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static struct fb_info * __init gxfb_init_fbinfo(struct device *dev) +{ + struct geodefb_par *par; + struct fb_info *info; + + /* Alloc enough space for the pseudo palette. */ + info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev); + if (!info) + return NULL; + + par = info->par; + + strcpy(info->fix.id, "Geode GX"); + + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.type_aux = 0; + info->fix.xpanstep = 0; + info->fix.ypanstep = 0; + info->fix.ywrapstep = 0; + info->fix.accel = FB_ACCEL_NONE; + + info->var.nonstd = 0; + info->var.activate = FB_ACTIVATE_NOW; + info->var.height = -1; + info->var.width = -1; + info->var.accel_flags = 0; + info->var.vmode = FB_VMODE_NONINTERLACED; + + info->fbops = &gxfb_ops; + info->flags = FBINFO_DEFAULT; + info->node = -1; + + info->pseudo_palette = (void *)par + sizeof(struct geodefb_par); + + info->var.grayscale = 0; + + return info; +} + +static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct geodefb_par *par; + struct fb_info *info; + int ret; + + info = gxfb_init_fbinfo(&pdev->dev); + if (!info) + return -ENOMEM; + par = info->par; + + /* GX display controller and GX video device. */ + par->dc_ops = &gx_dc_ops; + par->vid_ops = &gx_vid_ops; + + if ((ret = gxfb_map_video_memory(info, pdev)) < 0) { + dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n"); + goto err; + } + + ret = fb_find_mode(&info->var, info, mode_option, + gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16); + if (ret == 0 || ret == 4) { + dev_err(&pdev->dev, "could not find valid video mode\n"); + ret = -EINVAL; + goto err; + } + + /* Clear the frame buffer of garbage. */ + memset_io(info->screen_base, 0, info->fix.smem_len); + + gxfb_check_var(&info->var, info); + gxfb_set_par(info); + + if (register_framebuffer(info) < 0) { + ret = -EINVAL; + goto err; + } + pci_set_drvdata(pdev, info); + printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); + return 0; + + err: + if (info->screen_base) { + iounmap(info->screen_base); + pci_release_region(pdev, 0); + } + if (par->vid_regs) { + iounmap(par->vid_regs); + pci_release_region(pdev, 3); + } + if (par->dc_regs) { + iounmap(par->dc_regs); + pci_release_region(pdev, 2); + } + + pci_disable_device(pdev); + + if (info) + framebuffer_release(info); + return ret; +} + +static void gxfb_remove(struct pci_dev *pdev) +{ + struct fb_info *info = pci_get_drvdata(pdev); + struct geodefb_par *par = info->par; + + unregister_framebuffer(info); + + iounmap((void __iomem *)info->screen_base); + pci_release_region(pdev, 0); + + iounmap(par->vid_regs); + pci_release_region(pdev, 3); + + iounmap(par->dc_regs); + pci_release_region(pdev, 2); + + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); + + framebuffer_release(info); +} + +static struct pci_device_id gxfb_id_table[] = { + { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_VIDEO, + PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, + 0xff0000, 0 }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, gxfb_id_table); + +static struct pci_driver gxfb_driver = { + .name = "gxfb", + .id_table = gxfb_id_table, + .probe = gxfb_probe, + .remove = gxfb_remove, +}; + +static int __init gxfb_init(void) +{ +#ifndef MODULE + if (fb_get_options("gxfb", NULL)) + return -ENODEV; +#endif + return pci_register_driver(&gxfb_driver); +} + +static void __exit gxfb_cleanup(void) +{ + pci_unregister_driver(&gxfb_driver); +} + +module_init(gxfb_init); +module_exit(gxfb_cleanup); + +module_param_string(mode, mode_option, sizeof(mode_option), 0444); +MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])"); + +MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX"); +MODULE_LICENSE("GPL"); Index: linux-2.6-working/drivers/video/geode/video_gx.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/video_gx.c 2006-01-31 17:00:54.000000000 +0000 @@ -0,0 +1,217 @@ +/* + * Geode GX video processor device. + * + * Copyright (C) 2006 Arcom Control Systems Ltd. + * + * Portions from AMD's original 2.4 driver: + * Copyright (C) 2004 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/fb.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <asm/delay.h> +#include <asm/msr.h> + +#include "geodefb.h" +#include "video_gx.h" + + +/* + * Tables of register settings for various DOTCLKs. + */ +struct gx_pll_entry { + long pixclock; /* ps */ + u32 sys_rstpll_bits; + u32 dotpll_value; +}; + +#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3) +#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2) +#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3) + +struct gx_pll_entry gx_pll_table_48MHz[] = { + { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */ + { 39721, 0, 0x00000037 }, /* 25.1750 */ + { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */ + { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */ + { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */ + { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */ + { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */ + { 22271, 0, 0x00000063 }, /* 44.9000 */ + { 20202, 0, 0x0000054B }, /* 49.5000 */ + { 20000, 0, 0x0000026E }, /* 50.0000 */ + { 19860, PREMULT2, 0x00000037 }, /* 50.3500 */ + { 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */ + { 17777, 0, 0x00000577 }, /* 56.2500 */ + { 17733, 0, 0x000007F7 }, /* 56.3916 */ + { 17653, 0, 0x0000057B }, /* 56.6444 */ + { 16949, PREMULT2, 0x00000707 }, /* 59.0000 */ + { 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */ + { 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */ + { 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */ + { 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */ + { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */ + { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */ + { 13333, 0, 0x00000052 }, /* 75.0000 */ + { 12698, 0, 0x00000056 }, /* 78.7500 */ + { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */ + { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */ + { 10582, 0, 0x000002D2 }, /* 94.5000 */ + { 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */ + { 10000, PREMULT2, 0x00000036 }, /* 100.0000 */ + { 9259, 0, 0x000007E2 }, /* 108.0000 */ + { 8888, 0, 0x000007F6 }, /* 112.5000 */ + { 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */ + { 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */ + { 6349, 0, 0x00000055 }, /* 157.5000 */ + { 6172, 0, 0x000009C1 }, /* 162.0000 */ + { 5787, PREMULT2, 0x0000002D }, /* 172.798 */ + { 5698, 0, 0x000002C1 }, /* 175.5000 */ + { 5291, 0, 0x000002D1 }, /* 189.0000 */ + { 4938, 0, 0x00000551 }, /* 202.5000 */ + { 4357, 0, 0x0000057D }, /* 229.5000 */ +}; + +static void gx_set_dclk_frequency(struct fb_info *info) +{ + struct gx_pll_entry *pll_table; + int i, best_i; + long min, diff; + u64 dotpll, sys_rstpll; + int timeout = 1000; + + /* FIXME: Handle rev 1 Geode GXs with a 14 MHz reference clock */ + pll_table = gx_pll_table_48MHz; + + /* Search the table for the closest pixclock. */ + best_i = 0; + min = pll_table[0].pixclock - info->var.pixclock; + if (min < 0) min = -min; + for (i = 1; i < ARRAY_SIZE(gx_pll_table_48MHz); i++) { + diff = pll_table[i].pixclock - info->var.pixclock; + if (diff < 0L) diff = -diff; + if (diff < min) { + min = diff; + best_i = i; + } + } + + rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); + rdmsrl(MSR_GLCP_DOTPLL, dotpll); + + /* Program new M, N and P. */ + dotpll &= 0x00000000ffffffffull; + dotpll |= (u64)pll_table[best_i].dotpll_value << 32; + dotpll |= MSR_GLCP_DOTPLL_DOTRESET; + dotpll &= ~MSR_GLCP_DOTPLL_BYPASS; + + wrmsrl(MSR_GLCP_DOTPLL, dotpll); + + /* Program dividers. */ + sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 + | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 + | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 ); + sys_rstpll |= pll_table[best_i].sys_rstpll_bits; + + wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); + + /* Clear reset bit to start PLL. */ + dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET); + wrmsrl(MSR_GLCP_DOTPLL, dotpll); + + /* Wait for LOCK bit. */ + do { + rdmsrl(MSR_GLCP_DOTPLL, dotpll); + } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK)); +} + +static void gx_configure_display(struct fb_info *info) +{ + struct geodefb_par *par = info->par; + u32 dcfg, fp_pm; + + dcfg = readl(par->vid_regs + GX_DCFG); + + /* Clear bits from existing mode. */ + dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK + | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL + | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN); + + /* Set default sync skew. */ + dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT; + + /* Enable hsync and vsync. */ + dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN; + + /* Sync polarities. */ + if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) + dcfg |= GX_DCFG_CRT_HSYNC_POL; + if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) + dcfg |= GX_DCFG_CRT_VSYNC_POL; + + writel(dcfg, par->vid_regs + GX_DCFG); + + /* Power on flat panel. */ + fp_pm = readl(par->vid_regs + GX_FP_PM); + fp_pm |= GX_FP_PM_P; + writel(fp_pm, par->vid_regs + GX_FP_PM); +} + +static int gx_blank_display(struct fb_info *info, int blank_mode) +{ + struct geodefb_par *par = info->par; + u32 dcfg, fp_pm; + int blank, hsync, vsync; + + /* CRT power saving modes. */ + switch (blank_mode) { + case FB_BLANK_UNBLANK: + blank = 0; hsync = 1; vsync = 1; + break; + case FB_BLANK_NORMAL: + blank = 1; hsync = 1; vsync = 1; + break; + case FB_BLANK_VSYNC_SUSPEND: + blank = 1; hsync = 1; vsync = 0; + break; + case FB_BLANK_HSYNC_SUSPEND: + blank = 1; hsync = 0; vsync = 1; + break; + case FB_BLANK_POWERDOWN: + blank = 1; hsync = 0; vsync = 0; + break; + default: + return -EINVAL; + } + dcfg = readl(par->vid_regs + GX_DCFG); + dcfg &= ~(GX_DCFG_DAC_BL_EN + | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN); + if (!blank) + dcfg |= GX_DCFG_DAC_BL_EN; + if (hsync) + dcfg |= GX_DCFG_HSYNC_EN; + if (vsync) + dcfg |= GX_DCFG_VSYNC_EN; + writel(dcfg, par->vid_regs + GX_DCFG); + + /* Power on/off flat panel. */ + fp_pm = readl(par->vid_regs + GX_FP_PM); + if (blank_mode == FB_BLANK_POWERDOWN) + fp_pm &= ~GX_FP_PM_P; + else + fp_pm |= GX_FP_PM_P; + writel(fp_pm, par->vid_regs + GX_FP_PM); + + return 0; +} + +struct geode_vid_ops gx_vid_ops = { + .set_dclk = gx_set_dclk_frequency, + .configure_display = gx_configure_display, + .blank_display = gx_blank_display, +}; Index: linux-2.6-working/drivers/video/geode/video_gx.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/video_gx.h 2006-01-31 16:59:51.000000000 +0000 @@ -0,0 +1,47 @@ +/* + * Geode GX video device + * + * Copyright (C) 2006 Arcom Control Systems Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __VIDEO_GX_H__ +#define __VIDEO_GX_H__ + +extern struct geode_vid_ops gx_vid_ops; + +/* Geode GX video processor registers */ + +#define GX_DCFG 0x0008 +# define GX_DCFG_CRT_EN 0x00000001 +# define GX_DCFG_HSYNC_EN 0x00000002 +# define GX_DCFG_VSYNC_EN 0x00000004 +# define GX_DCFG_DAC_BL_EN 0x00000008 +# define GX_DCFG_CRT_HSYNC_POL 0x00000100 +# define GX_DCFG_CRT_VSYNC_POL 0x00000200 +# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000 +# define GX_DCFG_VG_CK 0x00100000 +# define GX_DCFG_GV_GAM 0x00200000 +# define GX_DCFG_DAC_VREF 0x04000000 + +/* Geode GX flat panel display control registers */ +#define GX_FP_PM 0x410 +# define GX_FP_PM_P 0x01000000 + +/* Geode GX clock control MSRs */ + +#define MSR_GLCP_SYS_RSTPLL 0x4c000014 +# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull) +# define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (0x0000000000000004ull) +# define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (0x0000000000000008ull) + +#define MSR_GLCP_DOTPLL 0x4c000015 +# define MSR_GLCP_DOTPLL_DOTRESET (0x0000000000000001ull) +# define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull) +# define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull) + +#endif /* !__VIDEO_GX_H__ */ -- Richard A. Smith

15 years, 11 months

[LinuxBIOS] IWILL DK8-HTX

by Philipp Degler

Hi greg, coming back on your thread-entry. We would like to get the IWILL DK8-HTX Rev. 1.0 running. Is it possible to use devbios or mtd to access the bios or is the hardware flash programmer the only possible (better) way? The board uses an AMIbios, SVR 2000, AA46 (6827) with the following layout: (x7) , , , , , , , - - - - - - - - - - (x9) - - - - - - - - , , , , , , , What hardware flash programmer would you suggest to get started? thx a lot -- phil On Fri, Dec 09, 2005 at 08:24:34AM -0600, Young, Jeff wrote: > > > I see that the Iwill board dk82s is supported? Does anyone know > > if the dk8-hkt board will work? It > > is interesting because it has an HTK connector on it. > > Do you mean the DK8-HTX ? If so, we ran LinuxBios during initial > bring-up of this board, and I believe we contributed back the changes > we needed for it. > > > -- greg

15 years, 11 months

Re: [LinuxBIOS] tyan s2895 build question

by Ronald G Minnich

Young, Jeff S. wrote: > > > Howdy folks, > > I have been trying to build the tyan s2895 board with gcc > 3.3 on SuSE 10.0 > > It doesn’t build. The loader tries to overlap some sections. I got > around this by > > laying out my own ldscript.lb file (similarly to what Ron wants to do). sorry for this confusion, but what you did and what I am doing are totally unrelated. I am merely proposing to mod the standard LinuxBIOS makefile so that the ldscript.ld is not a sequence of INCLUDE statements, but instead a sequence of ld commands. (Sorry, folks, I have not done this yet) What you did is hack the ldscript.ld script to make things fit. This is going to burn you big time next time you need to run buildtarget -- you will lose those changes. You need to set proper options in your targets/tyan/s2895/Config.lb -- for best results, however, make your own copy of that file. Please see my linux journal web article, wherein the way you size rom images is explained. Sorry you are having trouble, we are looking at this board too and will try to make sure it works. thanks ron

15 years, 12 months

[LinuxBIOS] tyan s2895 build question - again

by Young, Jeff S.

Howdy again, Things are getting better now, so I wanted to keep everyone up to date with what I had To do in order to get as far as I have. System: Tyan s2895 with 2 Dual Core AMDs and 8GB memory BIOS: Using RD1 Bios savior (4mbit) OS: Linux - SuSE 10.0 stock (ie, gcc 4) Build issues: when building, there was an overlapping section. I created the following Section and it fixes it: .rodata. : { *(.rodata.str1.*); } This was placed after .rom section Payload not found. It wasn't clear from the writeup that I had to get the Payload from the web site. Stefan was an immense help in this arena. Maybe the payload directory should be bundled with the snapshots because You need it anyway. Run issues: I build the s2895 bios (fallback and normal) and flash the RD1. I don't know If the fact that the RD1 is 4mbit and the original chip was 8mbit will cause any Problems. The BIOS starts up just fine until the time comes to enable the cache The second time around. (This is after the device enumeration and is in the Initialization stuff.) It hangs right after the code gets cr0 to update it. I get the impression that I am the only one seeing these issues. It seems that everyone else Can just build and run. Is this really true? If you just grab snapshot 2163, untar it, and buildtarget tyan/s2895 Cd tyan/s2895/s2895, and make, it does it just fine??? Any ideas on the cache enable? Thanks, Jeff

15 years, 12 months

Re: [LinuxBIOS] tyan s2895 build question

by Stefan Reinauer

* Young, Jeff S. <Jeff.Young(a)gd-ais.com> [060125 12:21]: > objcopy --gap-fill 0xff -O binary linuxbios linuxbios.strip > > ./buildrom linuxbios.strip linuxbios.rom ../../../../payloads/ > forcedeth--filo_hda2_vga.zelf 0x20000 0x40000 > > ../../../../payloads/forcedeth--filo_hda2_vga.zelf: No such file or directory It does not find your payload image. try using an absolute path in your target configuration file You said you are using gcc 3.3 in suse 10. Did you install this compiler yourself? I use the same distribution, but I have gcc 4 installed. > PS: Can anyone actually build the S2895 without any errors > today? If so, exactly how do you do it. (Note that I have tried > several snapshots from 2007 -> 2163 without success.) It builds fine here, see build log http://snapshots.linuxbios.org/stats/abuild-LinuxBIOSv2-2163.log Your gcc might make things larger than gcc 4 which is why you saw the overlap error. increasing ROM_IMAGE_SIZE(?) should help without changing the LD script. Also I am pretty sure you get your image compiling when you fix your payload path above.. Stefan

15 years, 12 months

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coreboot January 2006