coreboot June 2005

coreboot@coreboot.org

35 participants
100 discussions

[LinuxBIOS] Solaris
by Justin Cormack 06 Aug '05

06 Aug '05

Has anyone looked at what it would take to get Solaris booting under Linuxbios on Opteron? If not I might dig around (there is a modified grub - I think that does some of the init work; one suspects that because of its heritage it is quite BIOS-unencumbered). justin

6 9

Re: [PROPOSAL] enhanced table dumping
by YhLu 19 Jul '05

19 Jul '05

About APIC and ACPI. Some chipset has problems with apic and the workaround must to be used with acpi BIOS. YH

3 2

[LinuxBIOS] Re: Linuxbios is always 421bytes larger than allowed
by Tao Liu 05 Jul '05

05 Jul '05

On 6/27/05, yhlu <yinghailu(a)gmail.com> wrote: > I can not tell if you don't post your MB Config.lb > > To use cache_as_ram you need to update your MB Config.lb and Option.lb > and have your new cache_as_ram_auto.c I referenced tyan s2885 codes to modify my Config.lb, Options.lb and cache_as_ram_auto.c I just tried to build tyan s2885 images form a clean updated tree and met the same problem. Regards, Liu Tao

3 10

[LinuxBIOS] EPIA/EPIA-M Status?
by Jun OKAJIMA 05 Jul '05

05 Jul '05

Hello guys and I hope you tell me what is going on. It worked finally? The snapshot version still has compile error. --- Okajima, Jun. Tokyo, Japan.

5 6

[LinuxBIOS] Local APIC IDs for dual Xeons
by Steve Magnani 01 Jul '05

01 Jul '05

Hi all, I've reached the point where LB is attempting to start the secondary CPU on my custom board. As near as I can tell, LB thinks the secondary CPU isn't responding. This could be a hardware problem, or a LB issue of some sort. CPU 6 would not start! CPU 6 did not initialize! First thing I wanted to check was that LB is using the right APIC ID in the messages it's sending. But I haven't been able to find a good explanation anywhere of how local APIC IDs are assigned in dual-Xeon systems. All Intel says with any certainty is that the power-up sequence includes setting a unique ID for each LAPIC. There is a format to the IDs (i.e. some bits for logical processor, some for socket, some for APIC cluster), but nothing that says (for instance) "One Xeon chip is assigned LAPIC IDs 0 & 1 and the second is assigned LAPIC IDs 6 & 7". Looking over the s2735 config, and anything I found on the Internet, it seems that this is how dual-Xeon boards work. Does anyone know why? Do the addresses come out like this any time you have a dual-Xeon board, and every time you power it up? Or are there some pins that have to be strapped a certain way to end up with these IDs? (Side note, some Xeons support reset-time config of APIC cluster ID - mine don't). The way I'm interpreting the Intel documentation, it looks like the only way to find out a secondary CPU's LAPIC ID is to start it (via an IPI broadcast?) and have it write it somewhere. Thanks, Steve www.digidescorp.com

2 2

[LinuxBIOS] Re: floating irq_table
by yhlu 01 Jul '05

01 Jul '05

just committed the write_pirq_routing_table for s2882 and s2895. for s2882 also move pci_assign_irq from mptable to irq_table.c other x86 irq_table.c all added unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr); } and table.c will call write_pirq_routing_table instead of copy_pirq_routing_table. YH On 6/29/05, Ronald G. Minnich <rminnich(a)lanl.gov> wrote: > > > On Wed, 29 Jun 2005, yhlu wrote: > > > 2. create irq_table while creating the mptable... > > this is better. > > ron >

1 0

RE: [LinuxBIOS] mianboard Config.lb question....
by Ken Fuchs 29 Jun '05

29 Jun '05

YH, please explain your comment. Sincerely, Ken Fuchs <kfuchs(a)winternet.com> > -----Original Message----- > From: linuxbios-bounces(a)openbios.org > [mailto:linuxbios-bounces@openbios.org] On Behalf Of YhLu > Sent: Tuesday, June 28, 2005 19:45 > To: Huang-Jen Wang; linuxbios(a)openbios.org > Subject: RE: [LinuxBIOS] mianboard Config.lb question.... > > > ha ha, my coding is done and waiting for HW to debug..... > > YH > > > -----Original Message----- > > From: Huang-Jen Wang [mailto:huangjen.wang@gmail.com] > > Sent: Tuesday, June 28, 2005 5:37 PM > > To: linuxbios(a)openbios.org > > Subject: [LinuxBIOS] mianboard Config.lb question.... > > > > Dear all, > > I am porting a new mainboard, and its chipset are ServerWorks > > HT1000 and HT2000, in HT1000, it looks like its SMBUS is not > > a pci device. > > Because I can find it device number and function number, I > > have a very serious problem, how do I edit the mainboard > > Config.lbfile.Dose anyone has the same situation before....or > > any idea? > > > > Thanks

2 1

RE: [LinuxBIOS] mianboard Config.lb question....
by YhLu 29 Jun '05

29 Jun '05

ha ha, my coding is done and waiting for HW to debug..... YH > -----Original Message----- > From: Huang-Jen Wang [mailto:huangjen.wang@gmail.com] > Sent: Tuesday, June 28, 2005 5:37 PM > To: linuxbios(a)openbios.org > Subject: [LinuxBIOS] mianboard Config.lb question.... > > Dear all, > I am porting a new mainboard, and its chipset are ServerWorks > HT1000 and HT2000, in HT1000, it looks like its SMBUS is not > a pci device. > Because I can find it device number and function number, I > have a very serious problem, how do I edit the mainboard > Config.lbfile.Dose anyone has the same situation before....or > any idea? > > Thanks > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

1 0

[LinuxBIOS] mianboard Config.lb question....
by Huang-Jen Wang 29 Jun '05

29 Jun '05

Dear all, I am porting a new mainboard, and its chipset are ServerWorks HT1000 and HT2000, in HT1000, it looks like its SMBUS is not a pci device. Because I can find it device number and function number, I have a very serious problem, how do I edit the mainboard Config.lbfile.Dose anyone has the same situation before....or any idea? Thanks

1 0

[LinuxBIOS] Abuild test
by Li-Ta Lo 28 Jun '05

28 Jun '05

Hi, I tried to make as many boards to pass abuild test as possible. Now I have most of them working. The non working boards are in three categories: 1. Known to be broken: technologic/ts5300, via/epia-m 2. Bug in ROMCC: island/aruma, ROMCC complain about something in coherent_ht.c:1543.39: coherent_ht.c:1805.27: auto.c:166.47: 0x88cd720 phi Internal compiler error: Cannot find block dominated by 0x83b8150 3. Bug in Abuild: digitallogic/msm586seg, emulation/qemu-i386, Abuild generates incorrect value (0x-5000) for PAYLOAD_SIZE in Makefile.setting. I can figure out why it generate such a insane thing. 4. Bug in ldscript: tyan/s2880, tyan/s4880, the default ROM_IMAGE_SIZE generated by Abuild is wrong for these boards. The value in target Config.lb is good. 5. CAR WIP: tyan/s2735, YhLu, did you ever get CAR working on this one? make[1]: Entering directory `/tmp/freebios2_test/util/abuild/linuxbios- builds/tyan_s2735/normal' make[1]: *** No rule to make target `/tmp/freebios2_test/src/cpu/intel/car/cache_as_ram.inc', needed by `crt0.s'. Stop. -- Li-Ta Lo <ollie(a)lanl.gov> Los Alamos National Lab

4 4

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot June 2005