coreboot June 2005

coreboot@coreboot.org

35 participants
100 discussions

[LinuxBIOS] How to study the source code...?
by Huang-Jen Wang 21 Jun '05

21 Jun '05

Dear all, Recently I am studying the source code , because I want to try to porting new mainboard later, but it is not easy to realize source code I begin my study from the src/southbridge/amd8111/amd8111.c There are some lines that I can't understand even I have amd8111 datasheet....hope you can tell me 1.devfn = bus_dev->path.u.pci.devfn + (1 << 3); 2.index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8; 3.devfn = (dev->path.u.pci.devfn) & ~7; Thanks advanced... HJ Wang

5 5

[LinuxBIOS] Init wierdness without initrd - kernel 2.6.x
by Hamish Guthrie 21 Jun '05

21 Jun '05

I am wondering if anyone has come across this strange anomoly I am seeing: I have a device with an 8M NAND device, and running short of RAM. I am using SquashFS for the root filesystem. If I use a tftpboot scenario with an initrd, everything functions correctly. I am wanting to get rid of the initrd completely, and use a CramFS root filesystem directly on the NAND flash device. I set everything up correctly and am able to mount the root filesystem and execute /sbin/init directly from the NAND device (using MTD drivers), however, the init process, which is process 1, does not have superuser permissions, however, in the environment with initrd, it does have superuser permissions. Has anyone seen anything like this before - btw, I am using kernel 2.6.11 and the latest MTD drivers etc. TIA Hamish -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.323 / Virus Database: 267.7.9/23 - Release Date: 20.06.2005

1 0

[LinuxBIOS] VIA's KT400 + VT82C8231
by Anton Borisov 20 Jun '05

20 Jun '05

Hello. ASUS A7V8X-X carries northbridge KT400 and southbridge VT82C8231. FlashChip is PMC. flash_and_rom enables writes to flash and freezes system. Any workarounds? -- Sincerely, Anton Borisov

2 1

RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 20 Jun '05

20 Jun '05

make the cache_as_ram_auto for init.o to use printk now, #if CONFIG_USE_INIT printk_debug("linxbios_ram.bin length = %08x\r\n", olen); #else print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n"); #endif there is some space for optimize code for the raminit and ht init in auto ...... The 8 way system get most benefit from the cache-as-ram solution. 1. with romcc, the compile time may need 5 minutes and can not enable vga support 2. win cache as ram and gcc, compile only need 23 seconds. ( the same as four way and two way), and vga support is already enabled. the system with multi CK804 as slaves can get some benefits too. YH > -----Original Message----- > From: YhLu > Sent: Tuesday, June 14, 2005 4:58 PM > To: Ronald G. Minnich; Eric W. Biederman; 'Stefan Reinauer'; Li-Ta Lo > Cc: LinuxBIOS > Subject: RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram. > > AMD cache_as_ram first stage done. > > current status > 1. use gcc to produce auto.inc or init.o 2. it can reboot in > fallback 3. it can reboot from fallback to normal 4. it can > reboot in normal.... > > I'm using auto.c for romcc version > cache_as_ram_auto.c for gcc and via auto.inc version > cache_as_ram_auto.c for gcc and via init.o version > > next stage: > 1. convert cache_as_ram_init.c version. > 2. it will use the printk_debug to substitue print_debug 3. > create compressed init.o version???? could spare 10k bytes.... > > YH > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

3 2

[LinuxBIOS] ROMCC bug
by Steve Magnani 20 Jun '05

20 Jun '05

I've stumbled across a ROMCC bug that results in incorrect code being generated. As near as I can tell, multi-layer "if" statements are at risk of being miscompiled when optimization is enabled. The following program snippet induces the bug when compiled via "romcc -mcpu=p4 -O2" (or -O): /************************************************/ void die(void) { } static void miscompiled_function(unsigned short param) { unsigned int data = __builtin_inl(0); if (data == 0) param = 12; else if (data == 4) param = 42; else die(); __builtin_outl(param, 0); } static void internal_compiler_error(unsigned short param) { unsigned int data = __builtin_inl(0); if (data == 0) param = 12; if (data == 4) param = 42; if ((data != 0) && (data != 4)) die(); __builtin_outl(param, 0); } void main(void) { miscompiled_function(0); // internal_compiler_error(0); } /************************************************/ The assembly output for the miscompiled function is such that when data == 4, param is set to zero, instead of 42. The function 'internal_compiler_error' is logically equivalent to 'miscompiled_function', but attempting to call it results in the following message: bug.c:20.1: bug.c:36.32: warning: edge: bug.c:20.1: bug.c:36.32: warning: 0x9e53b08 copy :0.0: warning: 0x9e542d8 convert <built-in>:1.0: bug.c:21.42: bug.c:36.32: warning: def: <built-in>:1.0: bug.c:21.42: bug.c:36.32: warning: 0x9e53ea8 __inl <built-in>:1.0: bug.c:21.42: bug.c:36.32: 0x9e53ea8 __inl Internal compiler error: live range with already used color %eax Aborted ----------------------------- Steve Magnani www.digidescorp.com

4 6

[LinuxBIOS] EPIA-M Code
by Anton Borisov 20 Jun '05

20 Jun '05

Hello. I've played with EPIA-M tree recently. Interesting facts: 1) I'm always turning to "fallback" image. How LB decides which image to load? I guess this is done with CMOS entry (which one?), but I want boot VIA's AwardBIOS as well as LB (by switching Flash Chips in BIOS Savior). 2) I included file minicom.capped1.bz2. It's a minicom's output. I bet jmp_to_elf_entry() do the wrong staff (src/arch/i386/boot/boot.c) thus not loading payload at all. 3) Moreover. Looking at minicom.capped2.bz2. I've changed jmp_to_elf_entry() a little (put the code from PPC part). Ok, loading FILO now works. But reverting to "Normal" image. And finally, "SMBUS controller not found" because of wrong DEV (DEV = 0xFF). P.S. Booting in cold restart loading "Normal" image. "Normal" image don't boot - it stops at enable_smbus(). Any clues? -- Sincerely, Anton Borisov

2 3

[LinuxBIOS] EPIA-M Code (bz2)
by Anton Borisov 19 Jun '05

19 Jun '05

My apologies. Didn't attach anything :) -- Sincerely, Anton Borisov

1 0

Re: [LinuxBIOS] CN400 support
by Dave Ashley 19 Jun '05

19 Jun '05

>cn400 & vt8237 support is in the works. Is there anything I can do to assist? For example I can supply one or more EPIA-SP 800 mhz boards, we have some of them. Possibly I can make funds available to get developers to focus on the problem. At the very least I can test + offer feedback. I'm trying to come up with alternatives to diving in and doing it myself :^). -Dave

1 0

[LinuxBIOS] Mainboard Config.lb file
by Huang-Jen Wang 19 Jun '05

19 Jun '05

Dear all, Is there a utiltiy to help generate a new mainboard config.lb file or a document described how to write mainboard config.lb file.... thanks HJ Wang

2 1

[LinuxBIOS] A question in auto.c
by Huang-Jen Wang 18 Jun '05

18 Jun '05

Dear all, One part of auto.c, I can't understand , hope you can tell me. In the "static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)" function, how do I get the values of "static const unsigned int rows_4p[4][4]" array , I see an example : /* Link0 of CPU0 to Link0 of CPU1 */ /* Link1 of CPU0 to Link2 of CPU2 */ /* Link2 of CPU1 to Link1 of CPU3 */ /* Link0 of CPU2 to Link0 of CPU3 */ static const unsigned int rows_4p[4][4] = { { 0x00070101, 0x00010202, 0x00030404, 0x00010204 }, { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 }, { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 }, { 0x00010204, 0x00030404, 0x00010202, 0x00070101 } }; but I still can't understand why?

3 4

← Newer
1
2
3
4
5
6
7
8
9
10
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot June 2005