coreboot June 2005

coreboot@coreboot.org

35 participants
100 discussions

RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 13 Jun '05

13 Jun '05

Get into hardwaremain now, and boot_complete is right, but the console_init cause cpu_reset...... YH void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; post_code(0x80); /* displayinit MUST PRECEDE ALL PRINTK! */ console_init();

1 0

RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 13 Jun '05

13 Jun '05

I got the stack in ram works. it when execute the dump_mem(dst, dst+0x100); print_debug("Jumping to LinuxBIOS.\r\n"); __asm__ volatile ( "cli\n\t" "leal _iseg, %edi\n\t" "jmp %edi\n\t" ); in copy_and_run.c, the jmp will cause cpu_reset.... It's strang.... I want to check in the cache_as_ram code, and it can coexist with old romcc code, ( by USE_DCACHE_RAM to switch..) Please let me know if you want to check that code in...... YH LinuxBIOS-1.1.8_s2891_Fallback Mon Jun 13 14:33:38 PDT 2005 starting... (0,1) link=01 (1,0) link=00 02 nodes initialized. SBLink=00 NC node|link=00 NC node|link=02 busn=06 ht reset - LinuxBIOS-1.1.8_s2891_Fallback Mon Jun 13 14:33:38 PDT 2005 starting... (0,1) link=01 (1,0) link=00 02 nodes initialized. SBLink=00 NC node|link=00 NC node|link=02 busn=06 SMBus controller enabled Ram1.00 Ram1.01 Ram2.00 Ram2.01 Ram3 Initializing memory: done Initializing memory: done Ram4 v_esp=000cfe84 Clearing initial memory region: No cache as ram now - Use Ram as Stack now - done Copying LinuxBIOS to ram. src=fffe9c84 dst=00004000 0x00004000: fa 2e 0f 01 15 31 41 00 00 ea 10 40 00 00 10 00 0x00004010: b8 18 00 00 00 8e d8 8e c0 8e d0 8e e0 8e e8 b0 0x00004020: 13 e6 80 8d 3d 00 e0 03 00 b9 00 60 04 00 29 f9 0x00004030: 31 c0 f3 aa 8d 3d 70 54 02 00 b9 e8 dd 03 00 29 0x00004040: f9 74 04 31 c0 f3 aa bc 00 60 04 00 6a 00 6a 00 0x00004050: 55 89 e5 8d 3d 10 ad 01 00 8d 1d 9a 40 00 00 b8 0x00004060: 00 00 10 00 66 89 d8 89 da 66 ba 00 8e 89 47 00 0x00004070: 89 57 04 83 c3 06 83 c7 08 81 ff b0 ad 01 00 75 0x00004080: e3 0f 01 1d 08 ad 01 00 b0 fe e6 80 89 ec e8 a5 0x00004090: 42 00 00 b0 ee e6 80 f4 eb f9 6a 00 6a 00 eb 72 0x000040a0: 6a 00 6a 01 eb 6c 6a 00 6a 02 eb 66 6a 00 6a 03 0x000040b0: eb 60 6a 00 6a 04 eb 5a 6a 00 6a 05 eb 54 6a 00 0x000040c0: 6a 06 eb 4e 6a 00 6a 07 eb 48 6a 08 eb 44 90 90 0x000040d0: 6a 00 6a 09 eb 3c 6a 0a eb 38 90 90 6a 0b eb 32 0x000040e0: 90 90 6a 0c eb 2c 90 90 6a 0d eb 26 90 90 6a 0e 0x000040f0: eb 20 90 90 6a 00 6a 0f eb 18 6a 00 6a 10 eb 12 Jumping to LinuxBIOS. Clearing initial memory region: No cache as ram now - Use Ram as Stack now - done Copying LinuxBIOS to ram. src=fffe9c84 dst=00004000 0x00004000: fa 2e 0f 01 15 31 41 00 00 ea 10 40 00 00 10 00 0x00004010: b8 18 00 00 00 8e d8 8e c0 8e d0 8e e0 8e e8 b0 0x00004020: 13 e6 80 8d 3d 00 e0 03 00 b9 00 60 04 00 29 f9 0x00004030: 31 c0 f3 aa 8d 3d 70 54 02 00 b9 e8 dd 03 00 29 0x00004040: f9 74 04 31 c0 f3 aa bc 00 60 04 00 6a 00 6a 00 0x00004050: 55 89 e5 8d 3d 10 ad 01 00 8d 1d 9a 40 00 00 b8 0x00004060: 00 00 10 00 66 89 d8 89 da 66 ba 00 8e 89 47 00 0x00004070: 89 57 04 83 c3 06 83 c7 08 81 ff b0 ad 01 00 75 0x00004080: e3 0f 01 1d 08 ad 01 00 b0 fe e6 80 89 ec e8 a5 0x00004090: 42 00 00 b0 ee e6 80 f4 eb f9 6a 00 6a 00 eb 72 0x000040a0: 6a 00 6a 01 eb 6c 6a 00 6a 02 eb 66 6a 00 6a 03 0x000040b0: eb 60 6a 00 6a 04 eb 5a 6a 00 6a 05 eb 54 6a 00 0x000040c0: 6a 06 eb 4e 6a 00 6a 07 eb 48 6a 08 eb 44 90 90 0x000040d0: 6a 00 6a 09 eb 3c 6a 0a eb 38 90 90 6a 0b eb 32 0x000040e0: 90 90 6a 0c eb 2c 90 90 6a 0d eb 26 90 90 6a 0e 0x000040f0: eb 20 90 90 6a 00 6a 0f eb 18 6a 00 6a 10 eb 12 Jumping to LinuxBIOS. Clearing initial memory region: No cache as ram now - Use Ram as Stack now - done Copying LinuxBIOS to ram. src=fffe9c84 dst=00004000

1 0

RE: [LinuxBIOS] Tyan S2895 Mptable
by YhLu 11 Jun '05

11 Jun '05

There is no space in MB, the HW engineer didn't connect the second sata out. YH > -----Original Message----- > From: Ronald G. Minnich [mailto:rminnich@lanl.gov] > Sent: Thursday, June 09, 2005 7:53 PM > To: Stephen.Kimball(a)bench.com > Cc: linuxbios(a)openbios.org > Subject: RE: [LinuxBIOS] Tyan S2895 Mptable > > > > On Thu, 9 Jun 2005 Stephen.Kimball(a)bench.com wrote: > > > That's what I said ... it's disabled in the MB Config.lb, but the > > hardware is still there. It's only two lines in the mptable.c. Do > > you expect s2895 users to not need the extra 4 SATA ports? > Why not fix it? > > I'm sure you know how to fix it. > > I'm a little mixed up here, are the connectors and everything there? > > > If I see something that could be improved in the CK804 code, what > > should I do? So far all my suggestions have been dismissed. > > Just hang in there, sorry this is frustrating for you, I > don't have this mobo so can only go on what people say. > > Yh Lu, why is second one disabled? > > ron > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

3 2

RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 10 Jun '05

10 Jun '05

YES LinuxBIOS-1.1.8_s2891_Fallback Fri Jun 10 22:56:51 PDT 2005 starting... (0,1) link=01 (1,0) link=00 02 nodes initialized. SBLink=00 NC node|link=00 NC node|link=02 busn=06 ht reset - LinuxBIOS-1.1.8_s2891_Fallback Fri Jun 10 22:56:51 PDT 2005 starting... (0,1) link=01 (1,0) link=00 02 nodes initialized. SBLink=00 NC node|link=00 NC node|link=02 busn=06 SMBus controller enabled Ram1.00 Ram1.01 Ram2.00 Ram2.01 Ram3 Initializing memory: done Initializing memory: done Ram4 Clearing initial memory region: No cache as ram now - Use Ram as Stack now - > -----Original Message----- > From: Li-Ta Lo [mailto:ollie@lanl.gov] > Sent: Friday, June 10, 2005 10:58 PM > To: yhlu > Cc: Eric W. Biederman; YhLu; Ronald G. Minnich; Stefan > Reinauer; LinuxBIOS > Subject: Re: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram. > > On Fri, 2005-06-10 at 09:26 -0700, yhlu wrote: > > On 09 Jun 2005 23:27:26 -0600, Eric W. Biederman > <ebiederman(a)lnxi.com> > > > Potentially. It might simply be that we are > reprogramming top_mem > > > or the iorrs to define what memory is and messing up the early > > > definition. > > It seems top_mem....I will double check that. > > > > > > The trivial way is to include an asm directive at the beginning. > > > I had actually expected to use something like the init directive > > > that is used on the PPC, and let gcc generate the .o > files. At that > > > point a trivial linker script could place everything in .rom.text > > > and .rom.data if needed. > > That could be next step, in asm make it more easier to debug. > > Current I could not get out of auto.c, I guess i will 1. change > > cache_lbmem in raminit.c to 512k only 2. covert copy or decode in > > crt0.S to c and call directly after ram is initialized. > > 3. use init.o like Ollie wanted....and change to use new > print_debug > > to printk_debug.... > > > > > > p.s. > > > > > > Anyone know why I did not receive a copy of this message on the > > > mailing list? > > Stefan must leave your out of linuxbios list in openbios... > > > > Did you do HT reset after CAR but before DRAM? In my old > implementation, HT reset will mess up CAR. > > -- > Li-Ta Lo <ollie(a)lanl.gov> > Los Alamos National Lab >

1 0

RE: [BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.
by YhLu 10 Jun '05

10 Jun '05

I'm trying to enable the CAR for opteron. 1. create failover.inc and auto.inc with gcc -S 2. change the label in failover.inc from .L --> .fL 3. change section name in failover.inc and auto.c .text --> .rom.text .rodata--> .rom.data .rodata.str...-> .rom.data.str... 4. using following cache_as_ram.inc, and it will be executed after entry.inc at last it will call amd64 in failover.inc or auto.inc 5. current it will die after post code 0x22 I wonder how to make the cpu using the stack in cache.... movl $(CacheBase>>4), %eax movl %eax, %ss is enough? Also how to using gcc parammetor to do 2, and 3.... YH /* cache_as_ram.c */ #define CacheBase 0x60000 #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> /* Save the BIST result */ movl %eax, %ebp CacheAsRam: xorl %eax, %eax # clear %eax and %edx xorl %edx, %edx # movl $fixed_mtrr_msr, %esi enable_fixed_mtrr_dram_modify: movl $SYSCFG_MSR, %ecx rdmsr orl $SYSCFG_MSR_MtrrFixDramModEn, %eax wrmsr /*Clear all MTRRs */ clear_fixed_var_mtrr: lodsl (%esi), %eax testl %eax, %eax jz clear_fixed_var_mtrr_out movl %eax, %ecx xorl %eax, %eax wrmsr jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: /* enable mtrr dram enable */ enable_fixed_var_mtrr_dram: movl $SYSCFG_MSR, %ecx rdmsr orl $(7<<18), %eax wrmsr /* enable caching for 64K using variable mtrr */ movl $0x200, %ecx xorl %edx, %edx movl $(CacheBase | MTRR_TYPE_WRBACK), %eax wrmsr movl $0x201, %ecx movl $0x000000ff, %edx # AMD 40 bit movl $((~((CacheBase + 0x10000) - 1)) | 0x800), %eax wrmsr /* make it to be IO by clearing RD Dram and WR Dram */ movl $IORR0_BASE, %ecx xorl %edx, %edx movl $CacheBase, %eax # bit 3, and bit = 0 mean clear RD ram and ER ram wrmsr movl $IORR0_MASK, %ecx movl $0x000000ff, %edx movl $(~((CacheBase + 0x10000) - 1) | 0x800), %eax wrmsr /* enable cache */ movl %cr0, %eax andl $0x9fffffff,%eax movl %eax, %cr0 intel_chip_post_macro(0x21) /* post 21 */ #if 1 /* we zerod it above */ /* consistency: clear stack */ movl $(CacheBase+0x5000), %edi movl $0x100, %ecx xorl %eax, %eax rep stosl #endif intel_chip_post_macro(0x22) /* post 22 */ // movl $(CacheBase+0x10000-4), %esp movl $(CacheBase>>4), %eax movl %eax, %ss /* Load a different set of data segments */ #if 0 movw $CACHE_RAM_DATA_SEG, %ax movw %ax, %ds movw %ax, %es movw %ax, %ss #endif lout: /* Restore the BIST result */ movl %ebp, %eax jmp _start_init fixed_mtrr_msr: .long 0x250, 0x258, 0x259 .long 0x268, 0x269, 0x26A .long 0x26B, 0x26C, 0x26D .long 0x26E, 0x26F var_mtrr_msr: .long 0x200, 0x201, 0x202, 0x203 .long 0x204, 0x205, 0x206, 0x207 .long 0x208, 0x209, 0x20A, 0x20B .long 0x20C, 0x20D, 0x20E, 0x20F var_iorr_msr: .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 mem_top: .long 0xC001001A, 0xC001001D .long 0x000 /* NULL, end of table */ _start_init: cli intel_chip_post_macro(0x23) /* post 23 */ call amd64_main intel_chip_post_macro(0x24) /* post 24 */

5 11

[LinuxBIOS] TLA Sucks
by Li-Ta Lo 10 Jun '05

10 Jun '05

Ouch, I have messed up the TLA tree many times by trying to commit only the emulator changes. I guess patch-36 to patch-38 are mistakes. I hope I didn't mess the tree too much. BTW, how exactly should I roll back a patch level ? Is the "tla replay --revers" plus "tla sync-tree" the right way to do? Does it undo "tla add"? -- Li-Ta Lo <ollie(a)lanl.gov> Los Alamos National Lab

2 5

RE: [LinuxBIOS] Tyan S2895 Mptable
by YhLu 09 Jun '05

09 Jun '05

After i get cache as ram done. YH > -----Original Message----- > From: Ronald G. Minnich [mailto:rminnich@lanl.gov] > Sent: Thursday, June 09, 2005 8:04 PM > To: YhLu > Cc: Stephen.Kimball(a)bench.com; linuxbios(a)openbios.org > Subject: RE: [LinuxBIOS] Tyan S2895 Mptable > > > > On Thu, 9 Jun 2005, YhLu wrote: > > > There is no space in MB, the HW engineer didn't connect the > second sata out. > > > > ok, then, I guess Stephen's request for a comment in the > config file would be helpful for other users too, Yh Lu, can > you add a comment about that? > > ron >

1 0

RE: [LinuxBIOS] Tyan S2895 Mptable
by Stephen.Kimball＠bench.com 09 Jun '05

09 Jun '05

That's what I said ... it's disabled in the MB Config.lb, but the hardware is still there. It's only two lines in the mptable.c. Do you expect s2895 users to not need the extra 4 SATA ports? Why not fix it? I'm sure you know how to fix it. If I see something that could be improved in the CK804 code, what should I do? So far all my suggestions have been dismissed. Steve -----Original Message----- From: yhlu [mailto:yinghailu@gmail.com] Sent: Thursday, June 09, 2005 1:44 PM To: Kimball, Stephen Cc: linuxbios(a)openbios.org Subject: Re: [LinuxBIOS] Tyan S2895 Mptable the sata in second CK804 is disabled in MB Config.lb, So don't need that. YH On 6/9/05, Stephen.Kimball(a)bench.com <Stephen.Kimball(a)bench.com> wrote: > The Tyan/s2895 mptable.c is missing two entries for SATA. If the Config.lb file turns the SATA devices on the second CK804, this could be a problem. > Ethernet is the only device in the mptable for the second CK804. > > Steve > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

3 2

RE: [LinuxBIOS] Tyan S2895 Mptable
by Stephen.Kimball＠bench.com 09 Jun '05

09 Jun '05

Then maybe the S2895 MB Config.lb shouldn't make it look like the second CK804's SATA devices could be turned on. A comment noting the connector is missing would clear it up. Steve -----Original Message----- but the problem is that S2895 only used SATA on first CK804. And the mptable.c in Mb dir is sth related with MB Configuration. So if you have another MB that enable sata on second ck804, you should create that two entries for sata of it's mptable.c There is no extra space for another four sata connector, also there is some power consumption conern... YH

1 0

Re: [LinuxBIOS] Tyan S2895 Mptable
by Ken Fuchs 09 Jun '05

09 Jun '05

> On 6/9/05, Stephen.Kimball(a)bench.com <Stephen.Kimball(a)bench.com> wrote: > > The Tyan/s2895 mptable.c is missing two entries for SATA. If the > > Config.lb file turns the SATA devices on the second CK804, this > > could be a problem. Ethernet is the only device in the mptable > > for the second CK804. Yh Lu wrote: > the sata in second CK804 is disabled in MB Config.lb, So don't need > that. I think that Stephen has already clearly indicated that there is no problem when SATA for the second CK8-04 is disabled. Does the Tyan S2885 hardware (with COTS BIOS) support SATA on the second CK8-04? If so, the mptable should have the entries required to support SATA on the second CK8-04. Sincerely, Ken Fuchs <kfuchs(a)winternet.com>

2 1

← Newer
1
2
3
4
5
6
7
8
9
10
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot June 2005