coreboot May 2023

coreboot@coreboot.org

10 participants
25 discussions

Tree maintenance and build nodes
by Kyösti Mälkki 06 Aug '23

06 Aug '23

Hi A couple of questions, less technical than usual. Do we have any sample cases of bringing boards back from older branches? I would like to have a branch set up for bringing back some selected AGESA from 4.18 branch. My plan would be to backport features from ToT into said new branch and resolve issues there. Once considered clean enough, it should be a three commit drop (vendorcode, platform, boards) to land on master? Is there someone (corporate) currently funding or hiring personnel with reviews and tree maintenance as a priority? Is there currently anyone actually assigning from their existing resources to put attention to frameworks, while customers' board ports and resolving their issues have tight schedules? Regards, Kyösti Mälkki

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[coreboot - Feature #476] (New) Add option to convert coreboot-inited linear frame buffer to efifb directly
by Bill XIE 02 Aug '23

02 Aug '23

Issue #476 has been reported by Bill XIE. ---------------------------------------- Feature #476: Add option to convert coreboot-inited linear frame buffer to efifb directly https://ticket.coreboot.org/issues/476 * Author: Bill XIE * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-03-30 * Affected OS: GNU/Linux ---------------------------------------- Currently, the linear frame buffer that coreboot initializes should be handled by Linux kernel with dedicated driver "simplefb", but most installer of GNU/Linux distributions only enables "efifb" support, which causes a GNU/Linux installer kexec-ed from a Linux payload running atop simplefb unable to output graphics. Currently, Grub payload could turn coreboot-initialized simplefb to efifb, which can be easily examined from the dmesg log of GNU/Linux booted from Grub payload running atop coreboot-inited linear frame buffer (simplefb). Chainloading a Linux payload with a minimal Grub payload only containing module "linux" and "cbfs" could make the Linux payload running atop efifb, of which GNU/Linux installers can make use, but the related code could be ported to coreboot to make things easier. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #475] (New) mainboard_vbt_filename() in src/mainboard/lenovo/x200/blc.c does not work as intended
by Bill XIE 14 Jul '23

14 Jul '23

Issue #475 has been reported by Bill XIE. ---------------------------------------- Bug #475: mainboard_vbt_filename() in src/mainboard/lenovo/x200/blc.c does not work as intended https://ticket.coreboot.org/issues/475 * Author: Bill XIE * Status: New * Priority: Normal * Assignee: Arthur Heymans * Category: board support * Target version: master * Start date: 2023-03-30 * Affected versions: 4.15, 4.16, 4.17, 4.18, 4.19, master * Affected hardware: x200 ---------------------------------------- Date back to coreboot 4.9, mainboard_vbt_filename() in src/mainboard/lenovo/x200/blc.c calls get_blc_pwm_freq_value(NULL), making the following if condition always falling to the first, not to mention null dereference on strcmp() in get_blc_pwm_freq_value(). In order to determine the correct vbt filename at runtime, edid ascii string should be obtained first. This issue may be distantly related to #474. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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disable efficient-cores or performance-cores in Intel 12th gen processors
by baptx 29 Jun '23

29 Jun '23

Hello, For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_cor…), is it supported by coreboot or Dasharo? Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_perfo…), is it supported also? If some of these disabling option are not available, is there any plan to support them and is there a workaround currently? Thanks.

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Planned maintenance on ticket.coreboot.org on July 1st
by Felix Singer 01 Jun '23

01 Jun '23

I will do some maintenance work on our ticket system on July 1st, which is the upcoming Thursday. The maintenance will * start at 9:00 am UTC+0 * end at 11:00 am UTC+0 (estimated, probably at latest) During this time, the ticket system will be down and/or unusable. I will announce as soon as the work is finished. The maintenance will cover: * Updating the system to the newest stable release * Updating the ticket system to the newest stable release Felix

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[coreboot - Other #492] (New) Evaluate changes need to be made to support Intel's X86S ISA changes
by Martin Roth 28 May '23

28 May '23

Issue #492 has been reported by Martin Roth. ---------------------------------------- Other #492: Evaluate changes need to be made to support Intel's X86S ISA changes https://ticket.coreboot.org/issues/492 * Author: Martin Roth * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-05-28 ---------------------------------------- This past week, Intel announced a plan to boot directly to 64-bit mode[1]. While the timeline released with the announcement does't have any dates for the implementation, due to the huge impact this will have on coreboot, it seems appropriate to start looking at what changes will need to be made to support these changes to the ISA. Changes currently listed: Changes in X86-S ISA consist of: - restricting the CPU to be always in paged mode - removing 32-bit ring 0, as well as vm86 mode. - removing ring 1 and ring 2 - removing 16-bit real and protected modes - removing 16-bit addressing - removing fixed MTRRs - removing user-level I/O and string I/O - removing CR0 Write-Through mode - removing legacy FPU control bits in CR0 - removing ring 3 interrupt flag control - removing obsolete CR access instruction - rearchitecting INIT/SIPI - adding a new mechanism to switch between 4- and 5-level page tables - removing XAPIC and only supporting x2APIC - removing APIC support for 8529 - removing the disabling of NX or SYSCALL or long mode in the EFER MSR - removing the #SS and #NP exceptions - supporting a subset of segmentation architecture, with the following conditions: o restricted to a subset of IDT event delivery o base only for FS, GS o base and limit for GDT, IDT, and TSS o no limit on data or code fetches in 32-bit mode (similar to 64-bit) o no AR or unusable selector checking on CS, DS, ES, FS, and GS on data or code fetches in any mode o restricted support for far call, far return, far jump, and IRET (like FRED). 1: https://web.archive.org/web/20230526070811/https://www.intel.com/content/ww… -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Looking to get Coreboot working on Jasper Lake / N5105 mini PC with 4x Intel 2.5Gbit NICs
by Marcos Scriven 25 May '23

25 May '23

Hello all I'd like to get Coreboot working on a new target device, so I'll follow the 6 steps in the https://www.coreboot.org/FAQ section entitled "Will coreboot work on my machine?" It looks like someone emailed the mailing list about this back in November '22 https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/I5HF…, but if I'm reading the archive correctly, didn't get any responses. Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details. Board Vendor: Board is branded Topton, but the board is from CWWK. CWWK mentions this board on one of their firmware update pages https://www.changwang.com/down/74.html Board Name: MW-JSL2.5G4L CPU: N5105 North Bridge Intel Jasper Lake Host Bridge rev 00 South Bridge Intel Jasper Lake PCH rev 01 • Step 2: Linux "*lspci -tvnn*" output for your system, generated by booting Linux via the original BIOS and runnning lspci. -[0000:00]-+-00.0 Intel Corporation Device [8086:4e24] +-02.0 Intel Corporation Device [8086:4e61] +-04.0 Intel Corporation Device [8086:4e03] +-14.0 Intel Corporation Device [8086:4ded] +-14.2 Intel Corporation Device [8086:4def] +-15.0 Intel Corporation Device [8086:4de8] +-15.2 Intel Corporation Device [8086:4dea] +-16.0 Intel Corporation Device [8086:4de0] +-17.0 Intel Corporation Device [8086:4dd3] +-19.0 Intel Corporation Device [8086:4dc5] +-19.1 Intel Corporation Device [8086:4dc6] +-1c.0-[01]----00.0 Phison Electronics Corporation E12 NVMe Controller [1987:5012] +-1c.4-[02]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.5-[03]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.6-[04]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.7-[05]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1e.0 Intel Corporation Device [8086:4da8] +-1e.3 Intel Corporation Device [8086:4dab] +-1f.0 Intel Corporation Device [8086:4d87] +-1f.3 Intel Corporation Device [8086:4dc8] +-1f.4 Intel Corporation Device [8086:4da3] \-1f.5 Intel Corporation Device [8086:4da4] • Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "*superiotool <https://www.coreboot.org/Superiotool> -dV*"). Output of superiotool -dV (minus all the probing/failed): Found ITE IT8613E (id=0x8613, rev=0xc) at 0x2e Register dump: idx 20 21 22 23 24 2b val 86 13 0c 40 00 48 def 86 13 05 40 00 48 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 01 def 00 03 f8 04 00 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 fa fb fc val 01 0a 30 0a 20 00 80 00 00 00 20 00 f0 00 00 00 def 00 02 90 02 30 09 00 00 00 00 00 NA NA 00 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 01 02 48 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 70 71 72 73 74 b0 b1 b2 b3 b4 b8 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd da db e0 e1 e2 e3 e4 ec f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f7 80 08 d1 00 41 02 0a 10 0a 00 00 01 00 00 00 00 00 00 00 00 00 00 00 c0 03 01 06 80 48 90 00 00 00 00 00 00 b0 44 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 00 00 def 00 f3 00 00 00 01 01 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA 00 00 0e 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 • Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "*flashrom <http://flashrom.org/> -p internal -V*" Direct inspection shows 8-pin 16MB w25q128jv, however, flashrom doesn't seem to include that in the list of Winbond chips it probes for. dmidecode says it's an 8MB ROM, so not sure why the discrepancy • Step 5: URL to the mainboard specifications page (optional). Topton (branded) https://www.aliexpress.com/item/1005004374464011.html Can't find official specs, but there's a pho • Step 6: Any other relevant information you can provide. There's a photo of the board on the left of this BIOS update page https://www-changwang-com.translate.goog/down/74.html?_x_tr_sl=zh-CN&_x_tr_… I've been Googling both "Jasperlake coreboot" and "n5105 coreboot". I see there was news of starting to support this back in January 2020 https://www.phoronix.com/news/Coreboot-JSP-TGL-Razer-ICL Looking at some Coreboot commits, I see a "jasperlake-rvp" target was added, so I simply tried it out. It seems to build fine, but with two warnings: ** WARNING ** ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP. The resulting image won't contain the FSP binaries and will not boot unless they are added later. ** WARNING ** coreboot has been built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. The first warning seems to suggest I can't ignore is (as it won't boot). I thus went looking for an FSP bin for this chip. Unfortunately it doesn't seem to be in the official Intel Github repo, and there's an unanswered issue there looking for it https://github.com/intel/FSP/issues/74 I hope that provides the necessary info to make a start! Thanks Marcos

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Looking to get Coreboot working on Jasper Lake / N5105 mini PC with 4x Intel 2.5Gbit NICs
by Marcos Scriven 23 May '23

23 May '23

(This is a second attempt at posting - not heard back from mods, but so far as I can tell I'm a subscribe of this mail group) Hello all I'd like to get Coreboot working on a new target device, so I'll follow the 6 steps in the https://www.coreboot.org/FAQ section entitled "Will coreboot work on my machine?" It looks like someone emailed the mailing list about this back in November '22: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/I5HF…, but if I'm reading the archive correctly, didn't get any responses. Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details. Board Vendor: Board is branded Topton, but the board is from CWWK. CWWK mentions this board on one of their firmware update pages https://www.changwang.com/down/74.html Board Name: MW-JSL2.5G4L CPU: N5105 North Bridge Intel Jasper Lake Host Bridge rev 00 South Bridge Intel Jasper Lake PCH rev 01 • Step 2: Linux "*lspci -tvnn*" output for your system, generated by booting Linux via the original BIOS and runnning lspci. -[0000:00]-+-00.0 Intel Corporation Device [8086:4e24] +-02.0 Intel Corporation Device [8086:4e61] +-04.0 Intel Corporation Device [8086:4e03] +-14.0 Intel Corporation Device [8086:4ded] +-14.2 Intel Corporation Device [8086:4def] +-15.0 Intel Corporation Device [8086:4de8] +-15.2 Intel Corporation Device [8086:4dea] +-16.0 Intel Corporation Device [8086:4de0] +-17.0 Intel Corporation Device [8086:4dd3] +-19.0 Intel Corporation Device [8086:4dc5] +-19.1 Intel Corporation Device [8086:4dc6] +-1c.0-[01]----00.0 Phison Electronics Corporation E12 NVMe Controller [1987:5012] +-1c.4-[02]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.5-[03]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.6-[04]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.7-[05]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1e.0 Intel Corporation Device [8086:4da8] +-1e.3 Intel Corporation Device [8086:4dab] +-1f.0 Intel Corporation Device [8086:4d87] +-1f.3 Intel Corporation Device [8086:4dc8] +-1f.4 Intel Corporation Device [8086:4da3] \-1f.5 Intel Corporation Device [8086:4da4] • Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "*superiotool <https://www.coreboot.org/Superiotool> -dV*"). Output of superiotool -dV (minus all the probing/failed): Found ITE IT8613E (id=0x8613, rev=0xc) at 0x2e Register dump: idx 20 21 22 23 24 2b val 86 13 0c 40 00 48 def 86 13 05 40 00 48 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 01 def 00 03 f8 04 00 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 fa fb fc val 01 0a 30 0a 20 00 80 00 00 00 20 00 f0 00 00 00 def 00 02 90 02 30 09 00 00 00 00 00 NA NA 00 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 01 02 48 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 70 71 72 73 74 b0 b1 b2 b3 b4 b8 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd da db e0 e1 e2 e3 e4 ec f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f7 80 08 d1 00 41 02 0a 10 0a 00 00 01 00 00 00 00 00 00 00 00 00 00 00 c0 03 01 06 80 48 90 00 00 00 00 00 00 b0 44 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 00 00 def 00 f3 00 00 00 01 01 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA 00 00 0e 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 • Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "*flashrom <http://flashrom.org/> -p internal -V*" Direct inspection shows 8-pin 16MB w25q128jv, however, flashrom doesn't seem to include that in the list of Winbond chips it probes for. dmidecode says it's an 8MB ROM, so not sure why the discrepancy • Step 5: URL to the mainboard specifications page (optional). Topton (branded) https://www.aliexpress.com/item/1005004374464011.html Can't find official specs, but there's a pho • Step 6: Any other relevant information you can provide. There's a photo of the board on the left of this BIOS update page https://www-changwang-com.translate.goog/down/74.html?_x_tr_sl=zh-CN&_x_tr_… I've been Googling both "Jasperlake coreboot" and "n5105 coreboot". I see there was news of starting to support this back in January 2020 https://www.phoronix.com/news/Coreboot-JSP-TGL-Razer-ICL Looking at some Coreboot commits, I see a "jasperlake-rvp" target was added, so I simply tried it out. It seems to build fine, but with two warnings: ** WARNING ** ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP. The resulting image won't contain the FSP binaries and will not boot unless they are added later. ** WARNING ** coreboot has been built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. The first warning seems to suggest I can't ignore is (as it won't boot). I thus went looking for an FSP bin for this chip. Unfortunately it doesn't seem to be in the official Intel Github repo, and there's an unanswered issue there looking for it https://github.com/intel/FSP/issues/74 I hope that provides the necessary info to make a start! Thanks Marcos

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[coreboot - Bug #446] Optiplex 9010 No Post
by Aaron Burton 23 May '23

23 May '23

Issue #446 has been updated by Aaron Burton. Martin Roth wrote in #note-6: > Hi Aaron, any update on this bug? Apologies on the delay, building with APICX2 instead of APIC is what was giving me trouble. Unrelated but I bought a Xeon for it a while back as well but it doesn't post with coreboot, Core i-series chips boot fine. ---------------------------------------- Bug #446: Optiplex 9010 No Post https://ticket.coreboot.org/issues/446#change-1536 * Author: Aaron Burton * Status: New * Priority: Normal * Category: board support * Target version: 4.19 * Start date: 2023-01-09 ---------------------------------------- Working with an Optiplex 9010 SFF, configured and built coreboot as usual against the Optiplex 9010 SFF platform in menuconfig. Left every other setting alone in terms of configuration. Included EC firmware, ME, GBE, IFD blobs from stock firmware into my build. Turns on with fans at normal speed (not full blast), but no keyboard illumination or display output. Using SeaBIOS 1.16.1. Any suggestions as to what may be going on? Thanks. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #446] Optiplex 9010 No Post
by nolan p 22 May '23

22 May '23

Issue #446 has been updated by nolan p. I also have this issue with my 7010 DT when building from `master` with blobs from my stock firmware (SMSC, GBE, ME, IFD). Both `SeaBIOS 1.16.2` and `edk2` from MrChromebox and tianocore do not POST, though it seems like the fans will spin. My config is mostly default otherwise. ---------------------------------------- Bug #446: Optiplex 9010 No Post https://ticket.coreboot.org/issues/446#change-1535 * Author: Aaron Burton * Status: New * Priority: Normal * Category: board support * Target version: 4.19 * Start date: 2023-01-09 ---------------------------------------- Working with an Optiplex 9010 SFF, configured and built coreboot as usual against the Optiplex 9010 SFF platform in menuconfig. Left every other setting alone in terms of configuration. Included EC firmware, ME, GBE, IFD blobs from stock firmware into my build. Turns on with fans at normal speed (not full blast), but no keyboard illumination or display output. Using SeaBIOS 1.16.1. Any suggestions as to what may be going on? Thanks. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot May 2023