Hello,
For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_core...), is it supported by coreboot or Dasharo?
Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_perfor...), is it supported also?
If some of these disabling option are not available, is there any plan to support them and is there a workaround currently?
Thanks.
Hi,
On 1.03.2023 18:58, baptx wrote:
Hello,
For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance (https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_core... https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_cores_to_get_performance/), is it supported by coreboot or Dasharo?
Some people may also want to disable performance-cores instead to save more battery (https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_perfor... https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_performance_cores_to_force_an/), is it supported also?
Intel FSP, which is used to initialize the Intel silicon in coreboot is capable of disabling E and P cores. It is a matter of telling FSP to do it. But I assume you expect a runtime option in the firmware setup, so the answer is no, neither Dasharo nor coreboot supports it at the moment. Currently, the only way to achieve it is a custom coreboot build.
If some of these disabling option are not available, is there any plan to support them and is there a workaround currently?
We have plans from the Dasharo side to include as many options as possible, including core disabling as well. But it will take a lot of time to reach that point without sufficient resources (either financial or developers).
Thanks.
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Best regards,
Hello,
On 3.03.2023 22:33, baptx wrote:
Hello, what is the code we should change to disable E and P cores? Should I report an issue on https://ticket.coreboot.org/projects/coreboot/issues https://ticket.coreboot.org/projects/coreboot/issues or it is already tracked somewhere else? Having an issue open could be useful to give more visibility for people who want to contribute.
Please keep replying to the list if you want people to contribute, otherwise the answers will not reach whole community.
Everything is controlled by FSP UPD all you have to do is to simply disable the cores from the board code you want to build, e.g.:
https://github.com/intel/FSP/blob/master/AlderLakeFspBinPkg/Client/AlderLake... for P cores and https://github.com/intel/FSP/blob/master/AlderLakeFspBinPkg/Client/AlderLake... for E cores in the FSP params functions
Simple as that.
Best regards,
Ok, I missed the list email address since it was not in CC so I could not use the "reply all" feature. So if I understand correctly, we just need to set the value in FspmUpd.h by changing the code to something like "ActiveSmallCoreCount = 0;" before building and flashing coreboot? Are there already some FSP parameters that we can change without reflashing? For example like we can do to disable / enable Intel Management Engine using nvramtool ( https://github.com/system76/firmware-open/blob/master/docs/intel-me.md).
On Mon, 6 Mar 2023 at 11:45, Michał Żygowski michal.zygowski@3mdeb.com wrote:
Hello,
On 3.03.2023 22:33, baptx wrote:
Hello, what is the code we should change to disable E and P cores? Should I report an issue on
https://ticket.coreboot.org/projects/coreboot/issues
https://ticket.coreboot.org/projects/coreboot/issues or it is already
tracked
somewhere else? Having an issue open could be useful to give more
visibility for
people who want to contribute.
Please keep replying to the list if you want people to contribute, otherwise the answers will not reach whole community.
Everything is controlled by FSP UPD all you have to do is to simply disable the cores from the board code you want to build, e.g.:
https://github.com/intel/FSP/blob/master/AlderLakeFspBinPkg/Client/AlderLake... for P cores and
https://github.com/intel/FSP/blob/master/AlderLakeFspBinPkg/Client/AlderLake... for E cores in the FSP params functions
Simple as that.
Best regards,
Michał Żygowski Firmware Engineer GPG: 6B5BA214D21FCEB2 https://3mdeb.com | @3mdeb_com_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
On 8.03.2023 21:09, baptx wrote:
Ok, I missed the list email address since it was not in CC so I could not use the "reply all" feature. So if I understand correctly, we just need to set the value in FspmUpd.h by changing the code to something like "ActiveSmallCoreCount = 0;" before building and flashing coreboot?
Exactly.
Are there already some FSP parameters that we can change without reflashing? For example like we can do to disable / enable Intel Management Engine using nvramtool (https://github.com/system76/firmware-open/blob/master/docs/intel-me.md https://github.com/system76/firmware-open/blob/master/docs/intel-me.md).
No, there aren't. Only hyperthreading and legacy 8254 timer is hooked to CMOS NVRAM currently.
Best regards,
Hi everybody,
I have created a patch which adds Kconfig and runtime options for both of these settings.
https://review.coreboot.org/c/coreboot/+/73790
Let me know your opinion.
Felix
On Thu, 2023-03-02 at 11:27 +0100, Michał Żygowski wrote:
On 1.03.2023 18:58, baptx wrote:
For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficie ncy_cores_to_get_performance/ < https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_effici ency_cores_to_get_performance/>), is it supported by coreboot or Dasharo?
Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disabl e_performance_cores_to_force_an/ < https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disab le_performance_cores_to_force_an/>), is it supported also?
Intel FSP, which is used to initialize the Intel silicon in coreboot is capable of disabling E and P cores. It is a matter of telling FSP to do it. But I assume you expect a runtime option in the firmware setup, so the answer is no, neither Dasharo nor coreboot supports it at the moment. Currently, the only way to achieve it is a custom coreboot build.
Hello, thanks for your contribution. Is there any chance to have the option to disable efficient or performance cores in the next firmware, for example on NovaCustom NV41 laptop? I also saw another way to disable efficient or performance cores without needing to reboot, using taskset but I did not try it yet: https://unix.stackexchange.com/questions/686459/disable-intel-alder-lake-eff... The option in the BIOS could still be useful to have a default configuration.
On Sat, 18 Mar 2023 at 06:01, Felix Singer felixsinger@posteo.net wrote:
Hi everybody,
I have created a patch which adds Kconfig and runtime options for both of these settings.
https://review.coreboot.org/c/coreboot/+/73790
Let me know your opinion.
Felix
On Thu, 2023-03-02 at 11:27 +0100, Michał Żygowski wrote:
On 1.03.2023 18:58, baptx wrote:
For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficie ncy_cores_to_get_performance/ < https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_effici ency_cores_to_get_performance/>), is it supported by coreboot or Dasharo?
Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disabl e_performance_cores_to_force_an/ < https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disab le_performance_cores_to_force_an/>), is it supported also?
Intel FSP, which is used to initialize the Intel silicon in coreboot is capable of disabling E and P cores. It is a matter of telling FSP to do it. But I assume you expect a runtime option in the firmware setup, so the answer is no, neither Dasharo nor coreboot supports it at the moment. Currently, the only way to achieve it is a custom coreboot build.
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Yeah, I think too. I will start with the pre-release process for coreboot 4.21 next week. I will finish this then :)
Felix
On Sat, 2023-06-24 at 18:15 +0200, baptx wrote:
Hello, thanks for your contribution. Is there any chance to have the option to disable efficient or performance cores in the next firmware, for example on NovaCustom NV41 laptop? I also saw another way to disable efficient or performance cores without needing to reboot, using taskset but I did not try it yet: https://unix.stackexchange.com/questions/686459/disable-intel-alder-lake-eff... The option in the BIOS could still be useful to have a default configuration.
-
baptx -
Felix Singer -
Michał Żygowski