https://review.coreboot.org/21774
In case anyone else didn't notice - It is a sandy/ivy system with IOMMU.
This is great and should help get coreboot in to the corporate user world.
Hi Ivan,
On 03.04.2018 20:03, Ivan Ivanov wrote:
> I have noticed that both coreboot and seabios are using the very old
> versions of LZMA SDK.
True. I introduced the lzma code in coreboot (back when it was called
LinuxBIOS) when we were working on OLPC XO-1 support.
> If we will upgrade our LZMA libraries from the
> outdated-by-12-years 4.42 to the current version 18.04 , speed and
> compression ratio should improve and maybe a few bugs will be fixed.
Do you have any numbers for this? An improved compression ratio and
improved speed would be nice indeed, but how does the size of the
decompression code change? If the decompression code grows more than the
size reduction from better compression, it would be a net loss. A
significantly reduced decompression speed would also be a problem.
Decompression speed would have to be measured both for stream
decompression (i.e. the decompressor gets the compressed data in
single-byte or multibyte chunks) as well as full-size decompression
(i.e. the decompressor can access all compressed data at once). We also
have to make sure that stream decompression still works after the change.
> Do you think it should be done, or you are OK with using such an
> outdated version?
A size benefit for the resulting image is a good reason to switch.
Regards,
Carl-Daniel
Dne 30.5.2018 v 16:06 Mike Banon napsal(a):
> Hi Rudolf,
>
> Regarding this part:
> " To check if IMC is active check if PCI 0:14.3 0x40 bit7 set. "
> what command do I need to use to check this?
Try:
sudo setpci -s 14.3 40.b
Despite command name, it will print the value.
Thanks
Rudolf
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Hi @ all,
is there a Coroboot for the Lenovo T410 Laptop?
Greetings
Alex Veek
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A Hardware Enablement devroom will be taking place at FOSDEM this year,
on Sunday 10 December 2017. This newly-created devroom is the result of
3 proposals that were merged together. It is co-organized by several
individuals.
The devroom covers all aspects related to hardware enablement and
support with free software, including aspects related to boot software,
firmwares, drivers and userspace tools and adaptation.
Proposals for talks related to these topics are welcome and can be
submitted until Sunday 26 November 2017 via the pentabarf interface.
Short talks are encouraged over longer ones in order to cover a wide
range of topics.
The announcement for the devroom, that contains all the useful
information, was published at:
https://lists.fosdem.org/pipermail/fosdem/2017-October/002649.html
Cheers and see you at FOSDEM!
--
Paul Kocialkowski, developer of free digital technology and hardware
support
Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/https://git.code.paulk.fr/
Hello Hal,
On 28.05.2018 08:06, Hal Martin wrote:
> Name Offset Type Size Comp
> ...
> cpu_microcode_blob.bin 0x6f00 microcode 0 none
The size looks troubling, I think you really need the correct microcode
binary to get into coreboot. Make 100% sure it matches your SKU.
> Is it expected that ifwitool will not work on the coreboot generated image?
> Or does this indicate I've made a mistake somewhere?
I'm not sure. I'd extract the bios/ifwi region using ifdtool and try to
run ifwitool on that.
Nico
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On 05/03/2018 06:02 PM, ron minnich wrote:
>
>
> On Thu, May 3, 2018 at 1:20 PM Timothy Pearson
> <tpearson(a)raptorengineering.com <mailto:tpearson@raptorengineering.com>>
> wrote:
>
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA256
>
> I think I was being a bit pessimistic / too careful here. We're close
> to getting the docs publicly released, but that doesn't help anyone
> wanting access right now, which is why I mentioned the other route.
> IBM's committed to getting the documentation released, they're just
> making sure that what they release is actually correct for the products
> it covers.
>
> It might make sense to get our "working group" together over the next
> few weeks, by which time the documentation should be available in public
> form.
>
> Are you interested in joining? :-)
>
>
> of course, but not until those docs are freed up.
>
We're getting there. First manual to be released is the processor user
guide. More to follow, including register documentation, in around a week.
Users guide:
https://wiki.raptorcs.com/wiki/File:POWER9_um_OpenPOWER_v20GA_09APR2018_pub…
> Context: I've been trying for 2 years now to get OPAL released under
> dual gpl2 licensing with the current apache2 license, apache2 and gpl2
> are not compatible, so we'd be in a bit of a mess should we use OPAL
> code in coreboot, and it would be easiest if we were able to use some of
> that code.
>
> The first response from IBM was "why do you think you need coreboot?" I
> worked through that, and there was agreement in the end it ought to
> happen, said agreement reached about 2 years ago. Stuff Would Happen, I
> was told. After that, silence.
We've reignited this. It's underway. :-)
> This is pretty much par for the course with Power. In 1990 I spent two
> years getting an agreement that would allow me to .... get more agreements.
We've plowed through this already and are at the action point. For the
most part, just let me know what you need and I'll see if we can get it
published.
> So close doesn't count. Once I see the kind of docs I need to see, not
> requiring a clickwrap, and covering all aspects of every chip on your
> board, I'm in: I'll order a board. Until then, I can't really do much.
Is the NIC an issue? There are several people working on REing the
hardware with some great progress [1][2], but there's really no way to
get Broadcom to ever release official documentation. Everything else on
the libre-friendly non-SAS version either has docs available or we are
close to getting them published.
> Thanks for your efforts on Power!
No problem! We still consider Power the best path forward for powerful
libre systems at this point, getting really tired of the other vendors
actively working against efforts to create open firmware (this includes
SiFive at this point).
Will keep you posted as we get more docs published online, but thought
you and the others here might at least be interested in the users guide.
> ron
>
>
[1] https://wiki.raptorcs.com/wiki/BCM5719
[2] IRC discussions on #talos-workstation
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
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Hello Zvika,
On 31.05.2018 04:39, Zvi Vered wrote:
> The links you provided:
> https://www.coreboot.org/Motherboard_Porting_Guide
> https://www.coreboot.org/Developer_Manual
>
> Does not mention Intel's FSP at all.
there is few FSP documentation maintained by the coreboot community.
But there exists a book [1] and some documentation in our source repo-
sitory [2]. I have to admit, I have read neither of them. I'm used
to read code instead (it is always right and never outdated). So I
can't tell how useful the documentation is.
>
> How FSP is integrated during coreboot porting ?
> src\venorcode\intel contains 2 FSP versions.
There are actually three:
src/vendorcode/fsp1_0/
src/vendorcode/fsp/fsp1_1/
src/vendorcode/fsp/fsp2_0/
For your platform, FSP1.1 and FSP2.0 binaries exist.
> src\soc\intel contains fsp_baytrail, fsp_broadwell_de
These are for different chips. Your E3-1505M v5 is a Skylake processor.
We were used to name the directories explicitly with fsp_ prefix before,
because there were sometimes alternatives to FSP in the tree. That
stopped with Skylake, so src/soc/intel/*lake are all FSP based, too.
src/soc/skylake/ contains the chipset support for your platform.
As mentioned above, two FSP versions exist for Skylake. The original
Skylake FSP was version 1.1 but because its successor Kaby Lake is
mostly compatible, the src/soc/skylake/ code also supports Kaby Lake
and the newer Kaby Lake FSP 2.0 also supports Skylake.
IMO, you should choose which version of FSP you want to use, first.
I would advice you to use FSP 2.0 because that is generally better
supported in coreboot and FSP 1.1 lacks quite some options that you
might need for your mainboard. There are few publicly available blobs
[3,4]. Alas, the public FSP 2.0 binary [4] is not officially validated
for Skylake (but works so far in any case known to us).
If you have a contact to Intel and an NDA, you can ask Intel for a
binary for you processor, of course. I also want to encourage you to
do so because Intel still has to learn that people are interested in
coreboot+FSP.
> Can you please tell what is the best starting point for a XEON board ?
> I think there are no "Intel® XEON® Processor E3-1505M v5" boards in last
> version of coreboot.
> Am I right ?
It depends more on the chipset variant than the processor. I did a
port for a board with the C236 chipset. Yours might have the mobile
version of that chipset which comes very close. My code is not
upstreamed yet. Let me know if you want to peek at it soon.
Other boards that use a similar chipset are:
src/mainboard/intel/kblrvp/ (kblrvp8 variant)
src/mainboard/intel/saddlebrook/
Nico
[1] https://www.apress.com/us/book/9781484200711
Should be free to download.
[2] Documentation/Intel/index.html
[3] https://github.com/IntelFsp/FSP/tree/Skylake
[4] https://github.com/IntelFsp/FSP/tree/Kabylake
Hi All,
The links you provided:
https://www.coreboot.org/Motherboard_Porting_Guidehttps://www.coreboot.org/Developer_Manual
Does not mention Intel's FSP at all.
How FSP is integrated during coreboot porting ?
src\venorcode\intel contains 2 FSP versions.
src\soc\intel contains fsp_baytrail, fsp_broadwell_de
Thank you,
Zvika
On Thu, May 31, 2018 at 2:07 AM Youness Alaoui <
kakaroto(a)kakaroto.homelinux.net> wrote:
> This is the best I can do for you :
>
>
> https://ark.intel.com/products/89608/Intel-Xeon-Processor-E3-1505M-v5-8M-Ca…
>
> Product Collection: Intel® Xeon® Processor E3 v5 Family
> Code Name: Products formerly Skylake
>
> kakaroto@kakaroto:~/coding/purism/coreboot$ git grep SOC_INTEL_SKYLAKE
> | grep mainboard
> src/mainboard/google/chell/Kconfig: select SOC_INTEL_SKYLAKE
> src/mainboard/google/glados/Kconfig: select SOC_INTEL_SKYLAKE
> src/mainboard/google/lars/Kconfig: select SOC_INTEL_SKYLAKE
> src/mainboard/intel/kblrvp/Kconfig: select SOC_INTEL_SKYLAKE
> src/mainboard/intel/kunimitsu/Kconfig: select SOC_INTEL_SKYLAKE
> src/mainboard/intel/saddlebrook/Kconfig: select SOC_INTEL_SKYLAKE
> src/mainboard/purism/librem_skl/Kconfig: select SOC_INTEL_SKYLAKE
>
> I'm going to assume that the skylake Xeon is supported and will work
> (from a coreboot standpoint) just the same as a Core i5 or whatever,
> but it might not be the case. That will be your job to figure the rest
> out.
>
> Good luck,
> Youness.
>
>
> On Wed, May 30, 2018 at 3:35 PM, Zvi Vered <veredz72(a)gmail.com> wrote:
> > Hello Youness,
> >
> > Thank you very much for the detailed information !
> >
> > Can you please tell what is the best starting point for a XEON board ?
> > I think there are no "Intel® XEON® Processor E3-1505M v5" boards in last
> > version of coreboot.
> > Am I right ?
> >
> > Best regards,
> > Zvika
> >
> > On Tue, May 29, 2018 at 9:15 PM Youness Alaoui
> > <kakaroto(a)kakaroto.homelinux.net> wrote:
> >>
> >> Hi,
> >>
> >> I suggest you read the wiki :
> >> https://www.coreboot.org/Developer_Manual and
> >> https://www.coreboot.org/Motherboard_Porting_Guide
> >> I would also suggest maybe (optional) that you read my blog posts
> >> about my own experience porting coreboot to a new motherboard :
> >> https://puri.sm/posts/diving-back-into-coreboot-development/
> >> https://puri.sm/posts/librem-13-coreboot-report-january-12-2017/
> >> https://puri.sm/posts/librem-13-coreboot-report-february-3rd-2017/
> >> https://puri.sm/posts/librem-13-coreboot-report-february-25th-2017/
> >> https://puri.sm/posts/coreboot-on-the-librem-13-v2-part-1/
> >> https://puri.sm/posts/coreboot-on-the-skylake-librems-part-2/
> >>
> >> To answer your specific questions : It depends on your machine, is it
> >> AMD or is it Intel? Is it Ivybridge or Broadwell or Skylake or
> >> Apollolake, etc.. ? Does it have soldered RAM or does it use SODIMMs?
> >> Depending on the CPU architecture, the CPU 'brand' and even the model
> >> of the CPU itself, the port will be done very differently. You'd first
> >> want to find a mainboard that is as close as your current one, and
> >> start modifying that, there isn't "one mainboard to use as base"
> >> because the code, files, etc.. are almost unique depending on the
> >> CPU/northbridge/southbridge model, so use the closest one as your
> >> base.
> >> As far as I know, the file board_info.txt is just information about
> >> the board, it's not getting used by coreboot, it's more of an
> >> indication for developers.
> >> As for the other files, it will depend once again on your board. I'd
> >> say Kconfig and devicetree.cb are mandatory, the rest may or may not
> >> be mandatory depending on your hardware. The cmos.layout for example
> >> isn't mandatory, but you'd probably need it if you enable CMOS support
> >> in your KConfig, The 'spd' files containing the RAM's SPD EEPROM
> >> information are mandatory only if your board has soldered RAM (common
> >> in laptops but not in desktops), but they are not needed (and actually
> >> can't be provided) if the motherboard has SODIMM slots instead. So it
> >> all depends. Your best bet is to look at what's there and see if you
> >> need it or not and if you do, understand what it's for and what needs
> >> to be changed in order to match your board.
> >> Don't forget that before you get your board to boot with coreboot, you
> >> will probably have to flash it and brick your board 100 times, so make
> >> sure you have a backup of your original ROM copied somewhere safe and
> >> that you have the hardware to re-program the SPI flash externally (and
> >> test that it works), before you attempt to flash it.
> >> Also, make sure you are patient, and ready to learn!
> >>
> >> Good luck!
> >> Youness.
> >>
> >>
> >> On Mon, May 28, 2018 at 10:31 PM, Zvi Vered <veredz72(a)gmail.com> wrote:
> >> > Hello,
> >> >
> >> > I have to port coreboot to a new "Mainboard" not listed in menuconfig.
> >> > Is there a basic "Mainboard" I should use as a starting point that
> will
> >> > be
> >> > copied to my board ?
> >> >
> >> > The file board_info.txt contains few parameters.
> >> > How can I know the meaning of each parameter and its possible values ?
> >> >
> >> > The board kontron/kt690 for example contains few files like:
> >> > cmos.layout,
> >> > devicetree.cb, etc
> >> > Are all those files mandatory ?
> >> > Is there a list of mandatory files or routines required in order to
> port
> >> > a
> >> > board ?
> >> >
> >> > Your help is highly appreciated.
> >> > Best regards,
> >> > Zvika
> >> >
> >> > --
> >> > coreboot mailing list: coreboot(a)coreboot.org
> >> > https://mail.coreboot.org/mailman/listinfo/coreboot
>
This is the best I can do for you :
https://ark.intel.com/products/89608/Intel-Xeon-Processor-E3-1505M-v5-8M-Ca…
Product Collection: Intel® Xeon® Processor E3 v5 Family
Code Name: Products formerly Skylake
kakaroto@kakaroto:~/coding/purism/coreboot$ git grep SOC_INTEL_SKYLAKE
| grep mainboard
src/mainboard/google/chell/Kconfig: select SOC_INTEL_SKYLAKE
src/mainboard/google/glados/Kconfig: select SOC_INTEL_SKYLAKE
src/mainboard/google/lars/Kconfig: select SOC_INTEL_SKYLAKE
src/mainboard/intel/kblrvp/Kconfig: select SOC_INTEL_SKYLAKE
src/mainboard/intel/kunimitsu/Kconfig: select SOC_INTEL_SKYLAKE
src/mainboard/intel/saddlebrook/Kconfig: select SOC_INTEL_SKYLAKE
src/mainboard/purism/librem_skl/Kconfig: select SOC_INTEL_SKYLAKE
I'm going to assume that the skylake Xeon is supported and will work
(from a coreboot standpoint) just the same as a Core i5 or whatever,
but it might not be the case. That will be your job to figure the rest
out.
Good luck,
Youness.
On Wed, May 30, 2018 at 3:35 PM, Zvi Vered <veredz72(a)gmail.com> wrote:
> Hello Youness,
>
> Thank you very much for the detailed information !
>
> Can you please tell what is the best starting point for a XEON board ?
> I think there are no "Intel® XEON® Processor E3-1505M v5" boards in last
> version of coreboot.
> Am I right ?
>
> Best regards,
> Zvika
>
> On Tue, May 29, 2018 at 9:15 PM Youness Alaoui
> <kakaroto(a)kakaroto.homelinux.net> wrote:
>>
>> Hi,
>>
>> I suggest you read the wiki :
>> https://www.coreboot.org/Developer_Manual and
>> https://www.coreboot.org/Motherboard_Porting_Guide
>> I would also suggest maybe (optional) that you read my blog posts
>> about my own experience porting coreboot to a new motherboard :
>> https://puri.sm/posts/diving-back-into-coreboot-development/
>> https://puri.sm/posts/librem-13-coreboot-report-january-12-2017/
>> https://puri.sm/posts/librem-13-coreboot-report-february-3rd-2017/
>> https://puri.sm/posts/librem-13-coreboot-report-february-25th-2017/
>> https://puri.sm/posts/coreboot-on-the-librem-13-v2-part-1/
>> https://puri.sm/posts/coreboot-on-the-skylake-librems-part-2/
>>
>> To answer your specific questions : It depends on your machine, is it
>> AMD or is it Intel? Is it Ivybridge or Broadwell or Skylake or
>> Apollolake, etc.. ? Does it have soldered RAM or does it use SODIMMs?
>> Depending on the CPU architecture, the CPU 'brand' and even the model
>> of the CPU itself, the port will be done very differently. You'd first
>> want to find a mainboard that is as close as your current one, and
>> start modifying that, there isn't "one mainboard to use as base"
>> because the code, files, etc.. are almost unique depending on the
>> CPU/northbridge/southbridge model, so use the closest one as your
>> base.
>> As far as I know, the file board_info.txt is just information about
>> the board, it's not getting used by coreboot, it's more of an
>> indication for developers.
>> As for the other files, it will depend once again on your board. I'd
>> say Kconfig and devicetree.cb are mandatory, the rest may or may not
>> be mandatory depending on your hardware. The cmos.layout for example
>> isn't mandatory, but you'd probably need it if you enable CMOS support
>> in your KConfig, The 'spd' files containing the RAM's SPD EEPROM
>> information are mandatory only if your board has soldered RAM (common
>> in laptops but not in desktops), but they are not needed (and actually
>> can't be provided) if the motherboard has SODIMM slots instead. So it
>> all depends. Your best bet is to look at what's there and see if you
>> need it or not and if you do, understand what it's for and what needs
>> to be changed in order to match your board.
>> Don't forget that before you get your board to boot with coreboot, you
>> will probably have to flash it and brick your board 100 times, so make
>> sure you have a backup of your original ROM copied somewhere safe and
>> that you have the hardware to re-program the SPI flash externally (and
>> test that it works), before you attempt to flash it.
>> Also, make sure you are patient, and ready to learn!
>>
>> Good luck!
>> Youness.
>>
>>
>> On Mon, May 28, 2018 at 10:31 PM, Zvi Vered <veredz72(a)gmail.com> wrote:
>> > Hello,
>> >
>> > I have to port coreboot to a new "Mainboard" not listed in menuconfig.
>> > Is there a basic "Mainboard" I should use as a starting point that will
>> > be
>> > copied to my board ?
>> >
>> > The file board_info.txt contains few parameters.
>> > How can I know the meaning of each parameter and its possible values ?
>> >
>> > The board kontron/kt690 for example contains few files like:
>> > cmos.layout,
>> > devicetree.cb, etc
>> > Are all those files mandatory ?
>> > Is there a list of mandatory files or routines required in order to port
>> > a
>> > board ?
>> >
>> > Your help is highly appreciated.
>> > Best regards,
>> > Zvika
>> >
>> > --
>> > coreboot mailing list: coreboot(a)coreboot.org
>> > https://mail.coreboot.org/mailman/listinfo/coreboot
