coreboot October 2012

coreboot@coreboot.org

34 participants
312 discussions

by coreboot

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

6 years, 6 months

EHCI debug port finder

by Carl-Daniel Hailfinger

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

7 years

Dual SPI Flash adapter attempt 2.0

by Oliver Schinagl

Hi list(s), Here's my second attempt at routing the previously mailed png of my schema. It was a lot trickier to route then my previous version, but I think it worked out! As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1 should be 10k or ideally 100k, as Peter mentioned earlier. Hopefully there's no obvious mistakes and can start working on alternative layouts (so it is insert-able in different angles). DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow. That said, DRC check passes when I set the copper width/distance to 7mil's instead of the current 8 mils. I'm planning on having these PCB's manufactured by Seeed studio and their minimal width is much smaller. Minimum trace width: 6mil Minimum trace/vias/pads space : 6mil Minimum silkscreen width : 4mil Minimum silkscreen text size : 32mil I've used a grid size of 10mil and distances of 8 mils, as I didn't want to rely on the minimum of seed. The silkscreen I positioned using a grid size of 5 mil's however. Not sure what they mean with a 'minimum silkscreen text size' however. Anyhow, feedback greatly appreciated, so I can start working on alternative layouts :)

7 years, 3 months

#186: 3com 3c905tx / gpxe boot problem

by coreboot

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: just because) novice in the field, I encountered some problems with netbooting with coreboot. Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE} respectively. NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy slow! Although loading, the kernel is never able to start itself. Same kernel on HDU is no problem at all (GRUB2) Note: the gpxe-image is on the nic, coreboot payload is seabios. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186> coreboot <http://www.coreboot.org/>

7 years, 5 months

unsupported mb questions (amd fam10h)

by Roman Elshin

I try to get coreboot working with asrock 880g pro3 board. First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333? Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible to boot from sata. Are sb850 supported by coreboot? ----------------------------------------------------------------------- diff -urN a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c --- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14 21:49:54.000000000 +0400 @@ -94,7 +94,10 @@ rev = REV_SB800_A11; } else if (rev_id == 0x41) { rev = REV_SB800_A12; - } else { + } else if (rev_id == 0x42) { + rev = REV_SB800_A13; + } + else { die("It is not SB800 or SB810\r\n"); } diff -urN a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h --- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000 +0400 @@ -48,7 +48,7 @@ #define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 - +#define REV_SB800_A13 0x13 #ifdef __PRE_RAM__ void sb800_lpc_port80(void); -------------------------------------------------------------------------

7 years, 11 months

New patch to review: 49493f5 T60: add volume CMOS setting

by gerrit＠coreboot.org

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12 -gerrit

8 years, 4 months

Re: [coreboot] [SeaBIOS] USB Problems geode lx800

by Kevin O'Connor

On Thu, Oct 18, 2012 at 12:25:58PM +0200, Christian Gmeiner wrote: > 2012/10/17 Kevin O'Connor <kevin(a)koconnor.net>: > > The controller is supposed to update the toggle bit in the qh. The > > same qh is used for all transfers, so it should already be up to date > > between transfers. It is possible something subtle is going on here. > > USB is finally working :) http://dpaste.com/815054/ Great! Can you post the EHCI patch you used to make this work? Thanks, -Kevin

8 years, 7 months

F2A85-V PRO as good target?

by Rudolf Marek

Hi all, I think it is time to finally get new FM2 board! I have in mind some version of the F2A85-V PRO. Best would be to coordinate bit the efforts and choose some board which is long term supported. Also, everything costs quite some money and it would be nice if maybe someone already owns it to get some lspci/flash dumps etc in advance. So far I have learned: 1) it has socketed BIOS 2) there seems to be some hw way how to unbrick that, but question is if it will accept our images USB BIOS Flashback - Easy, worry-free USB BIOS I suspect it is done by some 8051 controller, possibly some of those chips: http://detail.zol.com.cn/picture_index_975/index9747187_0_p336189.shtml Looks like independent of any other chips, it could be cool feature for coreboot users. 3) it has serial port 4) it has NCT6779D which has no public datasheet 5) I was able to decompress the EFI firmware (skip first 2KB) with the bios_extract with some enhancements for compressed volumes. I think I got this from Patrick? I found there at least one 8051 firmware which looks like it is providing the EPU function. I suspect this runs inside southbridge, because the usual AMD signature is wiped with "xxxxxxxx" at 0x2000 ;) I think this can be a PITA but I dont know if it will work without this. Or if we would have to provide a way how to include that in the resulting image. I did not find a decompressed version of this fw. I suspect it lives iniside the flash after first flashing or so... 5) some of firmware files are quite funny and include cryptographic keys for microsoft and canonical also, it seems the "secure part" of the image updater is packed with UPX and this is then used by flashers (maybe extra other SMI layer is involved I dont know) (look for ASEX_update_bios_firmware does the trick) All in all, I'm nearly convinced I will try to do it, but of course it is hard not to imagine some showstoper and all the money invested to new coreboot hw as wasted. Thanks Rudolf

8 years, 7 months

Installing uboot/qemu to Chromebook

by Reese Chappuis

Ron Minnich requested that we move this conversation<https://plus.google.com/u/0/102325349472273329333/posts/Ly6n56R7Ltd> to here. I'm looking to install qemu on my Chromebook to run Arch Linux in a vm. -- Reese Chappuis

8 years, 7 months

qemu boot error: Unexpected Exception: 6 @ 10:00109910 - Halting

by WANG Siyuan

hi, I want to boot qemu with coreboot. the disk image use grub to load linux. but I got errors in write_coreboot_table() how to deal with it? the following msg is the wrong log. the attachment is the whole log. thank you! SMBIOS tables: 370 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 63e0 New low_table_end: 0x00000528 Now going to write high coreboot table at 0x7ffe1c00 rom_table_end = 0x7ffe1c00 Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0x7ffe1c00 to 0x7fff0000 Unexpected Exception: 6 @ 10:00109910 - Halting Code: 0 eflags: 00010006 eax: 7ffe1c18 ebx: 00010000 ecx: 00000014 edx: 00000000 edi: 7ffe1c00 esi: 0011ff10 ebp: 00000005 esp: 0011feb4 001098d0: ec 7c 89 44 24 14 8b 40 001098d8: 04 8d 74 24 5c c7 44 24 001098e0: 18 00 00 00 00 89 74 24 001098e8: 3c 89 44 24 10 83 e8 08 001098f0: f7 f1 89 44 24 34 89 44 001098f8: 24 38 8b 44 24 14 89 44 00109900: 24 30 e9 a5 00 00 00 6b 00109908: 44 24 18 14 03 44 24 14 00109910: 66 0f 6e 40 0c 66 0f d6 00109918: 44 24 20 8b 54 24 20 8d 00109920: 58 08 8b 40 08 89 5c 24 00109928: 28 8b 5c 24 18 89 d1 31 00109930: d2 89 4c 24 24 8b 4c 24 00109938: 30 89 54 24 20 31 d2 01 00109940: 44 24 20 11 54 24 24 83 00109948: c1 08 89 4c 24 2c 6b cb -- WANG Siyuan

8 years, 7 months

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coreboot October 2012