coreboot January 2018

coreboot@coreboot.org

60 participants
155 discussions

Optiplex 790 now has preliminary support by coreboot

by Taiidan＠gmx.com

https://review.coreboot.org/21774 In case anyone else didn't notice - It is a sandy/ivy system with IOMMU. This is great and should help get coreboot in to the corporate user world.

2 years

Lenovo T410 Coreboot

by A. Veek

3 years, 1 month

FOSDEM Hardware Enablement Devroom

by Paul Kocialkowski

A Hardware Enablement devroom will be taking place at FOSDEM this year, on Sunday 10 December 2017. This newly-created devroom is the result of 3 proposals that were merged together. It is co-organized by several individuals. The devroom covers all aspects related to hardware enablement and support with free software, including aspects related to boot software, firmwares, drivers and userspace tools and adaptation. Proposals for talks related to these topics are welcome and can be submitted until Sunday 26 November 2017 via the pentabarf interface. Short talks are encouraged over longer ones in order to cover a wide range of topics. The announcement for the devroom, that contains all the useful information, was published at: https://lists.fosdem.org/pipermail/fosdem/2017-October/002649.html Cheers and see you at FOSDEM! -- Paul Kocialkowski, developer of free digital technology and hardware support Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

3 years, 1 month

Re: [coreboot] Server systems shipped with coreboot

by Piotr Kubaj

There's no "pure coreboot" systems. You need some payload. Also, while Talos is truly awesome, the OP asked about coreboot specifically and Talos doesn't run coreboot :) At the moment, the best coreboot-supported server motherboard is ASUS KGPE-D16. You can also get libre BMC with OpenBMC port for it. If you just want a libre motherboard, Talos is the best you can get. On 18-01-17 12:00:01, coreboot-request(a)coreboot.org wrote: >Message: 2 >Date: Tue, 16 Jan 2018 19:29:18 +0100 >From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> >To: Coreboot <coreboot(a)coreboot.org> >Subject: [coreboot] Server systems shipped with coreboot >Message-ID: <d5d6d8ee-77ee-4232-a89a-e5158140b065(a)gmx.net> >Content-Type: text/plain; charset=UTF-8 > >Hi, > >does anyone have a list of server systems which are shipped with >coreboot? I'm interested in coreboot+UEFI systems, coreboot+Linux >systems, coreboot+SeaBIOS systems, pure coreboot systems. > >At 34C3 I was told by someone that a major vendor has been shipping >servers with coreboot without announcing this, and I unfortunately >neither remember the server model nor who told me about this. If said >person could remind contact me, I'd be thankful. > >Regards, >Carl-Daniel > > > >------------------------------ > >Message: 3 >Date: Wed, 17 Jan 2018 00:28:23 +0300 >From: Mike Banon <mikebdp2(a)gmail.com> >To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>, > coreboot(a)coreboot.org >Subject: Re: [coreboot] Server systems shipped with coreboot >Message-ID: > <CAK7947nVZptQEhiRzfPQpt_KqVFERXzFNrppeb_NTVhEGxSLQQ(a)mail.gmail.com> >Content-Type: text/plain; charset="UTF-8" > >Hi friend ! I just googled "coreboot servers" and found this: > >https://store.vikings.net/the-server-1u , and >https://www.siliconmechanics.com/i7045/opteron-server.php >(Installation of coreboot is available with certain configurations; >contact Sales for details.) > >And, of course, Talos II POWER9 servers which are already available >for pre-orders. >They are the future of libre server computing : >https://www.raptorcs.com/TALOSII/prerelease.php > >So basically there are two options: >1) use one of a few coreboot-supported boards with AMD Opterons (which >are also a bit outdated) >you can even build such a server by yourself, just get the supported >hardware and flash coreboot to it >2) preorder Talos II and wait for shiny new server to come ;) > >Mike > > >On Tue, Jan 16, 2018 at 9:29 PM, Carl-Daniel Hailfinger ><c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Hi, >> >> does anyone have a list of server systems which are shipped with >> coreboot? I'm interested in coreboot+UEFI systems, coreboot+Linux >> systems, coreboot+SeaBIOS systems, pure coreboot systems. >> >> At 34C3 I was told by someone that a major vendor has been shipping >> servers with coreboot without announcing this, and I unfortunately >> neither remember the server model nor who told me about this. If said >> person could remind contact me, I'd be thankful. >> >> Regards, >> Carl-Daniel >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot > > > >------------------------------ > >Subject: Digest Footer > >_______________________________________________ >coreboot mailing list >coreboot(a)coreboot.org >https://mail.coreboot.org/mailman/listinfo/coreboot > >------------------------------ > >End of coreboot Digest, Vol 155, Issue 24 >***************************************** > >-- >This message has been scanned for viruses and >dangerous content by MailScanner, and is >believed to be clean. >

3 years, 10 months

Re: [coreboot] Server systems shipped with coreboot

by Timothy Pearson

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 4 cores, SMT4. There's an 8-core available for $190 more, and AFAIK there are plans to start offering an 18-core server chip very shortly. These are the OpenPOWER machines, so there is hardware virtualization support (including I/O passthrough) that works well with kvm and QEMU. I haven't really heard anything referred to as "LPAR" on these newer POWER8/POWER9 machines outside of legacy documents. On 01/23/2018 12:47 PM, ron minnich wrote: > how many cores is that? Does it come with LPAR? > > On Mon, Jan 22, 2018 at 9:48 PM Taiidan(a)gmx.com <mailto:Taiidan@gmx.com> > <Taiidan(a)gmx.com <mailto:Taiidan@gmx.com>> wrote: > > In case anyone wants to know the (non-coreboot) libre firmware TALOS 2 > single CPU/board combo is now only 2.5K. > > I still can't figure out how they managed to make it so affordable, this > is seriously great. > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://mail.coreboot.org/mailman/listinfo/coreboot > - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJaZ4U2AAoJEK+E3vEXDOFbBUEIAKxL6cD2L27yZh63OhM0TD8h BZD2r0nYF/NLfGi50KuMZPNzb2lpzgLHc06ZHZmJBU0sFUbTdI3WrYibDPtY4lva 1uG3gedN2u+sUCzTKrLILOyrstlJ2lQ4+8jxyO8PncK9Zx3LtgbSlGVGq+pvxsXI Ac8Yqm+de6Is8aaAHMMzaT9UNxcjXCAs/zZm3iWcPkA2B0CVVUoKnsFuhtGG1cGd j4bukGJrojkUMEFxIG93qphcurdP2AjuvOaUdZVuoC0uxdVL2az77SgRUH8Vmxdd SFhAzG7j4LsqGMwiZBkubBZpSMPj6kPyRQUIxwwAk/vRLpOxoPdaEbrI/9wyIaM= =PFaf -----END PGP SIGNATURE-----

3 years, 10 months

Microcode updates for slightly older intel CPU's re: meltdown/spectre

by Taiidan＠gmx.com

I am curious of any intel insiders know if there will be microcode updates released for older intel CPU's (ex: sandy/ivybridge) and failing that, what can be done in regards to securing them from meltdown/spectre. I believe this is a relevant coreboot topic considering how many coreboot boards have these and older CPU's....without a fix there will be only one coreboot compatible laptop with open source hardware initiation that is remotely secure (lenovo g505s as has a pre-PSP AMD CPU) and theoretically owner controllable (as the previous C2D/C2Q's such as the X200 are now permanently insecure without intervention from intel apparently) At this point even a massive performance loss is better than having to throw out so much now-useless hardware.

3 years, 10 months

[PATCH 0/5] coreboot table bus and framebuffer driver

by Samuel Holland

On many systems, coreboot[1] firmware can initialize graphics hardware and set up a high-resolution linear framebuffer. It exports information about this framebuffer, along with various other information, in a table discoverable via ACPI or a device tree. coreboot also supports booting Linux directly from flash as a "payload". Projects such as Heads[2], u-root[3], and petitboot[4] provide a minimal userland that can then be used to chainload (via kexec) into a full Linux system loaded from disk or over the network. Fitting even a minimal Linux system on an SPI flash chip is challenging. Reusing the framebuffer setup from coreboot provides an enormous benefit to these projects by allowing them to omit full graphics drivers from their kernel builds. It also speeds up boot times by avoiding duplicated effort, and because coreboot's graphics initialization is often much faster than the Linux driver. Patch 1 of this series expands coreboot table support into an enumerable bus that devices can hang off of. Patches 2-3 convert the existing drivers to use the new bus structure instead of ad-hoc platform devices, and patch 4 removes the old coreboot_table_find function. Finally, patch 5 adds a new driver for the coreboot-initialized framebuffer. It improves on earlier work[5] by being architecture- independent and not needing to scan through low memory. This patchset has been tested on a Lenovo ThinkPad X220, and earlier versions of these patches have been tested by various members of the coreboot community on other hardware. [1]: https://www.coreboot.org/Welcome_to_coreboot [2]: https://github.com/osresearch/heads [3]: https://github.com/u-root/u-root [4]: https://www.kernel.org/pub/linux/kernel/people/geoff/petitboot/petitboot.ht… [5]: https://mail.coreboot.org/pipermail/coreboot/2014-September/078551.html Samuel Holland (5): firmware: coreboot: Expose the coreboot table as a bus firmware: memconsole: Probe via coreboot bus firmware: vpd: Probe via coreboot bus firmware: coreboot: Remove unused coreboot_table_find firmware: coreboot: Add coreboot framebuffer driver drivers/firmware/google/Kconfig | 8 ++ drivers/firmware/google/Makefile | 1 + drivers/firmware/google/coreboot_table-acpi.c | 2 +- drivers/firmware/google/coreboot_table-of.c | 2 +- drivers/firmware/google/coreboot_table.c | 130 ++++++++++++++++++------- drivers/firmware/google/coreboot_table.h | 72 +++++++++++--- drivers/firmware/google/framebuffer-coreboot.c | 115 ++++++++++++++++++++++ drivers/firmware/google/memconsole-coreboot.c | 49 ++++------ drivers/firmware/google/vpd.c | 43 +++----- 9 files changed, 313 insertions(+), 109 deletions(-) create mode 100644 drivers/firmware/google/framebuffer-coreboot.c -- 2.13.6

3 years, 10 months

Re: [coreboot] [off topic] Opteron CPU missing chips on the bottom

by Daniel Kulesz

Hi Taiidan, > I purchased a used g34 opteron off of fleabay (sold as working with no > mention of this) and I noticed that it is missing some of the bits on > the bottom and that most of them are crooked, I haven't tried it in my > system yet and I am wondering should return it? or if there isn't any > much risk of it damaging my (expensive kgpe-d16) motherboard and I > should see if it works? > I got it for half the usual price....guess I should have asked for photos. > > I noticed many CPU's sold on ebay have this issue (in those cases they > mentioned it) but I can't understand how it happens, for instance I > noticed a 6386 for sale where they mentioned that it was missing a few > and because of that it doesn't work in a dual socket configuration. I have a few Opterons which have this issue and it seems to pretty common. I assume that some "expert" put the CPU on a table before mounting it, and they move it one the table - can't imaging how people manage to chop off the chips otherwise. While some of these damaged CPUs seem to work just fine, I had several which do not recognize more than 1-2 pcs of memory and, thus, would not recommend buying one of these. Cheers, Daniel

3 years, 11 months

Serial input / output with SeaBIOS 1.11.0

by Piotr Kubaj

Hi, I've upgraded my coreboot to tag 4.7. As a payload I use SeaBIOS. I want to use the new feature of serial communication from SeaBIOS. The issue I have is that there's only serial output (meaning I can see the SeaBIOS menu on serial), but pressing any key on keyboard via serial doesn't do anything - I can only control SeaBIOS via keyboard plugged directly to the board, not via serial. Does anyone have the same issue? I use AsRock E350M1 board. I didn't create a custum SeaBIOS config, I just use the default one. -- ________________________ / Accordion, n.: \ | | \ A bagpipe with pleats. / ------------------------ \ ^__^ \ (oo)\_______ (__)\ )\/\ ||----w | || ||

3 years, 11 months

ASUS KFSN4-DRE Automated Test Failure [master]

by Raptor Engineering Automated Coreboot Test Stand

The ASUS KFSN4-DRE fails verification for branch master as of commit bb1e539f1440bc805dd6350ffba9646454334b2f The following tests failed: BOOT_FAILURE Commits since last successful test: bb1e539 mb/google/poppy/variants/nautilus: Add gpio-keys ACPI node for PENH 3c8e00e drivers/gpio_keys: Add driver for handling gpio-keys See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

3 years, 11 months

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coreboot January 2018