coreboot January 2018

coreboot@coreboot.org

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Re: [coreboot] I want to be a contributor(Cloud Dai)
by Taiidan＠gmx.com 23 Jan '18

23 Jan '18

I would suggest purchasing a USB CH341A programmer, I use it for my KGPE-D16 and it is great.

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FSP_BayTrail SMBus Access
by Michael Graichen 23 Jan '18

23 Jan '18

Hey, i have managed to run Coreboot on a MSC C10M-BT https://www.msc-technologies.eu/products-solutions/products/boards/com-expr… but I need SMBus access to configure an eDPtoLVDS Chip before graphic gets initialized. I have seen in src/soc/intel/fsp_broadwell_de that there is a file smbus.c that seems to do this for Broadwell an can bee called from mainboard_enable() but it is missing in src/soc/intel/fsp_baytrail/. Is this the right place to do this implementations or is it done/should it be done somewhere else? Best regards Michael

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Server systems shipped with coreboot
by Carl-Daniel Hailfinger 23 Jan '18

23 Jan '18

Hi, does anyone have a list of server systems which are shipped with coreboot? I'm interested in coreboot+UEFI systems, coreboot+Linux systems, coreboot+SeaBIOS systems, pure coreboot systems. At 34C3 I was told by someone that a major vendor has been shipping servers with coreboot without announcing this, and I unfortunately neither remember the server model nor who told me about this. If said person could remind contact me, I'd be thankful. Regards, Carl-Daniel

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Re: [coreboot] I want to be a contributor(Cloud Dai)
by Merlin Büge 23 Jan '18

23 Jan '18

On Tue, 23 Jan 2018 21:02:02 +0800 戴，曉政 via coreboot <coreboot(a)coreboot.org> wrote: > Dear Taiidan, > > I just want to install and simply compile correboot at the current > stage because I am a junior develop of coreboot. I will buy a ASUS > KGPE-D16 mainboard from auction website after I restore my > development environment. Thank you for your response. I have two > question finally. > 1. Does BIOS rom of KGPE-D16 be removable? The BIOS (SPI) flash chip on the KGPE-D16 is socketed, so yes it is removable. If you plan to swap it, I highly recommend a dedicated DIP extractor for it! Something like this: https://lut.im/K9hQJgJbKk/gR8wUUwDwd7pjBMu.JPG > 2. Does architecture of KGPE-D16 be pre-PSP or not? Yes, it is pre-PSP. Good luck! > > > > > Dear Taiidan, > > > > I have read letter from Kyosti, he said ?AGESA family15 boards and > > chipset vendorcode for older than Trinity has been/will be removed > > on 4.7 release?. In this case, whether I still can >use H8SCM for > > my first coreboot mainboard or not? > >If you want to port coreboot it is a good board, to have as a > >functional device no. > > And I will try to port KGPE-D16 after I complete porting of H8SCM > > with coreboot. In addition, I apologize again for my poor English. > >Porting is creating the code base for a motherboard. > >Installing coreboot is simply compiling and installing, I am not > >sure which you want? The H8SCM needs a port whereas the KGPE-D16 is > >fully functional and a great example of coreboot ports. > > > > --- > Avast 防毒軟體已檢查此封電子郵件的病毒。 > https://www.avast.com/antivirus -- Merlin Büge <toni(a)bluenox07.de>

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Re: [coreboot] I want to be a contributor(Cloud Dai)
by 戴，曉政 23 Jan '18

23 Jan '18

Dear Taiidan, I just want to install and simply compile correboot at the current stage because I am a junior develop of coreboot. I will buy a ASUS KGPE-D16 mainboard from auction website after I restore my development environment. Thank you for your response. I have two question finally. 1. Does BIOS rom of KGPE-D16 be removable? 2. Does architecture of KGPE-D16 be pre-PSP or not? > Dear Taiidan, > > I have read letter from Kyosti, he said ?AGESA family15 boards and chipset vendorcode for older than Trinity has been/will be removed on 4.7 release?. In this case, whether I still can >use H8SCM for my first coreboot mainboard or not? >If you want to port coreboot it is a good board, to have as a functional >device no. > And I will try to port KGPE-D16 after I complete porting of H8SCM with coreboot. In addition, I apologize again for my poor English. >Porting is creating the code base for a motherboard. >Installing coreboot is simply compiling and installing, I am not sure >which you want? The H8SCM needs a port whereas the KGPE-D16 is fully >functional and a great example of coreboot ports. --- Avast 防毒軟體已檢查此封電子郵件的病毒。 https://www.avast.com/antivirus

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How are PCI capabilities set in coreboot?
by Taiidan＠gmx.com 23 Jan '18

23 Jan '18

How are the PCI capabilities in coreboot set for integrated devices? I have poked around the files but am unable to figure this out. Myself and my associates are trying to fix a few boards so the capabilities match the spec sheets - ie: add FLR to the USB controllers and ARI to the root hubs. Thank you!

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Re: [coreboot] I want to be a contributor
by Taiidan＠gmx.com 22 Jan '18

22 Jan '18

On 01/21/2018 09:56 AM, 戴，曉政 via coreboot wrote: > Dear Taiidan, > > I have read letter from Kyosti, he said ‘AGESA family15 boards and chipset vendorcode for older than Trinity has been/will be removed on 4.7 release’. In this case, whether I still can use H8SCM for my first coreboot mainboard or not? If you want to port coreboot it is a good board, to have as a functional device no. > And I will try to port KGPE-D16 after I complete porting of H8SCM with coreboot. In addition, I apologize again for my poor English. Porting is creating the code base for a motherboard. Installing coreboot is simply compiling and installing, I am not sure which you want? The H8SCM needs a port whereas the KGPE-D16 is fully functional and a great example of coreboot ports.

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Re: [coreboot] Link layer between "coreboot" - "seabios" - "coreinfo/nvramcui"
by Аладышев Константин 22 Jan '18

22 Jan '18

I've found out that commit that broke down compatibility with my old Coreboot was: libpayload/libc/console: Flush input driver buffer on init https://review.coreboot.org/#/c/coreboot/+/19345/ If I revert it with the newest Coreboot, payloads (coreinfo/nvramcui) will work with my old Coreboot version. Best regards, Aladyshev Konstantin -----Original Message----- From: Аладышев Константин [mailto:aladyshev@nicevt.ru] Sent: Thursday, January 18, 2018 1:02 PM To: 'Coreboot' Subject: Re: Link layer between "coreboot" - "seabios" - "coreinfo/nvramcui" Last lines of log from SeaBIOS: Run img/coreinfo.elf Segment 45444f43 48469@0xfff6a770 -> 405328@0x00100000 Uncompressing data 48469@0xfff6a770 to 405328@0x00100000 Calling addr 0x00100000 Best regards, Aladyshev Konstantin -----Original Message----- From: Аладышев Константин [mailto:aladyshev@nicevt.ru] Sent: Thursday, January 18, 2018 12:35 PM To: 'Coreboot' Subject: Link layer between "coreboot" - "seabios" - "coreinfo/nvramcui" Hello! I have a project for my motherboard with coreboot version that I fixed couple years back (so it is pretty old), and now I want to update all payloads to most modern ones. There is no problem with SeaBIOS, but coreinfo and nvramcui don't work. When I try to jump to them from SeaBIOS, nothing happens and screen turns black. So... what is the link layer between those payloads and coreboot? Layer that I should also update for those new payloads to work fine? Don't forget, this it is not only video problem, there is no output from COM also. So maybe it is connected to CBFS or payload format? What should I check? Best regards, Aladyshev Konstantin

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Re: [coreboot] Gigabyte Brix
by Igor Skochinsky 21 Jan '18

21 Jan '18

Hello Konrad, Sunday, January 21, 2018, 9:29:35 PM, you wrote: KE> Hi Igor, I know your work and I want to give kudos to you. However without being KE> kritical (it is just like that) I want to note the tips you read i.e. at winraid.com KE> really make you just more confused - eather they are refering to programmes that KE> are unavailabe or are from different contexts of Bios versions etc, or require you KE> to handle weapongrade security bypasses. Welcome to the world of BIOS modding. This stuff is not something you can just pick up in a couple hours, I'm actually impressed you managed to achieve it over a weekend. KE> Now I spent a whole weekend trying to enable DCI on the Brix. I managed it KE> in the end using only Ru.efi. KE> Because maybe coreboot people without the money to buy a SystemStudio and XDP KE> hardware for $5000 might find it interesting ther is a writeup here: KE> https://gist.github.com/eiselekd/d235b52a1615c79d3c6b3912731ab9b2#file-enab… KE> I think this method is reasonably easy and the board is cheap ($400). Nice writeup, thanks! Now you can start porting coreboot to it :) -- WBR, Igor mailto:skochinsky@mail.ru

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Re: [coreboot] Gigabyte Brix
by Igor Skochinsky 21 Jan '18

21 Jan '18

Hello Konrad, Sunday, January 21, 2018, 3:12:07 PM, you wrote: KE> You can probably set the DCI enable bit in the PCH softstraps in the KE> descriptor, no need to mess with the BIOS editing. It seems to be bit 17 KE> in strap 0, right next to the HAP bit: KE> <LayoutEntry name="PchStrapDciEnabled" type="bitfield32" KE> value="0x1" offset="0x0" bitfield_high="17" bitfield_low="17" /> KE> <LayoutEntry name="reserve_hap" type="bitfield32" value="0x0" KE> offset="0x0" bitfield_high="16" bitfield_low="16" /> KE> (xml from the Intel Flash Image Tool). KE> Interesting. Where can I read about this xml definition of the KE> softstrap. Which tool can I use to modify the PCH softstrap KE> section? Do I need to Intel Flash Image Tool for that, and where can KE> I download that one? I guess there are crcs and I cannot KE> just poke around? XMLs are stored in compressed format (as Qt resource) inside the FIT binary. You can find one approach of extracting them in Positive Technologies blog: http://blog.ptsecurity.com/2017/04/intel-me-way-of-static-analysis.html You can indeed use FIT for setting the strap but you'll have to find it yourself :) Or you can just edit the descriptor directly - it's not protected by any checksums or signatures. Check e.g. how me_cleaner sets the HAP bit: print("Setting the HAP bit in PCHSTRP0 to disable Intel ME...") fdf.seek(fpsba) pchstrp0 = unpack("<I", fdf.read(4))[0] pchstrp0 |= (1 << 16) fdf.write_to(fpsba, pack("<I", pchstrp0)) KE> I wonder weather DCI is left enabled when the BIOS start KE> initializing and probably I also need a softstrap bit for the KE> Debug Interface enable if I want to connect with DAL later? This depends on the specific BIOS implementation. I guess it's possible that they turn off DCI if it's not explicitly enabled in settings, but maybe you can intercept this with the debugger. KE> Why is this stuff so complicated? It's not complicated to firmware engineers who are familiar with low-level details of the platform and have access to the Intel docs/tools and support... If this is complicated for you, maybe you are looking at the wrong thing. -- WBR, Igor mailto:skochinsky@mail.ru

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coreboot January 2018