coreboot January 2018

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Re: [coreboot] Link layer between "coreboot" - "seabios" - "coreinfo/nvramcui"
by Аладышев Константин 18 Jan '18

18 Jan '18

Last lines of log from SeaBIOS: Run img/coreinfo.elf Segment 45444f43 48469@0xfff6a770 -> 405328@0x00100000 Uncompressing data 48469@0xfff6a770 to 405328@0x00100000 Calling addr 0x00100000 Best regards, Aladyshev Konstantin -----Original Message----- From: Аладышев Константин [mailto:aladyshev@nicevt.ru] Sent: Thursday, January 18, 2018 12:35 PM To: 'Coreboot' Subject: Link layer between "coreboot" - "seabios" - "coreinfo/nvramcui" Hello! I have a project for my motherboard with coreboot version that I fixed couple years back (so it is pretty old), and now I want to update all payloads to most modern ones. There is no problem with SeaBIOS, but coreinfo and nvramcui don't work. When I try to jump to them from SeaBIOS, nothing happens and screen turns black. So... what is the link layer between those payloads and coreboot? Layer that I should also update for those new payloads to work fine? Don't forget, this it is not only video problem, there is no output from COM also. So maybe it is connected to CBFS or payload format? What should I check? Best regards, Aladyshev Konstantin

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Link layer between "coreboot" - "seabios" - "coreinfo/nvramcui"
by Аладышев Константин 18 Jan '18

18 Jan '18

Hello! I have a project for my motherboard with coreboot version that I fixed couple years back (so it is pretty old), and now I want to update all payloads to most modern ones. There is no problem with SeaBIOS, but coreinfo and nvramcui don't work. When I try to jump to them from SeaBIOS, nothing happens and screen turns black. So... what is the link layer between those payloads and coreboot? Layer that I should also update for those new payloads to work fine? Don't forget, this it is not only video problem, there is no output from COM also. So maybe it is connected to CBFS or payload format? What should I check? Best regards, Aladyshev Konstantin

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 16 Jan '18

16 Jan '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 29 new defect(s) introduced to coreboot found with Coverity Scan. 28 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 20 of 29 defect(s) ** CID 1385126: (UNUSED_VALUE) /src/mainboard/asus/am1i-a/romstage.c: 148 in board_BeforeAgesa() /src/mainboard/asus/am1i-a/romstage.c: 154 in board_BeforeAgesa() ________________________________________________________________________________________________________ *** CID 1385126: (UNUSED_VALUE) /src/mainboard/asus/am1i-a/romstage.c: 148 in board_BeforeAgesa() 142 /* Enable the AcpiMmio space */ 143 outb(0x24, 0xcd6); 144 outb(0x1, 0xcd7); 145 146 /* Configure ClkDrvStr1 settings */ 147 addr32 = (u32 *)0xfed80e24; >>> CID 1385126: (UNUSED_VALUE) >>> Assigning value from "*addr32" to "t32" here, but that stored value is overwritten before it can be used. 148 t32 = *addr32; 149 t32 = 0x030800aa; 150 *addr32 = t32; 151 152 /* Configure MiscClkCntl1 settings */ 153 addr32 = (u32 *)0xfed80e40; /src/mainboard/asus/am1i-a/romstage.c: 154 in board_BeforeAgesa() 148 t32 = *addr32; 149 t32 = 0x030800aa; 150 *addr32 = t32; 151 152 /* Configure MiscClkCntl1 settings */ 153 addr32 = (u32 *)0xfed80e40; >>> CID 1385126: (UNUSED_VALUE) >>> Assigning value from "*addr32" to "t32" here, but that stored value is overwritten before it can be used. 154 t32 = *addr32; 155 t32 = 0x000c4050; 156 *addr32 = t32; 157 158 /* enable SIO LPC decode */ 159 dev = PCI_DEV(0, 0x14, 3); ** CID 1383919: Resource leaks (RESOURCE_LEAK) /util/cbfstool/partitioned_file.c: 201 in partitioned_file_reopen() ________________________________________________________________________________________________________ *** CID 1383919: Resource leaks (RESOURCE_LEAK) /util/cbfstool/partitioned_file.c: 201 in partitioned_file_reopen() 195 } 196 197 const struct fmap_area *fmap_fmap_entry = 198 fmap_find_area(file->fmap, SECTION_NAME_FMAP); 199 200 if (!fmap_fmap_entry) >>> CID 1383919: Resource leaks (RESOURCE_LEAK) >>> Variable "file" going out of scope leaks the storage it points to. 201 return NULL; 202 203 if ((long)fmap_fmap_entry->offset != fmap_region_offset) { 204 ERROR("FMAP's '%s' section doesn't point back to FMAP start (did something corrupt this file?)\n", 205 SECTION_NAME_FMAP); 206 partitioned_file_close(file); ** CID 1361275: (TAINTED_SCALAR) /util/cbfstool/ifwitool.c: 839 in parse_subpart_dir() ________________________________________________________________________________________________________ *** CID 1361275: (TAINTED_SCALAR) /util/cbfstool/ifwitool.c: 832 in parse_subpart_dir() 826 memcpy(hdr.name, data + offset, sizeof(hdr.name)); 827 offset += sizeof(hdr.name); 828 829 validate_subpart_dir_without_checksum((struct subpart_dir *)&hdr, name); 830 831 assert(size > subpart_dir_size(&hdr)); >>> CID 1361275: (TAINTED_SCALAR) >>> Passing tainted variable "subpart_dir_size(&hdr)" to a tainted sink. 832 alloc_buffer(subpart_dir_buf, subpart_dir_size(&hdr), "Subpart Dir"); 833 memcpy(buffer_get(subpart_dir_buf), &hdr, SUBPART_DIR_HEADER_SIZE); 834 835 /* Read Subpart Dir entries. */ 836 struct subpart_dir *subpart_dir = buffer_get(subpart_dir_buf); 837 struct subpart_dir_entry *e = &subpart_dir->e[0]; /util/cbfstool/ifwitool.c: 839 in parse_subpart_dir() 833 memcpy(buffer_get(subpart_dir_buf), &hdr, SUBPART_DIR_HEADER_SIZE); 834 835 /* Read Subpart Dir entries. */ 836 struct subpart_dir *subpart_dir = buffer_get(subpart_dir_buf); 837 struct subpart_dir_entry *e = &subpart_dir->e[0]; 838 uint32_t i; >>> CID 1361275: (TAINTED_SCALAR) >>> Using tainted variable "hdr.num_entries" as a loop boundary. 839 for (i = 0; i < hdr.num_entries; i++) { 840 memcpy(e[i].name, data + offset, sizeof(e[i].name)); 841 offset += sizeof(e[i].name); 842 offset = read_member(data, offset, sizeof(e[i].offset), 843 &e[i].offset); 844 offset = read_member(data, offset, sizeof(e[i].length), ** CID 1361274: Insecure data handling (TAINTED_SCALAR) ________________________________________________________________________________________________________ *** CID 1361274: Insecure data handling (TAINTED_SCALAR) /util/cbfstool/ifwitool.c: 718 in alloc_bpdt_buffer() 712 { 713 struct bpdt_header bpdt_header; 714 assert((offset + BPDT_HEADER_SIZE) < size); 715 bpdt_read_header((uint8_t *)data + offset, &bpdt_header, name); 716 717 /* Buffer to read BPDT header and entries. */ >>> CID 1361274: Insecure data handling (TAINTED_SCALAR) >>> Passing tainted variable "get_bpdt_size(&bpdt_header)" to a tainted sink. 718 alloc_buffer(b, get_bpdt_size(&bpdt_header), name); 719 720 struct bpdt *bpdt = buffer_get(b); 721 memcpy(&bpdt->h, &bpdt_header, BPDT_HEADER_SIZE); 722 723 /* ** CID 1361253: Memory - illegal accesses (BUFFER_SIZE_WARNING) /util/cbfstool/ifwitool.c: 1301 in init_subpart_dir_entry() ________________________________________________________________________________________________________ *** CID 1361253: Memory - illegal accesses (BUFFER_SIZE_WARNING) /util/cbfstool/ifwitool.c: 1301 in init_subpart_dir_entry() 1295 static size_t init_subpart_dir_entry(struct subpart_dir_entry *e, 1296 struct buffer *b, size_t offset) 1297 { 1298 memset(e, 0, sizeof(*e)); 1299 1300 assert(strlen(b->name) <= sizeof(e->name)); >>> CID 1361253: Memory - illegal accesses (BUFFER_SIZE_WARNING) >>> Calling strncpy with a maximum size argument of 12 bytes on destination array "e->name" of size 12 bytes might leave the destination string unterminated. 1301 strncpy((char *)e->name, (char *)b->name, sizeof(e->name)); 1302 e->offset = offset; 1303 e->length = buffer_size(b); 1304 1305 return (offset + buffer_size(b)); 1306 } ** CID 1353028: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 352 in integrate_psp_firmwares() ________________________________________________________________________________________________________ *** CID 1353028: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 352 in integrate_psp_firmwares() 346 pspdir[4+4*i+2] = 1; 347 pspdir[4+4*i+3] = 0; 348 } else if (fw_table[i].filename != NULL) { 349 pspdir[4+4*i+0] = fw_table[i].type; 350 351 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353028: Error handling issues (NEGATIVE_RETURNS) >>> "fd" is passed to a parameter that cannot be negative. [Note: The source code implementation of the function has been overridden by a builtin model.] 352 fstat(fd, &fd_stat); 353 pspdir[4+4*i+1] = (uint32_t)fd_stat.st_size; 354 355 pspdir[4+4*i+2] = pos + rom_base_address; 356 pspdir[4+4*i+3] = 0; 357 ** CID 1353027: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 295 in integrate_firmwares() ________________________________________________________________________________________________________ *** CID 1353027: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 295 in integrate_firmwares() 289 int i; 290 uint32_t rom_base_address = 0xFFFFFFFF - rom_size + 1; 291 292 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { 293 if (fw_table[i].filename != NULL) { 294 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353027: Error handling issues (NEGATIVE_RETURNS) >>> "fd" is passed to a parameter that cannot be negative. [Note: The source code implementation of the function has been overridden by a builtin model.] 295 fstat(fd, &fd_stat); 296 297 switch (fw_table[i].type) { 298 case AMD_FW_IMC: 299 pos = ALIGN(pos, 0x10000U); 300 romsig[1] = pos + rom_base_address; ** CID 1353021: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 366 in integrate_psp_firmwares() ________________________________________________________________________________________________________ *** CID 1353021: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 366 in integrate_psp_firmwares() 360 " will not fit %s. Exiting.\n", 361 rom_size, fw_table[i].filename); 362 free(base); 363 exit(1); 364 } 365 >>> CID 1353021: Error handling issues (CHECKED_RETURN) >>> "read(int, void *, size_t)" returns the number of bytes read, but it is ignored. 366 read(fd, (void *)(base + pos), (size_t)fd_stat.st_size); 367 368 pos += fd_stat.st_size; 369 close(fd); 370 pos = ALIGN(pos, 0x100U); 371 } else { ** CID 1353020: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 352 in integrate_psp_firmwares() ________________________________________________________________________________________________________ *** CID 1353020: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 352 in integrate_psp_firmwares() 346 pspdir[4+4*i+2] = 1; 347 pspdir[4+4*i+3] = 0; 348 } else if (fw_table[i].filename != NULL) { 349 pspdir[4+4*i+0] = fw_table[i].type; 350 351 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353020: Error handling issues (CHECKED_RETURN) >>> Calling "fstat(fd, &fd_stat)" without checking return value. This library function may fail and return an error code. [Note: The source code implementation of the function has been overridden by a builtin model.] 352 fstat(fd, &fd_stat); 353 pspdir[4+4*i+1] = (uint32_t)fd_stat.st_size; 354 355 pspdir[4+4*i+2] = pos + rom_base_address; 356 pspdir[4+4*i+3] = 0; 357 ** CID 1353019: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 321 in integrate_firmwares() ________________________________________________________________________________________________________ *** CID 1353019: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 321 in integrate_firmwares() 315 " will not fit %s. Exiting.\n", 316 rom_size, fw_table[i].filename); 317 free(base); 318 exit(1); 319 } 320 >>> CID 1353019: Error handling issues (CHECKED_RETURN) >>> "read(int, void *, size_t)" returns the number of bytes read, but it is ignored. 321 read(fd, (void *)(base + pos), (size_t)fd_stat.st_size); 322 323 pos += fd_stat.st_size; 324 close(fd); 325 pos = ALIGN(pos, 0x100U); 326 } ** CID 1353018: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 295 in integrate_firmwares() ________________________________________________________________________________________________________ *** CID 1353018: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 295 in integrate_firmwares() 289 int i; 290 uint32_t rom_base_address = 0xFFFFFFFF - rom_size + 1; 291 292 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { 293 if (fw_table[i].filename != NULL) { 294 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353018: Error handling issues (CHECKED_RETURN) >>> Calling "fstat(fd, &fd_stat)" without checking return value. This library function may fail and return an error code. [Note: The source code implementation of the function has been overridden by a builtin model.] 295 fstat(fd, &fd_stat); 296 297 switch (fw_table[i].type) { 298 case AMD_FW_IMC: 299 pos = ALIGN(pos, 0x10000U); 300 romsig[1] = pos + rom_base_address; ** CID 1347335: (UNINIT) /util/cbfstool/elfheaders.c: 1000 in write_phdrs() /util/cbfstool/elfheaders.c: 1002 in write_phdrs() /util/cbfstool/elfheaders.c: 1003 in write_phdrs() /util/cbfstool/elfheaders.c: 1004 in write_phdrs() ________________________________________________________________________________________________________ *** CID 1347335: (UNINIT) /util/cbfstool/elfheaders.c: 1000 in write_phdrs() 994 } else { 995 /* Accumulate file size and memsize. The assumption 996 * is that each section is either NOBITS or full 997 * (sh_size == file size). This is standard in that 998 * an ELF section doesn't have a file size component. */ 999 if (sec->shdr.sh_flags & SHF_EXECINSTR) >>> CID 1347335: (UNINIT) >>> Using uninitialized value "phdr.p_flags". 1000 phdr.p_flags |= PF_X | PF_R; 1001 if (sec->shdr.sh_flags & SHF_WRITE) 1002 phdr.p_flags |= PF_W; 1003 phdr.p_filesz += buffer_size(&sec->content); 1004 phdr.p_memsz += sec->shdr.sh_size; 1005 } /util/cbfstool/elfheaders.c: 1002 in write_phdrs() 996 * is that each section is either NOBITS or full 997 * (sh_size == file size). This is standard in that 998 * an ELF section doesn't have a file size component. */ 999 if (sec->shdr.sh_flags & SHF_EXECINSTR) 1000 phdr.p_flags |= PF_X | PF_R; 1001 if (sec->shdr.sh_flags & SHF_WRITE) >>> CID 1347335: (UNINIT) >>> Using uninitialized value "phdr.p_flags". 1002 phdr.p_flags |= PF_W; 1003 phdr.p_filesz += buffer_size(&sec->content); 1004 phdr.p_memsz += sec->shdr.sh_size; 1005 } 1006 } 1007 /util/cbfstool/elfheaders.c: 1003 in write_phdrs() 997 * (sh_size == file size). This is standard in that 998 * an ELF section doesn't have a file size component. */ 999 if (sec->shdr.sh_flags & SHF_EXECINSTR) 1000 phdr.p_flags |= PF_X | PF_R; 1001 if (sec->shdr.sh_flags & SHF_WRITE) 1002 phdr.p_flags |= PF_W; >>> CID 1347335: (UNINIT) >>> Using uninitialized value "phdr.p_filesz". 1003 phdr.p_filesz += buffer_size(&sec->content); 1004 phdr.p_memsz += sec->shdr.sh_size; 1005 } 1006 } 1007 1008 /* Write out the last phdr. */ /util/cbfstool/elfheaders.c: 1004 in write_phdrs() 998 * an ELF section doesn't have a file size component. */ 999 if (sec->shdr.sh_flags & SHF_EXECINSTR) 1000 phdr.p_flags |= PF_X | PF_R; 1001 if (sec->shdr.sh_flags & SHF_WRITE) 1002 phdr.p_flags |= PF_W; 1003 phdr.p_filesz += buffer_size(&sec->content); >>> CID 1347335: (UNINIT) >>> Using uninitialized value "phdr.p_memsz". 1004 phdr.p_memsz += sec->shdr.sh_size; 1005 } 1006 } 1007 1008 /* Write out the last phdr. */ 1009 if (num_needs_write != num_written) { ** CID 1302457: Control flow issues (MISSING_RESTORE) /util/cbfstool/flashmap/fmap.c: 485 in fmap_append_area_test() ________________________________________________________________________________________________________ *** CID 1302457: Control flow issues (MISSING_RESTORE) /util/cbfstool/flashmap/fmap.c: 485 in fmap_append_area_test() 479 if ((*fmap)->nareas != 1) { 480 printf("FAILURE: failed to increment number of areas\n"); 481 goto fmap_append_area_test_exit; 482 } 483 484 status = pass; >>> CID 1302457: Control flow issues (MISSING_RESTORE) >>> Jumped to here, skipping restore. 485 fmap_append_area_test_exit: 486 return status; 487 } 488 489 static int fmap_find_area_test(struct fmap *fmap) 490 { ** CID 1302456: Error handling issues (NEGATIVE_RETURNS) /util/cbfstool/flashmap/fmap.c: 601 in fmap_find_test() ________________________________________________________________________________________________________ *** CID 1302456: Error handling issues (NEGATIVE_RETURNS) /util/cbfstool/flashmap/fmap.c: 601 in fmap_find_test() 595 printf("FAILURE: bsearch returned false positive\n"); 596 goto fmap_find_test_exit; 597 } 598 599 /* simple test case: fmap at (total_size / 2) + 1 */ 600 offset = (total_size / 2) + 1; >>> CID 1302456: Error handling issues (NEGATIVE_RETURNS) >>> "fmap_size(fmap)" is passed to a parameter that cannot be negative. [Note: The source code implementation of the function has been overridden by a builtin model.] 601 memcpy(&buf[offset], fmap, fmap_size(fmap)); 602 603 if ((unsigned)fmap_find(buf, total_size - 1) != offset) { 604 printf("FAILURE: lsearch failed to find fmap\n"); 605 goto fmap_find_test_exit; 606 } ** CID 1302453: Resource leaks (RESOURCE_LEAK) /util/cbfstool/flashmap/fmap.c: 563 in fmap_flags_to_string_test() ________________________________________________________________________________________________________ *** CID 1302453: Resource leaks (RESOURCE_LEAK) /util/cbfstool/flashmap/fmap.c: 563 in fmap_flags_to_string_test() 557 } 558 free(my_str); 559 free(str); 560 561 status = pass; 562 fmap_flags_to_string_test_exit: >>> CID 1302453: Resource leaks (RESOURCE_LEAK) >>> Variable "my_str" going out of scope leaks the storage it points to. 563 return status; 564 565 } 566 567 static int fmap_find_test(struct fmap *fmap) 568 { ** CID 1302452: (RESOURCE_LEAK) /util/cbfstool/flashmap/fmap.c: 563 in fmap_flags_to_string_test() /util/cbfstool/flashmap/fmap.c: 563 in fmap_flags_to_string_test() ________________________________________________________________________________________________________ *** CID 1302452: (RESOURCE_LEAK) /util/cbfstool/flashmap/fmap.c: 563 in fmap_flags_to_string_test() 557 } 558 free(my_str); 559 free(str); 560 561 status = pass; 562 fmap_flags_to_string_test_exit: >>> CID 1302452: (RESOURCE_LEAK) >>> Variable "str" going out of scope leaks the storage it points to. 563 return status; 564 565 } 566 567 static int fmap_find_test(struct fmap *fmap) 568 { /util/cbfstool/flashmap/fmap.c: 563 in fmap_flags_to_string_test() 557 } 558 free(my_str); 559 free(str); 560 561 status = pass; 562 fmap_flags_to_string_test_exit: >>> CID 1302452: (RESOURCE_LEAK) >>> Variable "str" going out of scope leaks the storage it points to. 563 return status; 564 565 } 566 567 static int fmap_find_test(struct fmap *fmap) 568 { ** CID 1302451: Resource leaks (RESOURCE_LEAK) /util/cbfstool/flashmap/fmap.c: 240 in fmap_print() ________________________________________________________________________________________________________ *** CID 1302451: Resource leaks (RESOURCE_LEAK) /util/cbfstool/flashmap/fmap.c: 240 in fmap_print() 234 kv_pair_fmt(pair, "area_flags_raw", "0x%02x", 235 fmap->areas[i].flags); 236 237 /* Print descriptive strings for flags rather than the field */ 238 flags = fmap->areas[i].flags; 239 if ((str = fmap_flags_to_string(flags)) == NULL) >>> CID 1302451: Resource leaks (RESOURCE_LEAK) >>> Variable "pair" going out of scope leaks the storage it points to. 240 return -1; 241 kv_pair_fmt(pair, "area_flags", "%s", str); 242 free(str); 243 244 kv_pair_print(pair); 245 kv_pair_free(pair); ** CID 1241818: Memory - illegal accesses (OVERRUN) /src/vendorcode/amd/cimx/rd890/nbPcieLib.c: 1359 in PcieLibGetPortInfo() ________________________________________________________________________________________________________ *** CID 1241818: Memory - illegal accesses (OVERRUN) /src/vendorcode/amd/cimx/rd890/nbPcieLib.c: 1359 in PcieLibGetPortInfo() 1353 case GPP3a_CORE: 1354 pGppCfgInfoTable = (GPP_CFG_INFO*)FIX_PTR_ADDR (&GppCfgInfoTable[CoreConfig - 1], NULL); 1355 NativePortId = PcieLibNativePortId (PortId, pConfig); 1356 if (NativePortId == 0xf) { 1357 return NULL; 1358 } >>> CID 1241818: Memory - illegal accesses (OVERRUN) >>> Overrunning array of 6 8-byte elements at element index 4294967295 (byte offset 34359738360) by dereferencing pointer "pGppCfgInfoTable". 1359 pPortInfo = &pGppCfgInfoTable->PortInfoPtr[NativePortId - 4]; 1360 break; 1361 default: 1362 return NULL; 1363 } 1364 return (PORT_INFO*)FIX_PTR_ADDR (pPortInfo, NULL); ** CID 1241790: Insecure data handling (TAINTED_SCALAR) /util/cbfstool/lzma/C/LzFind.c: 653 in Bt2_MatchFinder_Skip() ________________________________________________________________________________________________________ *** CID 1241790: Insecure data handling (TAINTED_SCALAR) /util/cbfstool/lzma/C/LzFind.c: 653 in Bt2_MatchFinder_Skip() 647 static void Bt2_MatchFinder_Skip(struct CMatchFinder *p, uint32_t num) 648 { 649 do 650 { 651 SKIP_HEADER(2) 652 HASH2_CALC; >>> CID 1241790: Insecure data handling (TAINTED_SCALAR) >>> Using tainted variable "hashValue" as an index to pointer "p->hash". 653 curMatch = p->hash[hashValue]; 654 p->hash[hashValue] = p->pos; 655 SKIP_FOOTER 656 } 657 while (--num != 0); 658 } ** CID 1241788: Insecure data handling (TAINTED_SCALAR) /util/cbfstool/lzma/C/LzFind.c: 489 in Bt2_MatchFinder_GetMatches() ________________________________________________________________________________________________________ *** CID 1241788: Insecure data handling (TAINTED_SCALAR) /util/cbfstool/lzma/C/LzFind.c: 489 in Bt2_MatchFinder_GetMatches() 483 484 static uint32_t Bt2_MatchFinder_GetMatches(struct CMatchFinder *p, uint32_t *distances) 485 { 486 uint32_t offset; 487 GET_MATCHES_HEADER(2) 488 HASH2_CALC; >>> CID 1241788: Insecure data handling (TAINTED_SCALAR) >>> Using tainted variable "hashValue" as an index to pointer "p->hash". 489 curMatch = p->hash[hashValue]; 490 p->hash[hashValue] = p->pos; 491 offset = 0; 492 GET_MATCHES_FOOTER(offset, 1) 493 } 494 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] BDX-DE PCI init fail
by Zoran Stojsavljevic 16 Jan '18

16 Jan '18

Hilbert, David is right. GRUB2 should be also Legacy installable. I am simply forgetting stuff, since I am not in BSP domain anymore, these days. Today early morning I started my Fedora 27, and it failed to enter grub.cfg for unknown reason (file was wiped out for some reason?!). It is, after all, an easy fix, I estimated 10 minutes for that, but it took me (amazingly) an hour to recover grub.cfg. It is matter of practice... It is. ;-) Zoran _______ On Tue, Jan 16, 2018 at 6:14 AM, David Hendricks <david.hendricks(a)gmail.com> wrote: > Hi Hilbert, > > On Mon, Jan 15, 2018 at 12:51 AM, Hilbert Tu(杜睿哲_Pegatron) < > Hilbert_Tu(a)pegatroncorp.com> wrote: > >> Hi Zoran, >> >> That information was dumped when I use SeaBIOS as coreboot's payload. I >> don't know why it is related to GRUB_legacy. If I use GRUB2 as payload, it >> just hangs there. I am still struggling on this :( >> > > If you are using serial console, did you remember to enable serial output > in grub.cfg? There is a GRUB2 wiki page on coreboot.org which you might > find helpful (if you haven't already read it): > https://www.coreboot.org/GRUB2 > > > By the way, I saw following message in the log. Should I choose >> NodeManager Mode? Do you know what's different? > > >> >>[SPS] SiliconEnabling Mode >> >> >> Thanks. >> -Hilbert >> >> -----Original Message----- >> From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] >> Sent: Thursday, January 11, 2018 7:27 PM >> To: Hilbert Tu(杜睿哲_Pegatron) >> Cc: Zeh, Werner; coreboot(a)coreboot.org; David Hendricks >> Subject: Re: [coreboot] BDX-DE PCI init fail >> >> > Booting from Hard Disk... >> > Booting from 0000:7c00 >> >> It is booting from the thirty second Kbyte of HDD (sector 62, sector 0 >> is MBR), where the beginning of GRUB Legacy is placed/implanted, >> called core.img or similar name. >> >> https://wiki.archlinux.org/index.php/GRUB_Legacy >> >> Well, you have succeed, by all means. Problem solved! ;-) >> >> Zoran >> _______ >> >> On Thu, Jan 11, 2018 at 12:06 PM, Hilbert Tu(杜睿哲_Pegatron) >> <Hilbert_Tu(a)pegatroncorp.com> wrote: >> > Hi Werner, >> > >> > Thanks for your information. It works but still has same result. The >> result is like following. My usb stick is ext4fs formatted and has kernel >> and rootfs files. I wish SeaBIOS can give me a shell like Grub so that I >> can specify how to boot next. Or should I create a bootable usb stick? >> > >> > >> > ============= PEIM FSP is Completed ============= >> > >> > Returned from FspNotify(EnumInitPhaseReadyToBoot) >> > Jumping to boot code at 000ff06e(7eff6000) >> > CPU0: stack: 00128000 - 00129000, lowest used address 00128b00, stack >> used: 1280 bytes >> > entry = 0x000ff06e >> > lb_start = 0x00100000 >> > lb_size = 0x0012d6d0 >> > buffer = 0x7ed66000 >> > SeaBIOS (version rel-1.10.2-0-g5f4c7b1) >> > BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: >> (GNU Binutils) 2.28 >> > Found mainboard Intel Camelback Mountain CRB >> > Relocating init from 0x000e3860 to 0x7ef74cc0 (size 49824) >> > Found CBFS header at 0xffe00138 >> > multiboot: eax=0, ebx=0 >> > Found 25 PCI devices (max PCI bus is 05) >> > Copying SMBIOS entry point from 0x7efc1000 to 0x000f7140 >> > Copying ACPI RSDP from 0x7efd2000 to 0x000f7110 >> > Using pmtimer, ioport 0x408 >> > WARNING - Timeout at tis_wait_sts:160! >> > WARNING - Timeout at tis_wait_sts:160! >> > Scan for VGA option rom >> > XHCI init on dev 00:14.0: regs @ 0xfea00000, 21 ports, 32 slots, 32 >> byte contexts >> > XHCI protocol USB 2.00, 8 ports (offset 1), def 3001 >> > XHCI protocol USB 3.00, 6 ports (offset 16), def 1000 >> > XHCI extcap 0xc1 @ 0xfea08040 >> > XHCI extcap 0xc0 @ 0xfea08070 >> > XHCI extcap 0x1 @ 0xfea0846c >> > EHCI init on dev 00:1a.0 (regs=0xfea18020) >> > EHCI init on dev 00:1d.0 (regs=0xfea19020) >> > WARNING - Timeout at i8042_flush:71! >> > ebda moved from 9f000 to 9e800 >> > AHCI controller at 00:1f.2, iobase 0xfea17000, irq 5 >> > Found 0 lpt ports >> > Found 2 serial ports >> > XHCI no devices found >> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 >> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 >> > USB MSC vendor='Generic-' product='Multiple Reader' rev='1.11' type=0 >> removable=1 >> > ehci_wait_td error - status=80e42 >> > Initialized USB HUB (0 ports used) >> > USB MSC blksize=512 sectors=30777344 >> > Initialized USB HUB (1 ports used) >> > All threads complete. >> > Scan for option roms >> > Running option rom at c000:0003 >> > Running option rom at c100:0003 >> > Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0 >> > Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0,1 >> > >> > Press ESC for boot menu. >> > >> > WARNING - Timeout at tis_wait_sts:160! >> > Searching bootorder for: HALT >> > drive 0x000f70c0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=30777344 >> > Space available for UMB: c2000-efb00, f6960-f70c0 >> > Returned 184320 bytes of ZoneHigh >> > e820 map has 9 items: >> > 0: 0000000000000000 - 000000000009e800 = 1 RAM >> > 1: 000000000009e800 - 00000000000a0000 = 2 RESERVED >> > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED >> > 3: 0000000000100000 - 000000007efae000 = 1 RAM >> > 4: 000000007efae000 - 0000000090000000 = 2 RESERVED >> > 5: 00000000feb00000 - 00000000feb10000 = 2 RESERVED >> > 6: 00000000feb80000 - 00000000fef00000 = 2 RESERVED >> > 7: 00000000ff000000 - 0000000100000000 = 2 RESERVED >> > 8: 0000000100000000 - 0000000280000000 = 1 RAM >> > enter handle_19: >> > NULL >> > Booting from Hard Disk... >> > Booting from 0000:7c00 >> > >> > -Hilbert >> > >> > This e-mail and its attachment may contain information that is >> confidential or privileged, and are solely for the use of the individual to >> whom this e-mail is addressed. If you are not the intended recipient or >> have received it accidentally, please immediately notify the sender by >> reply e-mail and destroy all copies of this email and its attachment. >> Please be advised that any unauthorized use, disclosure, distribution or >> copying of this email or its attachment is strictly prohibited. >> > 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子 >> 郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 >> > >

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Re: [coreboot] BDX-DE PCI init fail
by David Hendricks 16 Jan '18

16 Jan '18

Hi Hilbert, On Mon, Jan 15, 2018 at 12:51 AM, Hilbert Tu(杜睿哲_Pegatron) < Hilbert_Tu(a)pegatroncorp.com> wrote: > Hi Zoran, > > That information was dumped when I use SeaBIOS as coreboot's payload. I > don't know why it is related to GRUB_legacy. If I use GRUB2 as payload, it > just hangs there. I am still struggling on this :( > If you are using serial console, did you remember to enable serial output in grub.cfg? There is a GRUB2 wiki page on coreboot.org which you might find helpful (if you haven't already read it): https://www.coreboot.org/GRUB2 By the way, I saw following message in the log. Should I choose NodeManager > Mode? Do you know what's different? > >>[SPS] SiliconEnabling Mode > > > Thanks. > -Hilbert > > -----Original Message----- > From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > Sent: Thursday, January 11, 2018 7:27 PM > To: Hilbert Tu(杜睿哲_Pegatron) > Cc: Zeh, Werner; coreboot(a)coreboot.org; David Hendricks > Subject: Re: [coreboot] BDX-DE PCI init fail > > > Booting from Hard Disk... > > Booting from 0000:7c00 > > It is booting from the thirty second Kbyte of HDD (sector 62, sector 0 > is MBR), where the beginning of GRUB Legacy is placed/implanted, > called core.img or similar name. > > https://wiki.archlinux.org/index.php/GRUB_Legacy > > Well, you have succeed, by all means. Problem solved! ;-) > > Zoran > _______ > > On Thu, Jan 11, 2018 at 12:06 PM, Hilbert Tu(杜睿哲_Pegatron) > <Hilbert_Tu(a)pegatroncorp.com> wrote: > > Hi Werner, > > > > Thanks for your information. It works but still has same result. The > result is like following. My usb stick is ext4fs formatted and has kernel > and rootfs files. I wish SeaBIOS can give me a shell like Grub so that I > can specify how to boot next. Or should I create a bootable usb stick? > > > > > > ============= PEIM FSP is Completed ============= > > > > Returned from FspNotify(EnumInitPhaseReadyToBoot) > > Jumping to boot code at 000ff06e(7eff6000) > > CPU0: stack: 00128000 - 00129000, lowest used address 00128b00, stack > used: 1280 bytes > > entry = 0x000ff06e > > lb_start = 0x00100000 > > lb_size = 0x0012d6d0 > > buffer = 0x7ed66000 > > SeaBIOS (version rel-1.10.2-0-g5f4c7b1) > > BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: > (GNU Binutils) 2.28 > > Found mainboard Intel Camelback Mountain CRB > > Relocating init from 0x000e3860 to 0x7ef74cc0 (size 49824) > > Found CBFS header at 0xffe00138 > > multiboot: eax=0, ebx=0 > > Found 25 PCI devices (max PCI bus is 05) > > Copying SMBIOS entry point from 0x7efc1000 to 0x000f7140 > > Copying ACPI RSDP from 0x7efd2000 to 0x000f7110 > > Using pmtimer, ioport 0x408 > > WARNING - Timeout at tis_wait_sts:160! > > WARNING - Timeout at tis_wait_sts:160! > > Scan for VGA option rom > > XHCI init on dev 00:14.0: regs @ 0xfea00000, 21 ports, 32 slots, 32 byte > contexts > > XHCI protocol USB 2.00, 8 ports (offset 1), def 3001 > > XHCI protocol USB 3.00, 6 ports (offset 16), def 1000 > > XHCI extcap 0xc1 @ 0xfea08040 > > XHCI extcap 0xc0 @ 0xfea08070 > > XHCI extcap 0x1 @ 0xfea0846c > > EHCI init on dev 00:1a.0 (regs=0xfea18020) > > EHCI init on dev 00:1d.0 (regs=0xfea19020) > > WARNING - Timeout at i8042_flush:71! > > ebda moved from 9f000 to 9e800 > > AHCI controller at 00:1f.2, iobase 0xfea17000, irq 5 > > Found 0 lpt ports > > Found 2 serial ports > > XHCI no devices found > > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 > > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 > > USB MSC vendor='Generic-' product='Multiple Reader' rev='1.11' type=0 > removable=1 > > ehci_wait_td error - status=80e42 > > Initialized USB HUB (0 ports used) > > USB MSC blksize=512 sectors=30777344 > > Initialized USB HUB (1 ports used) > > All threads complete. > > Scan for option roms > > Running option rom at c000:0003 > > Running option rom at c100:0003 > > Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0 > > Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0,1 > > > > Press ESC for boot menu. > > > > WARNING - Timeout at tis_wait_sts:160! > > Searching bootorder for: HALT > > drive 0x000f70c0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=30777344 > > Space available for UMB: c2000-efb00, f6960-f70c0 > > Returned 184320 bytes of ZoneHigh > > e820 map has 9 items: > > 0: 0000000000000000 - 000000000009e800 = 1 RAM > > 1: 000000000009e800 - 00000000000a0000 = 2 RESERVED > > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED > > 3: 0000000000100000 - 000000007efae000 = 1 RAM > > 4: 000000007efae000 - 0000000090000000 = 2 RESERVED > > 5: 00000000feb00000 - 00000000feb10000 = 2 RESERVED > > 6: 00000000feb80000 - 00000000fef00000 = 2 RESERVED > > 7: 00000000ff000000 - 0000000100000000 = 2 RESERVED > > 8: 0000000100000000 - 0000000280000000 = 1 RAM > > enter handle_19: > > NULL > > Booting from Hard Disk... > > Booting from 0000:7c00 > > > > -Hilbert > > > > This e-mail and its attachment may contain information that is > confidential or privileged, and are solely for the use of the individual to > whom this e-mail is addressed. If you are not the intended recipient or > have received it accidentally, please immediately notify the sender by > reply e-mail and destroy all copies of this email and its attachment. > Please be advised that any unauthorized use, disclosure, distribution or > copying of this email or its attachment is strictly prohibited. > > 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件， > 請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。 >

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Re: [coreboot] BDX-DE PCI init fail
by Hilbert Tu(杜睿哲_Pegatron) 16 Jan '18

16 Jan '18

Hi Zoran, Anyway, thanks. I have learnt a lot from the discussion. Thank you all. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Re: [coreboot] free to good home: minnowmax board(s)
by ron minnich 15 Jan '18

15 Jan '18

aaaaand it's gone, sorry all,Philip got here first ... ron On Mon, Jan 15, 2018 at 11:27 AM ron minnich <rminnich(a)gmail.com> wrote: > anybody want one of these? I have a few but no time to work on them. >

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Re: [coreboot] free to good home: minnowmax board(s)
by my First name is Test And my last Name is iPation 15 Jan '18

15 Jan '18

If no one is interested, I am. > On 15 Jan 2018, at 20:27, ron minnich <rminnich(a)gmail.com> wrote: > > anybody want one of these? I have a few but no time to work on them. > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

1 0

free to good home: minnowmax board(s)
by ron minnich 15 Jan '18

15 Jan '18

anybody want one of these? I have a few but no time to work on them.

1 0

Re: [coreboot] BDX-DE PCI init fail
by Zoran Stojsavljevic 15 Jan '18

15 Jan '18

As my best understanding is, you need to install GRUB Legacy for Legacy (SeaBIOS) to boot. To do this, you need to boot from UEFI BIOS to GRUB2, then to Ubuntu (to install GRUB Legay. 0.97). Please, read: https://ubuntuforums.org/showthread.php?t=1298932 They (GRUB 0.97 abd GRUB 2.0) can co-exist there days, and the result of this is the option in BIOS and Bootable USB called MBR + UEFI mode. SPS stands for: Server Platform Services, and as I understand this, this is layer above ME, managing Servers (BDX-DE is a server). As well as AMT. It belongs to ME part of INTEL platform. Sorry I could not help you more. No time. Zoran _______ On Mon, Jan 15, 2018 at 9:51 AM, Hilbert Tu(杜睿哲_Pegatron) <Hilbert_Tu(a)pegatroncorp.com> wrote: > Hi Zoran, > > That information was dumped when I use SeaBIOS as coreboot's payload. I don't know why it is related to GRUB_legacy. If I use GRUB2 as payload, it just hangs there. I am still struggling on this :( > By the way, I saw following message in the log. Should I choose NodeManager Mode? Do you know what's different? > >>>[SPS] SiliconEnabling Mode > > > Thanks. > -Hilbert > > -----Original Message----- > From: Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com] > Sent: Thursday, January 11, 2018 7:27 PM > To: Hilbert Tu(杜睿哲_Pegatron) > Cc: Zeh, Werner; coreboot(a)coreboot.org; David Hendricks > Subject: Re: [coreboot] BDX-DE PCI init fail > >> Booting from Hard Disk... >> Booting from 0000:7c00 > > It is booting from the thirty second Kbyte of HDD (sector 62, sector 0 > is MBR), where the beginning of GRUB Legacy is placed/implanted, > called core.img or similar name. > > https://wiki.archlinux.org/index.php/GRUB_Legacy > > Well, you have succeed, by all means. Problem solved! ;-) > > Zoran > _______ > > On Thu, Jan 11, 2018 at 12:06 PM, Hilbert Tu(杜睿哲_Pegatron) > <Hilbert_Tu(a)pegatroncorp.com> wrote: >> Hi Werner, >> >> Thanks for your information. It works but still has same result. The result is like following. My usb stick is ext4fs formatted and has kernel and rootfs files. I wish SeaBIOS can give me a shell like Grub so that I can specify how to boot next. Or should I create a bootable usb stick? >> >> >> ============= PEIM FSP is Completed ============= >> >> Returned from FspNotify(EnumInitPhaseReadyToBoot) >> Jumping to boot code at 000ff06e(7eff6000) >> CPU0: stack: 00128000 - 00129000, lowest used address 00128b00, stack used: 1280 bytes >> entry = 0x000ff06e >> lb_start = 0x00100000 >> lb_size = 0x0012d6d0 >> buffer = 0x7ed66000 >> SeaBIOS (version rel-1.10.2-0-g5f4c7b1) >> BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: (GNU Binutils) 2.28 >> Found mainboard Intel Camelback Mountain CRB >> Relocating init from 0x000e3860 to 0x7ef74cc0 (size 49824) >> Found CBFS header at 0xffe00138 >> multiboot: eax=0, ebx=0 >> Found 25 PCI devices (max PCI bus is 05) >> Copying SMBIOS entry point from 0x7efc1000 to 0x000f7140 >> Copying ACPI RSDP from 0x7efd2000 to 0x000f7110 >> Using pmtimer, ioport 0x408 >> WARNING - Timeout at tis_wait_sts:160! >> WARNING - Timeout at tis_wait_sts:160! >> Scan for VGA option rom >> XHCI init on dev 00:14.0: regs @ 0xfea00000, 21 ports, 32 slots, 32 byte contexts >> XHCI protocol USB 2.00, 8 ports (offset 1), def 3001 >> XHCI protocol USB 3.00, 6 ports (offset 16), def 1000 >> XHCI extcap 0xc1 @ 0xfea08040 >> XHCI extcap 0xc0 @ 0xfea08070 >> XHCI extcap 0x1 @ 0xfea0846c >> EHCI init on dev 00:1a.0 (regs=0xfea18020) >> EHCI init on dev 00:1d.0 (regs=0xfea19020) >> WARNING - Timeout at i8042_flush:71! >> ebda moved from 9f000 to 9e800 >> AHCI controller at 00:1f.2, iobase 0xfea17000, irq 5 >> Found 0 lpt ports >> Found 2 serial ports >> XHCI no devices found >> Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 >> Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 >> USB MSC vendor='Generic-' product='Multiple Reader' rev='1.11' type=0 removable=1 >> ehci_wait_td error - status=80e42 >> Initialized USB HUB (0 ports used) >> USB MSC blksize=512 sectors=30777344 >> Initialized USB HUB (1 ports used) >> All threads complete. >> Scan for option roms >> Running option rom at c000:0003 >> Running option rom at c100:0003 >> Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0 >> Searching bootorder for: /pci@i0cf8/pci-bridge@2,2/*@0,1 >> >> Press ESC for boot menu. >> >> WARNING - Timeout at tis_wait_sts:160! >> Searching bootorder for: HALT >> drive 0x000f70c0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=30777344 >> Space available for UMB: c2000-efb00, f6960-f70c0 >> Returned 184320 bytes of ZoneHigh >> e820 map has 9 items: >> 0: 0000000000000000 - 000000000009e800 = 1 RAM >> 1: 000000000009e800 - 00000000000a0000 = 2 RESERVED >> 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED >> 3: 0000000000100000 - 000000007efae000 = 1 RAM >> 4: 000000007efae000 - 0000000090000000 = 2 RESERVED >> 5: 00000000feb00000 - 00000000feb10000 = 2 RESERVED >> 6: 00000000feb80000 - 00000000fef00000 = 2 RESERVED >> 7: 00000000ff000000 - 0000000100000000 = 2 RESERVED >> 8: 0000000100000000 - 0000000280000000 = 1 RAM >> enter handle_19: >> NULL >> Booting from Hard Disk... >> Booting from 0000:7c00 >> >> -Hilbert >> >> This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. >> 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

1 0

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coreboot January 2018