coreboot February 2012

coreboot@coreboot.org

34 participants
348 discussions

#95: Run coreboot in VirtualBox
by coreboot 10 Dec '14

10 Dec '14

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

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EHCI debug port finder
by Carl-Daniel Hailfinger 30 May '14

30 May '14

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

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#186: 3com 3c905tx / gpxe boot problem
by coreboot 11 Jan '14

11 Jan '14

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: just because) novice in the field, I encountered some problems with netbooting with coreboot. Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE} respectively. NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy slow! Although loading, the kernel is never able to start itself. Same kernel on HDU is no problem at all (GRUB2) Note: the gpxe-image is on the nic, coreboot payload is seabios. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186> coreboot <http://www.coreboot.org/>

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New patch to review: 49493f5 T60: add volume CMOS setting
by gerrit＠coreboot.org 28 Jan '13

28 Jan '13

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12 -gerrit

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#131: New flashrom motherboard support
by coreboot 18 Sep '12

18 Sep '12

#131: New flashrom motherboard support ---------------------------------+------------------------------------------ Reporter: anonymous | Owner: somebody Type: enhancement | Status: new Priority: trivial | Milestone: Going mainstream Component: flashrom | Version: v2 Keywords: flashrom asus | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Did not know where I should put this but the bugtracker seemed like the right place. I tried flashrom and it could not detect my chip on my ASUS P5ND2-SLI Deluxe motherboard. The board has a SST49LF004B flash chip and after enforcing the right chip flashrom seems to work fine. {{{ # ./flashrom -V -f -r -c SST49LF004A/B test Calibrating delay loop... 796M loops per second, 100 myus = 201 us. OK. No coreboot table found. WARNING: No chipset found. Flash detection will most likely fail. Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x21, id2 0x5e, id1 parity violation No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Probing for SST SST49LF004A/B, 512 KB: Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Force reading flash... done. }}} This should probably apply to the P5ND-SLI board, too. What do you need from me for adding autodetection of this board/chip? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/131> coreboot <http://www.coreboot.org/>

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Re: [coreboot] how to delete symbol link created at compile time
by She, Kerry 18 Jul '12

18 Jul '12

> -----Original Message----- > From: Marc Jones [mailto:marcj303@gmail.com] > Sent: Tuesday, October 18, 2011 10:39 AM > To: Stefan Reinauer > Cc: She, Kerry; coreboot > Subject: Re: [coreboot] how to delete symbol link created at compile time > > On Mon, Oct 17, 2011 at 4:44 PM, Stefan Reinauer > <stefan.reinauer(a)coreboot.org> wrote: > > * Marc Jones <marcj303(a)gmail.com> [111016 10:10]: > >> >> > I have created 2 devicetree file : > >> >> > > >> >> > devicetree_f15.cb for platform with family 15 CPU > >> >> > > >> >> > devicetree_f10.cb for platform with family 10 CPU > >> >> > > >> >> > > >> >> > > >> >> > I changed the makefile to create a symbol link "devicetree.cb" > link to > >> >> > devicetree_f10.cb or devicetree_f15.cb at compile time. > >> >> > > >> >> > The problem is that I can't delete the symbol link when make > >> >> > clean/distclean. > >> > > >> > Please fix the problem by using one device tree for both platforms. > > > >> Stefan, > >> > >> Can you explain your thoughts on how that would work? Can we put a #if > >> in the devicetree.cb? It uses the c precompiler? It requires different > >> CPU files/device locations. We can try it next week. > > > > Usually the way this is handled in coreboot is that there is one socket > > that binds together all CPU types. Then in the device tree only the > > socket type is specified, and code for both CPUs is pulled in. > > Maybe we need something like a socket for northbridge code, since the > > northbridge now lives in the CPU? > > > > It seems like a bad idea to have to recompile your BIOS because you > > change the CPU. We did a lot of nastyness with K8 and Fam10, but we > > should find a better way to do this for future chipsets/CPUs. > > > Yes, we are discussing how the AGESA code would work. The socket > decision is rather complicated as we need a way to handle multiple > calls with the same names (function point tables etc). I think that > there may be a solution within AGESA, but the device tree may still be > a problem as the CPUs have different HT link numbering. This makes it > hard to have the same device tree layout for the same socket. Because of the function name conflict, put cpu code of 2 families together would not compile. We need to dig into AGESA more to figure out a solution. As for the devicetree problem, following text is the devicetree difference in detail: --- devicetree_fam10.cb 2011-08-15 15:00:14.426692437 +0800 +++ devicetree_fam15.cb 2011-08-15 15:00:14.426692437 +0800 @@ -16,19 +16,17 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -chip northbridge/amd/agesa/family10/root_complex +chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on - chip cpu/amd/agesa/family10 - device lapic 0x10 on end + chip cpu/amd/agesa/family15 + device lapic 0x20 on end end end device pci_domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro - chip northbridge/amd/agesa/family10 # CPU side of HT root complex - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on end # link 2 - device pci 18.0 on # link 3, SB on socket0 link 2, on internal Node0 Link 3 + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on end # Link 0 + device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1) chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600

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#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E)
by coreboot 24 Mar '12

24 Mar '12

#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E) ---------------------------------+------------------------------------------ Reporter: Jan@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ I've tried updating the BIOS of a Tomcat n3400B (S2925-E). The update itself worked fine, but the MAC addresses of the onboard NVidia-Gigabit Ethernet chips were set to bogus values (66:55:44:33:22:11 or something like that) afterwards. Restoring the old flash backup worked. This does not happen with the official update tool from Tyan. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/135> coreboot <http://www.coreboot.org/>

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Set top box update
by Gregg Levine 11 Mar '12

11 Mar '12

Hello! Amazon tells me that there are now two people selling their Akimbo boxes. Perhaps I'll definitely buy one. And Joe here is the linked page which contains a reference to the STB kit from Intel: http://cerberus.teamhackaday.com/?p=3 It turns out that it comes up right below the description for the device. It seems the only thing nonstandard about it is the crappy BIOS that Akimbo insisted on. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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Re: [coreboot] libpayload alloc() gcc 4.6.2 bug?
by Patrick Georgi 02 Mar '12

02 Mar '12

Am 28.02.2012 23:06, schrieb Marc Jones: > I found this bug building tint with libpayload. libpayload is built > with defconfig and using the same coreboot crosstools gcc. The bug > happens in the first call to alloc() when the first header of the > first region is installed. The header memory location is checked, > found to be 0, and then loaded with the header. The bug is that the > original value of the location is used after the memory was updated. > It should have been reloaded. It is pretty easy to see in the > disassembly below. workaround: mark setup() __attribute__((noinline)) The proper fix is to clean up the various casts so the aliasing based optimizations in gcc do the right thing. Patrick

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Patch merged into coreboot/master: 5326f5c gitconfig: Add lint-stable as pre-commit hook
by gerrit＠coreboot.org 01 Mar '12

01 Mar '12

the following patch was just integrated into master: commit 5326f5c7e6a9d56bc0f030c81651050d6d280150 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 25 19:52:45 2012 +0100 gitconfig: Add lint-stable as pre-commit hook When configuring the tree with "make gitconfig", a pre-commit hook is installed that runs the stable lint tests. If any of these fail, the log is visible (on stdout) and the commit is aborted. Change-Id: Ie2a26e87f466c63b24db8dca8827057a18ac7f3e Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/682 for details. -gerrit

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coreboot February 2012