Hello,
Recently I have decided to give a try to coreboot for first time and
flashed my ThinkPad T420, but a few weeks ago I have swapped the USB
controller on the back, next to the battery, with a FireWire/USB controller
(40GAB5809-G200) from another T420. Nothing special, since some models have
been shipped like this. The controller is no longer accessible on my laptop.
It seems like it may have been detected as an "SD Host Controller" or not
detected at all. I will probably have to remove the chip and compare the
output of lspci and lshw. If nothing has changed, I will probably have to
return the stock BIOS and compare the results again. I have also tried to
load some of the firewire kernel modules manually with modprobe.
The operating systems I have tested so far are Arch Linux and Xubuntu. I am
willing to provide more useful information, boot into a fresh Windows
install, flash the chip again or whatever else. Correct me if I am wrong,
but if I go back to the stock BIOS, the next time I flash, I will have to
disassemble the laptop again and otherwise I must be fine with flashing
internally, right?
Thanks
Dear coreboot community,
I have encountered problem with silicon init on Tiger Lake RVP platform.
I managed to resolve previous issues with memory initialization and now
hitting an error with TCSS init. The FSP asserts on IOM ready check,
which is 0. The configuration has selected CONFIG_USE_INTEL_FSP_MP_INIT
(without MP PPI service).
When the CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI is
selected, then the FSP-S returns smoothly (at least from one of the
phases I guess) and resets after clearing MCEs in coreboot's CPU init:
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
Clearing out pending MCEs
Setting up local APIC...
apic_id: 0x00 done.
Turbo is available but hidden
Turbo is available and visible
CPU #0 initialized
Initializing CPU #2
Initializing CPU #6
Initializing CPU #7
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
Clearing out pending MCEs
Cl (tutaj następuje reset)
Any ideas what may cause these issues? When I clean this up, I will
upstream the DDR4 variant of TGL UP3 RVP.
--
Michał Żygowski
Firmware Engineer
https://3mdeb.com | @3mdeb_com
Hi all,
that we had another case of a missing-device-below-chip in a devicetree
made me write a patch for `sconfig` [1]. Now that it's checking for the
issue, that uncovered a few (31) more cases [2] that need to be fixed
before upstream can benefit from the patch. Please help to fix the
devicetrees.
Note, `sconfig` currently doesn't print the file name of override trees,
e.g. when it says
SCONFIG mainboard/.../devicetree.cb
line 10: end: syntax error
that might as well refer to line 10 in an override tree.
Nico
[1] https://review.coreboot.org/c/coreboot/+/51119
[2] https://qa.coreboot.org/job/coreboot-gerrit/164572/
Failing boards:
board.AMD_BILBY
board.AMD_CEREME
board.AMD_MANDOLIN
board.GETAC_P470
board.GOOGLE_BRYA0
board.GOOGLE_FALCO
board.GOOGLE_PEPPY
board.GOOGLE_WOLF
board.KONTRON_BSL6
board.LENOVO_R500
board.LENOVO_T430S
board.LENOVO_T431S
board.LENOVO_T520
board.LENOVO_T530
board.LENOVO_W530
board.LENOVO_X1
board.LENOVO_X220
board.LENOVO_X220I
board.LENOVO_X220_MRC_BIN
board.LENOVO_X220_OPTION_TABLE_DEBUG_TPM_EXTENDED_CBFS
board.LENOVO_X230
board.LENOVO_X230S
board.LENOVO_X230T
board.LENOVO_X301
board.LENOVO_X60
board.RODA_RK886EX
board.SIEMENS_BOXER26
Hi!
We developed our CRB motherboard on Intel Atom C3538 (4 core) Denverton_NS processor. Faced with the following problem.
For part of processors with the same SKU and steping (Atom C3538), lapic #4 in devicetree.cb needed (95%), and for the other part lapic #0 (5%).
Intel confirmed that it might be so and that's okay ...
Part of devicetree.cb:
device cpu_cluster 0 on
device lapic 4 on end
end
If we do not specify lapic id correctly in devicetree.cb, freeBSD OS does not BOOT (Unix like).
FreeBSD BOOT log (set lapic #4 in devicetree.cb but need lapic #0):
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
APIC: Found table at 0x7f769420
APIC: Using the MADT enumerator.
MADT: Found CPU APIC ID 0 ACPI ID 0: enabled
SMP: Added CPU 0 (AP)
MADT: Found CPU APIC ID 4 ACPI ID 1: enabled
SMP: Added CPU 4 (AP)
MADT: Found CPU APIC ID 12 ACPI ID 2: enabled
SMP: Added CPU 12 (AP)
MADT: Found CPU APIC ID 16 ACPI ID 3: enabled
SMP: Added CPU 16 (AP)
MADT: Found CPU APIC ID 24 ACPI ID 4: enabled
SMP: Added CPU 24 (AP)
Copyright (c) 1992-2019 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 11.3-RELEASE #0 r349754: Fri Jul 5 04:45:24 UTC 2019
root@releng2.nyi.freebsd.org:/usr/obj/usr/src/sys/GENERIC amd64
FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0)
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
Table 'HPET' at 0x7f7694a0
ACPI: No SRAT table found
PPIM 0: PA=0xa0000, VA=0xffffffff82410000, size=0x10000, mode=0
VT(vga): resolution 640x480
Preloaded elf kernel "/boot/kernel/kernel" at 0xffffffff8226d000.
Calibrating TSC clock ... TSC clock: 2100071708 Hz
CPU: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz (2100.07-MHz K8-class CPU)
Origin="GenuineIntel" Id=0x506f1 Family=0x6 Model=0x5f Stepping=1
Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
Features2=0x4ff8ebbf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,RDRAND>
AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM>
AMD Features2=0x101<LAHF,Prefetch>
Structured Extended Features=0x2294e283<FSGSBASE,TSCADJ,SMEP,ERMS,NFPUSG,MPX,PQE,RDSEED,SMAP,CLFLUSHOPT,PROCTRACE,SHA>
Structured Extended Features3=0xac000400<MD_CLEAR,IBPB,STIBP,ARCH_CAP,SSBD>
XSAVE Features=0xf<XSAVEOPT,XSAVEC,XINUSE,XSAVES>
IA32_ARCH_CAPS=0x69<RDCL_NO,SKIP_L1DFL_VME>
VT-x: Basic Features=0xda0400<SMM,INS/OUTS,TRUE>
Pin-Based Controls=0xff<ExtINT,NMI,VNMI,PreTmr,PostIntr>
Primary Processor Controls=0xfff9fffe<INTWIN,TSCOff,HLT,INVLPG,MWAIT,RDPMC,RDTSC,CR3-LD,CR3-ST,CR8-LD,CR8-ST,TPR,NMIWIN,MOV-DR,IO,IOmap,MTF,MSRmap,MONITOR,PAUSE>
Secondary Processor Controls=0x1d6fff<APIC,EPT,DT,RDTSCP,x2APIC,VPID,WBINVD,UG,APIC-reg,VID,PAUSE-loop,RDRAND,VMFUNC,VMCS,XSAVES>
Exit Controls=0xda0400<PAT-LD,EFER-SV,PTMR-SV>
Entry Controls=0xda0400
EPT Features=0x6334141<XO,PW4,UC,WB,2M,1G,INVEPT,AD,single,all>
VPID Features=0xf01<INVVPID,individual,single,all,single-globals>
TSC: P-state invariant, performance statistics
DTLB: 4k pages, fully associative, 32 entries
Data TLB: 4 KBytes pages, 4-way set associative, 512 entries
Instruction TLB: 4 KByte pages, fully associative, 48 entries
DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
L2 cache: 2048 kbytes, 16-way associative, 64 bytes/line
real memory = 8589934592 (8192 MB)
Physical memory chunk(s):
0x0000000000010000 - 0x000000000009bfff, 573440 bytes (140 pages)
0x0000000000100000 - 0x00000000001fffff, 1048576 bytes (256 pages)
0x0000000002400000 - 0x000000007f74ffff, 2100625408 bytes (512848 pages)
0x0000000100000000 - 0x000000027012efff, 6175256576 bytes (1507631 pages)
avail memory = 8220336128 (7839 MB)
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
Table 'HPET' at 0x7f7694a0
ACPI: No DMAR table found
Event timer "LAPIC" quality 600
ACPI APIC Table: <COREv4 COREBOOT>
WARNING: L1 data cache covers less APIC IDs than a core
0 < 1
Package ID shift: 5
L2 cache ID shift: 2
L1 cache ID shift: 1
Core ID shift: 1
panic: AP #4 (PHY# 0) failed!
cpuid = 0
KDB: stack backtrace:
#0 0xffffffff80b4c4b7 at kdb_backtrace+0x67
#1 0xffffffff80b054ce at vpanic+0x17e
#2 0xffffffff80b05343 at panic+0x43
#3 0xffffffff80f752a4 at native_start_all_aps+0x344
#4 0xffffffff80f74c4f at cpu_mp_start+0x2ef
#5 0xffffffff80b5cb76 at mp_start+0xa6
#6 0xffffffff80aa0b48 at mi_startup+0x118
#7 0xffffffff8031202c at btext+0x2c
Uptime: 1s
Other Linux OS boot but show an incorrect number of cores (5 instead of 4) and offline processor cores appear (see log).
Ubuntu 18.04 LTS (GNU/Linux 4.15.0-20-generic x86_64)
# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 5
On-line CPU(s) list: 0,2-4
Off-line CPU(s) list: 1
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 95
Model name: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz
Stepping: 1
CPU MHz: 2097.502
CPU max MHz: 2100.0000
CPU min MHz: 800.0000
BogoMIPS: 4200.00
Virtualization: VT-x
L1d cache: 24K
L1i cache: 32K
L2 cache: 2048K
NUMA node0 CPU(s): 0,2-4
What can be done in this situation? How to make a universal version of devicetree.cb?
Hello Coreboot Developers!
First, I want to say that it is really a joy to work with Coreboot. The code is
well-written and of high-quality. :)
I'm currently trying to get Tianocore EDK2 running as a Coreboot payload in Qemu
and meeting with limited success, though. I have a working configuration for the
qemu q35 target. Building it for and running it with the 440fx/piix4 chipset
results in the crash below.
Is PIIX4 supported with Coreboot/EDK2 or should this configuration be avoided?
I also appreciate any pointers in how to debug a situation like this. It looks
like the crash happens in EDK2. Is there a way to get an ELF file that objdump
understands, so I can see where in EDK2 code this issue originates from?
BS: BS_PAYLOAD_LOAD run times (exec / console): 64 / 2 ms
Jumping to boot code at 0x008008c0(0x7ff9b000)
!!!! X64 Exception Type - 00(#DE - Divide Error) CPU Apic ID - 00000000 !!!!
RIP - 000000007F92FAB0, CS - 0000000000000038, RFLAGS - 0000000000000202
RAX - 000000007F938C20, RCX - 000000007F938C20, RDX - 0000000000000008
RBX - 0000000000000008, RSP - 000000007FF4B278, RBP - 000000007FF666E0
RSI - 000000007FF65910, RDI - 0000000000000001
R8 - 000000007FF63480, R9 - 0000000000000038, R10 - 000000007F93CF08
R11 - 000000007FF64F08, R12 - 0000000000000000, R13 - 0000000000000080
R14 - 000000007FF66760, R15 - 000000007FAA9118
DS - 0000000000000030, ES - 0000000000000030, FS - 0000000000000030
GS - 0000000000000030, SS - 0000000000000030
CR0 - 0000000080010011, CR2 - 0000000000000000, CR3 - 000000007FC01000
CR4 - 0000000000000228, CR8 - 0000000000000000
DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000
DR3 - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400
GDTR - 000000007FBED718 0000000000000047, LDTR - 0000000000000000
IDTR - 000000007F93A018 0000000000000FFF, TR - 0000000000000000
FXSAVE_STATE - 000000007FF4AED0
!!!! Can't find image information. !!!!
Thanks!
Julian
Issue #303 has been reported by Julian Stecklina.
----------------------------------------
Bug #303: qemu: Failure to build TianoCore UefiPayload
https://ticket.coreboot.org/issues/303
* Author: Julian Stecklina
* Status: New
* Priority: Normal
* Assignee:
* Category: build system
* Target version:
----------------------------------------
I'm trying to build Coreboot with the TianoCore payload (CONFIG_TIANOCORE_UEFIPAYLOAD=y). This fails early when building the bundled TianoCore:
~~~
Using EDK2 in-source Basetools
WORKSPACE: /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore
EDK_TOOLS_PATH: /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/BaseTools
CONF_PATH: /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/Conf
Copying $EDK_TOOLS_PATH/Conf/build_rule.template
to /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/Conf/build_rule.txt
Copying $EDK_TOOLS_PATH/Conf/tools_def.template
to /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/Conf/tools_def.txt
Copying $EDK_TOOLS_PATH/Conf/target.template
to /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/Conf/target.txt
Build environment: Linux-5.11.9-200.fc33.x86_64-x86_64-with-glibc2.32
Build start time: 15:10:51, Mar.29 2021
WORKSPACE = /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore
EDK_TOOLS_PATH = /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/BaseTools
CONF_PATH = /home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/Conf
PYTHON_COMMAND = /usr/bin/python3.9
build.py...
: error 000E: File/directory not found in workspace
/home/julian/src/own/coreboot/payloads/external/tianocore/tianocore/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
- Failed -
Build end time: 15:10:51, Mar.29 2021
Build total time: 00:00:00
~~~
I've attached my config and the full build output. I'm building on Fedora 33 on x86_64.
---Files--------------------------------
coreboot-config (20.5 KB)
build.log (90.8 KB)
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Hi Coreboot,
We are from a computer store and we sell computers and laptops with
Linux or Windows or dual boot. For Linux we are many asked for laptops
with coreboot, probably due to the presence of intel ME spyware in the
laptops. So, we are now investigating whether there is a possibility to
offer the laptops with coreboot. Normally we buy our laptops at a
distributor, we have also asked the distributor to have coreboot they
don't know anything about bios/eufi or coreboot. They only deliver the
laptops with the bios/eufi that the manufacturer made it, we can always
ask for a bios update but not for other bios systems like coreboot. We
don't have any contact with the manufacturer or have any contact data. I
know there are laptops of this brand that have coreboot on it, but to
buy directly ar the manufacturer we don't sell enough (i think we must
sell 10.000 laptops in a quarter or more).
My questions:
- We i have installed coreboot, can i also boot Windows 10 or boot in
dual-boot (Windows and Linux)?
- The installation of coreboot is very unclair. I have looking to google
but i don't realy know how can install it.
- Can i install coreboot like we normally flash a bios? (startup with a
efi boot stick and run a batch file, or startup in the bios and do a
bios update directly from the bios with a usb stick with the flash file)
- Or do i need a eeprom programmer or something like that?
- Must itake out the motherboard completely of the laptop?
To work with coreboot it's very important to have a very fast procedure
to install it in mass production. We cannot spell a few hours on each
laptop. It must be a flash file for a model laptop and a other flash
file for a other model laptop. So we can install coreboot on the best
selling models. Startup from a usb-stick, do a flash update wait 5 or 10
minutes and reboot, ... done.
When it's possible in the procudure like above can i get some help to
make the first coreboot flash.
With Kind Regards,
Gert
Issue #302 has been reported by Tim L.
----------------------------------------
Bug #302: You need to be root
https://ticket.coreboot.org/issues/302
* Author: Tim L
* Status: New
* Priority: Normal
* Assignee:
* Category:
* Target version:
----------------------------------------
~~~
# ./intelmetool -m
iopl: Operation not permitted
You need to be root.
# id
uid=0(root) gid=0(root) groups=0(root)
~~~
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Issue #301 has been reported by Paul Menzel.
----------------------------------------
Bug #301: soc/amd: gpio_bank_lib.asl: IASL remarks on inefficient creation of named objects
https://ticket.coreboot.org/issues/301
* Author: Paul Menzel
* Status: New
* Priority: Normal
* Assignee:
* Category:
* Target version:
----------------------------------------
Building amd/majolica, IASL 20200925 shows the remarks below.
```
dsdt.asl 98: Name(BUFF, Buffer(Local0) {})
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.S2BF)
dsdt.asl 188: OperationRegion (GPDW, SystemMemory, Local0, 4)
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.GPRD)
dsdt.asl 201: OperationRegion (GPDW, SystemMemory, Local0, 4)
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.GPWR)
dsdt.asl 298: OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.STXS)
dsdt.asl 312: OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.CTXS)
dsdt.asl 326: OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.GRXS)
dsdt.asl 342: OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.GTXS)
```
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