Have you experienced anything like this while compiling from the branch 4.8.1?
I have a fresh and a ~ 1 year old crossgcc pack, but both are end up
after a make menuconfig ; make -j8 with the same way.
In the latest crossgcc build, I had to apply an include string fix to
binutils and a -Wl,--allow-multiple-definition to the acpica's
$ CC=/usr/bin/gcc make -d -j8
GNU Make 4.3
Built for x86_64-pc-linux-gnu
Copyright (C) 1988-2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Reading makefile 'Makefile'...
Reading makefile '/media/ramdisk/coreboot/util/kconfig/Makefile'
(search path) (no ~ expansion)...
Reading makefile '/media/ramdisk/coreboot/.config' (search path) (no ~
Reading makefile '.xcompile' (search path) (don't care) (no ~ expansion)...
Reading makefile 'toolchain.inc' (search path) (no ~ expansion)...
Reading makefile 'Makefile.inc' (search path) (don't care) (no ~ expansion)...
Skipping submodule '3rdparty/blobs'
Reading makefile 'util/crossgcc/Makefile.inc' (search path) (no ~ expansion)...
Reading makefile 'src/vendorcode/amd/pi/00670F00/Makefile.inc' (search
path) (don't care) (no ~ expansion)...
Segmentation error (core dumped)
$ dmesg | tail -1
[30582.804975] make: segfault at 7fffb5d2dff8 ip
00007fd105838cff sp 00007fffb5d2e000 error 6 in
[30582.804983] Code: 00 00 00 48 3b 1d 51 64 13 00 0f 82 ab 00 00 00
64 8b 04 25 18 00 00 00 85 c0 0f 85 23 01 00 00 48 89 ee 48 8d 3d 01
6d 13 00 <e8> cc e2 ff ff 49 89 c0 48 85 c0 0f 84 c8 00 00 00 48 8b 40
Do you have any ideas? I'm using Arch Linux 5.9 with GCC 10.2
I had a try on another machine with Arch Linux 4.19 LTS@GCC 10.2
I have a kgpe d16 motherboard with coreboot and seabios, and 2 opteron 6282 SE processor with 64 gb of RAM: all the modules are 16 Gb hynix HMT42GR7AFR4C - RD and all are inserted into the orange slots. The problem is, if I add 2 additional modules, inside the last 2 orange slots, the machine doesn't starts and only black screen is shown, no log is detected over COM port. Any suggestion? Maybe another RAM module configuration is needed, because I read that 192 Gb of RAM is possible to obtain (I have followed the official Asus manual for the RAM-Slots configuration)
Thank you very much
I would appreciate any guidance on the proper way to reserve (arbitrary)
DRAM for a MMIO device in coreboot such that the Linux driver for that
device is also able to map the reserved DRAM.
Based on code inspection, my attempt is to add a cbmem entry via
cbmem_alloc and mark that memory as reserved via reserved_ram_resource in
the read_resources operation for the device driver.
static void foo_read_resources(struct device *dev)
const unsigned long size = 0x8000;
buf = cbmem_add(CBMEM_ID_FOO, size);
reserved_ram_resource(dev, 0, ((unsigned long)buf) >> 10, size >>
I can see that the resource is allocated during resource reading.
MMIO: fd110500 resource base *8de82000* size 8000 align 0 gran 0 limit 0
flags f0004200 index 0
I then pass this resource to the linux driver via an ACPI device entry.
const struct cbmem_entry *ce = cbmem_entry_find(CBMEM_ID_FOO);
However, the memory is presented to Linux as "type 16" instead of
"reserved" in the physical RAM map.
[ 0.000000] BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type
[ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff]
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000008de34fff] usable
*[ 0.000000] BIOS-e820: [mem 0x000000008de35000-0x000000008fffffff] type
[ 0.000000] BIOS-e820: [mem 0x0000000090000000-0x00000000cfffffff]
[ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff]
[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000022f33ffff] usable
[ 0.000000] BIOS-e820: [mem 0x000000022f340000-0x000000022fffffff]
The e820 type 16 is unknown to the linux kernel, causing it to mark the
region as busy. This subsequently causes devm_ioremap_resource to fail
when called on the DRAM address from the ACPI device entry.
Looking through the code, it seems that coreboot marks the entire cbmem as
type 16 in bootmem despite my (improper, it would seem) attempt to mark the
ram as reserved. What would be the proper way to reserve (arbitrary) DRAM
for a MMIO device such that the memory is marked as reserved in the BIOS
physical RAM map?
Hello coreboot community!
I would like to formally announce a new project I've been working on for
the last few weeks.
Retroboot is based on coreboot, and today I have made an official
release. This release is available from the https://retroboot.org/ with
ROM images and source code provided. Please read the Retroboot
documentation if you wish to learn how to use them. Support is provided
at the #retroboot IRC channel on Freenode.
Retroboot is a new coreboot distribution, forked from the Libreboot
20160907 build system, but allows binary blobs from coreboot and uses an
up to date version of coreboot. The purpose of Retroboot is to provide
pre-compiled ROM images for any system that coreboot supports.
Retroboot, based on coreboot, provides hardware initialization on
supported x86 computers; it sets up the hardware and boots an operating
system such as GNU+Linux, BSD and Windows.
Retroboot provides an automated build system that compiled coreboot,
GRUB, SeaBIOS and various other required software, with specific
configurations. It provides a completely automated way to build and test
ROM images of coreboot, in various configurations. Each board added to
Retroboot can specify a coreboot version at a specific commit ID from
the coreboot Git repository, and custom patches. It can then be used
with any number of coreboot payloads such as GRUB, SeaBIOS and (planned
for a future release) Tianocore and linuxboot. Read the documentation on
the Retroboot website for more information about each system supported
in the Retroboot build system.
The aim of Retroboot is to make coreboot easy to use. Coreboot is
notoriously difficult to build, and very much not user friendly.
Retroboot provides user focused documentation and professional support
based on years of experience dealing with coreboot. I, Leah Rowe, am the
founder of the Retroboot project and I am also the founder of the
This release, marked beta, released on 28 December 2020, supports the
* ThinkPad X220 (untested at the time of release)
* ThinkPad X230 (tested on a few machines at the time of release)
* ThinkPad X230 Tablet (untested at the time of release, but X230 is
the same board as the X230T, with minor differences, so the X230T
ROMs should work)
* ThinkPad T60 with ATI Mobility Radeon X1400, PCI ID 1002:7145
(tested on one machine at the time of release)
NOTE: /tested/ in this context means that the machine can be observed
booting a Linux kernel. Also, Windows 10 was confirmed to boot on the
X230 with Intel VGA ROM and SeaBIOS payload. (we recommend the use of
free operating systems like GNU+Linux).
For documentation, refer to the accompnying source code release archive.
Documentation is included in that archive. You can also refer to the
documentation hosted directly at https://retroboot.org/ and this is more
recommended due to it being more up to date.
This is a public /beta/ release. The ROM images provided in this release
are NOT guaranteed to boot correctly on your machine. If you install
this, you should make sure that you have SPI flashing equipment (for
flashing 25XX NOR flash) and, ideally, debugging equipment such as EHCI
Extensive testing is required for all of the ROMs in this release, so
user testing is highly encouraged! The plan for Retroboot is to have
long, long periods of /testing/ releases, before versions are marked
stable (similar to how the Debian project operates).
More information about Retroboot can be found on the Retroboot website:
Extensive documentation is provided, including for developers.
I'm currently looking for people to add and maintain boards in
Retroboot. The entire build system is documented here:
And now, a song:
On the Baytrail platform with ALC262 Realtek Codec, HDA Audio is enumerated
as PCI device 00 1b 00,
the verb table is being programmed on HDABAR + command offset.
Using uefi Payload which has PchInit -> DetectAndInitializeAzalia, there
are no Errors in this path, all looks good
Either Beep or Audio speakers fail to work in EFI Shell and also in Ubuntu
aplay -l does not Audio ALC Codec as sound card
what is missing to enumerate, FSP path\SoC Straps are enabled for Audio so
they seem to be fine too
Appreciate for any clues to make HDA to work on a BayTrail Platform
Dear Coreboot community,
I am developing bios for my custom Apollo Lake SoC E3950 mainboard. I got to a point where SeaBios is loaded and awaits to choose a boot option. The problem is that its getting stuck while waiting for timeout or keyboard press (see log attached). I figured out that it is getting stuck on wait_irq() function. In particular, call stack looks like this:
get_keystroke() (int scan_code = get_keystroke(menutime);)
Why can this happen? Is hardware not initialized properly during Coreboot operation or it should be done in SeaBios?
Looks like interrupts from timer and keyboard are not working. I tried loading with FILO payload and keyboard was working Ok except keyboard leds were not working.
There are two/three devices which I would like to run coreboot on, which are variants of devices explicitly supported by coreboot.
These document pages, however, are a little ambiguous as to which variants of the supported devices would work. I seek clarification.
On the page https://doc.coreboot.org/mainboard/asrock/h110m-dvs.html is linked ASRock's information page about the H110M-DVS R2.0. I should like to run coreboot on the H110M-DVS R3.0, as this one is of the mini-DTX form-factor, which the R2.0 is not. Does anyone know if coreboot's H110M-DVS port would function on the R3.0? There is no indication (other than the fact that the doc page links to the R2.0's info) that this would not be the case. Indeed, the documentation page consistently refers to the motherboard as merely the 'H110M-DVS,' without the revision specifier.
Another, related question, is whether the very-similar H110M-DGS would be supported by this coreboot port. http://www.asrock.com/mb/Intel/H110M-DGS/index.asp
Note that the H81M-DGS is supported by coreboot.
On the page https://doc.coreboot.org/mainboard/libretrend/lt1000.html is linked Libretrend's purchase website for their 'Librebox.' Libretrend is, quite sadly, defunct - it was the maker of the 'librebox' which to my knowledge is the sole 'thin mini-ITX' motherboard supported by coreboot. However, Libretrend did not manufacture their own hardware, but instead seemingly ordered it from an external OEM - indeed this OEM is linked to in the coreboot docs. The page for their version of the board is here: http://www.minicase.net/product_LR-i7S65T1.html
Indeed the OEM version, the LR-i7S65T1, looks exactly the same as the Libretrend Librebox.
Would anyone happen to know if the OEM LR-i7S65T1 would be supported by the Libretrend Librebox coreboot port? Or is the hardware between the OEM (minicase) and distributor (libretrend) versions of this board different somehow?
- Daniel C.
Posted this in #coreboot IRC just now
Retroboot is a new build system forked from Libreboot build system. It
provides an automated build system around coreboot, GRUB, SeaBIOS, and
all the other components needed, and provides ROMs for users. it
provides documentation aimed at non-technical users, and user support.
Unlike Libreboot, it allows blobs and includes the 3rdparty repo. It is
a very competent build system and can have *any* coreboot system added
Boards specify a revision aswell, so it's possible to specify older
coreboot revisions if you want to add a board that was removed from
06:12 <unoccupied> https://retroboot.org/ launched yesterday
06:13 <unoccupied> it's a new coreboot distribution. it tries to use the
latest version of coreboot at all times, and provides an automated build
system around coreboot that integrates many other things such as payloads
06:13 <unoccupied> the aim is to provide pre-built ROMs, utilities and
user-friendly documentation, with user-friendly support, but developer
documentation is also provided which explains the entire build system
06:13 <unoccupied> there are no releases yet, just the website and the
git repo, but build instructions are provided.
06:14 <unoccupied> it is a fork of the libreboot 20160907 build system,
with many improvements. i've worked on it non-stop for 2 weeks.
06:14 <unoccupied> it's based on libreboot build system, but allows
blobs from coreboot and includes the 3rdparty repo.
06:14 <unoccupied> it can support any board from coreboot, and i welcome
any and all coreboot users who wish to give it a try!
06:15 <unoccupied> This is build instructions:
06:15 <unoccupied> This is maintenance instructions (shows how to add
new boards and maintain them): https://retroboot.org/docs/maintain/
06:15 <unoccupied> adding boards is basicall: add a config, specify what
payload you want, add whatever customer patches you want. then build!
06:16 <unoccupied> IRC is #retroboot if you wish to discuss development.
though no actual coreboot development is allowed; coreboot dev must be
done in coreboot, with your coreboot work mergede downstream in retroboot
06:16 <unoccupied> enjoy!
06:16 <unoccupied> just thought i'd post this here
And now, a song:
Minifree Ltd, trading as RetroFreedom,
Registered in England, No. 9361826,
VAT No. GB202190462, Registered Office:
19 Hilton Road, Canvey Island, Essex SS8 9QA, UK