I have attached all the log files releated to the dmidecode ectool
inteltool etc. Can you read those out and tell me if it is possible to port
coreboot to my netbook? If it is then how hard will it be?
> SeaBIOS is a legacy BIOS implementation, so no it can't boot UEFI boot media. Likewise, Tianocore is a pure UEFI implementation, and doesn't boot legacy boot media / legacy installed OSes. There should be a way to use SeaBIOS as a CSM for Tianocore, but currently it's not working / not implemented (I tried briefly awhile back but didn't have any luck).
I tried to follow the steps to build tianocore for SeaBIOS https://www.coreboot.org/TianoCore But I get these errors. It says it can't found nmake.exe... Is this should be build on Windows? How to setup the environment?
[dalao@pc tianocore2018]$ git clone --branch UDK2018 https://github.com/tianocore/edk2
Cloning into 'edk2'...
remote: Enumerating objects: 66, done.
remote: Counting objects: 100% (66/66), done.
remote: Compressing objects: 100% (43/43), done.
remote: Total 342725 (delta 35), reused 31 (delta 23), pack-reused 342659
Receiving objects: 100% (342725/342725), 286.48 MiB | 436.00 KiB/s, done.
Resolving deltas: 100% (247240/247240), done.
Updating files: 100% (15636/15636), done.
[dalao@pc tianocore2018]$ cd edk2/
[dalao@pc edk2]$ cd BaseTools
[dalao@pc BaseTools]$ export EDK_TOOLS_PATH=$(pwd)
[dalao@pc BaseTools]$ cd ../
[dalao@pc edk2]$ . ./edksetup.sh BaseTools
[dalao@pc edk2]$ build -p DuetPkg/DuetPkgIa32.dsc
Build environment: Linux-5.4.22-1-MANJARO-x86_64-with-glibc2.2.5
Build start time: 11:48:18, Mar.15 2020
WORKSPACE = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2
ECP_SOURCE = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/EdkCompatibilityPkg
EDK_SOURCE = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/EdkCompatibilityPkg
EFI_SOURCE = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/EdkCompatibilityPkg
EDK_TOOLS_PATH = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/BaseTools
CONF_PATH = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/Conf
POSTBUILD = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/DuetPkg/PostBuild.bat -p DuetPkg/DuetPkgIa32.dsc -b DEBUG -a IA32 -t MYTOOLS --conf=/home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/Conf all
Architecture(s) = IA32
Build target = DEBUG
Toolchain = MYTOOLS
Active Platform = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/DuetPkg/DuetPkgIa32.dsc
Flash Image Definition = /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/DuetPkg/DuetPkg.fdf
Processing meta-data ......... done!
Building ... /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf [IA32]
Building ... /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf [IA32]
Building ... /home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf [IA32]
/bin/sh: Vcbinnmake.exe: command not found
: error 7000: Failed to execute command
Vc\bin\nmake.exe /nologo tbuild [/home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/Build/DuetPkgIA32/DEBUG_MYTOOLS/IA32/MdePkg/Library/BasePcdLibNull/BasePcdLibNull]
: error 7000: Failed to execute command
Vc\bin\nmake.exe /nologo tbuild [/home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/Build/DuetPkgIA32/DEBUG_MYTOOLS/IA32/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull]
: error 7000: Failed to execute command
Vc\bin\nmake.exe /nologo tbuild [/home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/Build/DuetPkgIA32/DEBUG_MYTOOLS/IA32/MdePkg/Library/BaseMemoryLib/BaseMemoryLib]
: error F002: Failed to build module
/home/dalao/T440pCorebooting/tianocoreAsSeabiosPayload/tianocore2018/edk2/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf [IA32, MYTOOLS, DEBUG]
- Failed -
Build end time: 11:48:28, Mar.15 2020
Build total time: 00:00:10
> Personally, given that it's 2020, I'd not bother with legacy-installed OSes (or SeaBIOS) outside of use with emulation or if a special use case demands it. Esp given that it's easy enough to migrate Windows from legacy to UEFI.
I tried the tianocore payload by selecting it and using all default settings. But I can't see anything like the SeaBIOS for me to select the boot media. But it does boot the archlinux in UEFI mode. I'm wondering is this the problem with my display (I have tried both "Use libgfxinit" and "Run VGA Option ROMs" with tianocore) or the tianocore has nothing to display to select boot media?
Mar 15, 2020, 10:08 by matt.devillier(a)gmail.com:
> On Sat, Mar 14, 2020 at 8:33 PM Dalao via coreboot
> <coreboot(a)coreboot.org> wrote:
>> I have just corebooted T440p. Then I noticed some graphic display problems...
>> Firstly I "Use libgfxinit" with "Legacy VGA text mode", insert a usb disk with archlinux's latest install image iso. I can see a text mode of archlinux's start screen.
>> But when I hit enter, it shows some log till "Triggering uevents" and then there is no display...
>> Then I tried "Use libgfxinit" with "Linear "high-resolution" framebuffer". I can see the graphic mode of archlinux's start screen, but again after I hit enter and see some logs, there is no display... Also, the display is not ideal, just at the top left corner not full screen.
>> Also, under this setting, the nvramcui's display becomes bad.
> unfortunately, many legacy bootloaders seem to assume a full array of
> VESA video modes will be available, and fail less than gracefully when
> that's not the case. With libgfxinit there is no ability to change
> video modes -- all that's available is either the native panel
> resolution (high resolution framebuffer) or VGA text mode.
>> Next I included pci8086,0416.rom vbios and tried "Run VGA Option ROMs" with "Legacy VGA text mode". This time, I can't see the archlinux start screen as shown above, there is no display at the beginning. But I can hit the enter blindly. Then after a while I can see archlinux is booting and the first line I can see is "Probing EDD (edd=off to disable)...ok" the archlinux starts ok.
>> Lastly I also tried "Run VGA Option ROMs" with "Set framebuffer graphics resolution" with the default "framebuffer graphics resolution (1024x768 16.8M-color (8:8:8))" (although my T440p's resolution is 1920x1080). Also the Framebuffer mode is changed to "VESA framebuffer". I still can't see archlinux's start screen...
>> How to make everything work like the vendor BIOS? i.e., I can see both the archlinux's start screen and it's booting.
> add the VGA BIOS. set the PCI IDs correctly. Set coreboot display init
> to none, and let SeaBIOS run the VBIOS.
>> How to fix the nvramcui under "high-resolution" framebuffer"?
> will work properly with above settings
>> Also, as for now it appears seabios can't boot UEFI media. Tianocore by default can't boot Linux/Windows installed by legacy method (installed when using seabios). my goal is to add UEFI support through tianocore as seabios payload (or through tianocore's CSM compatibility support module? ). So that it can boot both UEFI installed Windows or legacy installed Windows like the vendor bios can do. How to achieve this?
> SeaBIOS is a legacy BIOS implementation, so no it can't boot UEFI boot
> media. Likewise, Tianocore is a pure UEFI implementation, and doesn't
> boot legacy boot media / legacy installed OSes. There should be a way
> to use SeaBIOS as a CSM for Tianocore, but currently it's not working
> / not implemented (I tried briefly awhile back but didn't have any
> Personally, given that it's 2020, I'd not bother with legacy-installed
> OSes (or SeaBIOS) outside of use with emulation or if a special use
> case demands it. Esp given that it's easy enough to migrate Windows
> from legacy to UEFI.
>> coreboot mailing list -- coreboot(a)coreboot.org
>> To unsubscribe send an email to coreboot-leave(a)coreboot.org
> coreboot mailing list -- coreboot(a)coreboot.org
> To unsubscribe send an email to coreboot-leave(a)coreboot.org
I'm trying to get OpenBSD to install on an x220 Thinkpad with
Coreboot/SeaBIOS but I'm running into two problems: the ethernet device
doesn't work and OpenBSD doesn't detect my HDD. dmesg said em0 wouldn't
load because the EEPROM had an invalid signature. I have no idea why
OpenBSD doesn't see my HDD though. It's strange because everything works
fine under Linux. And I cannot seem to mount a usb drive under the
OpenBSD installer to attach dmesg errors.
I originally posted this as a bug report to bug report mailing list but
Theo said it would be better suited for Coreboot's and wasn't a bug in
I own an Acer Aspire VN7-572G and have not been impressed with its OEM
firmware. After discovering that it does not utilise Intel's Boot Guard
technology, that several Skylake and Kabylake laptops (it has a Skylake
chip, but I read that the platforms are similar) have received successful
coreboot ports and reading the porting guide on the wiki, I figured that I
could give porting coreboot to my laptop a shot.
When I was done, I figured that I had an image that might boot so I flashed
it to my laptop with a Raspberry Pi and a SOIC clip. However, here's what
a) It powers on quietly, as expected;
b) The backlight and power LED light up;
c) The fans spin up to high and then it stays that way. It does nothing
else. The display is dark too.
After 15 minutes and a second attempt, I figured that I could no longer
blame anything on a long first boot-up and gave up and flashed back to
Now, in all honesty I should have tried first without cleaning Intel ME but
I find it so much more likely that I did something wrong than that cleaning
ME was the sole problem.
Can anyone advise me on how to continue? My code is here:
With the help from reddit, it works now! The reason is I need to remove the code added by this patch.
https://review.coreboot.org/c/coreboot/+/38723/6/src/mainboard/lenovo/t440p… This patch is for dGPU, my model does not have dGPU. I didn't thought it would affect my model, but removed it Win10 works both using SeaBIOS or Tianocore.
There are some issues with Win10:
1, The first thing I notice is there is no sound output. The system speaker device present in vendor BIOS is missing in coreboot:
2, Some FN-keys (FN-F4, Fn-F7 to F12) does not work.
3, Card reader's subsystemid is wrong and driver can't be installed.
4, Two more devices which were not present in vendor BIOS but are present in coreboot, and these driver can't not be installed:
High Definition Audio Controller PCI\VEN_8086&DEV_8C20&SUBSYS_220E17AA&REV_05\3&B1BFB68...
PCI Data Acquisition and Signal Processing Controller PCI\VEN_8086&DEV_0C03&SUBSYS_00000000&REV_06\3&B1BFB68...
5, There is a Diagnostic Policy Service kept running.
2020年3月28日 14:54 来自 coreboot(a)coreboot.org:
> I have almost tried everything these days trying to boot Windows 10 using T440p with coreboot, but still haven't succeed.
> I had created my Windows 10 installer usb by writing the en_windows_10_business_editions_version_1909_updated_jan_2020_x64_dvd_e9cb5542.iso to usb drive through Rufus, and checked this usb works on a T420 with coreboot. But this usb does not work on T440p.
> I have tried SeaBIOS, Tianocore, and with/without VGA BIOS but still not work.
> When using SeaBIOS without VGA BIOS, I can see a loading bar at the bottom but then hanging there.
> When using SeaBIOS with VGA BIOS, the backlight is on but the screen shows nothing.
> I tried extract data.vbt from vendor BIOS and replaced the one from source with it, still not work.
> I did see one post on reddit mentioned that he had been able to boot Windows 10. > https://www.reddit.com/r/coreboot/comments/enor0h/t440p_tianocore_and_windo…
> I was wondering is my hardware different from others' T440p? Then I tried cherry-pick this patch (git fetch > https://review.coreboot.org/coreboot> refs/changes/90/30890/10 && git cherry-pick FETCH_HEAD) and using autoport to generate source of my T440p. Then I compared it with masters' source, but there is not much difference.
> I tried changed CPU and RAM but still not work.
> Since I make a fresh install of Windows on the T440p, I tried install it on T420 and then change the hard disk to T440p. It still does not work.
> When I use Tianocore, the circle stopped spin and hangs at "Preparing Automatic Repair":
> Sometimes it hangs shows a BSOD of "MACHINE CHECK EXCEPTION" But there is no further information > https://imgur.com/HKio1QY> (I tried to find if there are mce error logs under linux using rasdaemon but I get nothing > https://wiki.archlinux.org/index.php/Machine-check_exception> ) I also checked C:\Windows\minidump to see if there are BSOD dumps but there is none.
> I almost out of idea, I will attach all my files, original BIOS (a modded one with ME cleaned, advanced menu unlocked, and whitelist unlocked), auto port generated logs and sources, and the mrc.bin, data.vbt, defconfig, and also my build coreboot.rom. > https://mega.nz/#!TNlCFKjA!rXDhP5K4S8FZpSif8Ntj-NUGKML4kFYtwAG_70XTpsU
> Could anyone help me with this? Could anyone successfully using T440p to boot Windows share the steps you did it and your config or your coreboot.rom (last 4MB)?
Hi Michal, hi Matt,
On 15.03.20 06:41, Matt B wrote:
> You probably want to speak with Nico. He's a libgfxinit expert afaik.
thanks for the heads up :)
> On Wed, Mar 11, 2020 at 9:45 AM Michal Zygowski <michal.zygowski(a)3mdeb.com>
>> Particularly I would like to implement Braswell support for native
>> graphics init with libgfxinit.
Angel is also looking forward to Braswell support. He mentioned it as a
possible summer-of-code stretch goal (after Bay Trail support), IIRC.
But applications are not written yet (start tomorrow).
> I see the programming manuals from Intel
>> are in place:
Alas, this is a pitfall for Braswell. The only part that matters for
libgfxinit (information about the display engine) is 100% scrubbed
away. If you look into the `Display` chapter, it only contains legacy
VGA registers and audio verbs, nothing about display at all. And if you
search for any of "hdmi", "lvds", "mipi", "dsi", or "lane" in the
`Register` chapter: nothing :-/
So for Braswell, the only public information source I know is the Linux
driver i915. It's the one exception btw. All other chips have a proper
`Display` chapter. Hence also the idea to add Bay Trail support first.
Even if it turns out to be much different, we could at least tell if
Brasswell is closer to Bay Trail or the newer Haswell/Apollo Lake
>> What do I need to implement a new microarchitecture in libgfxinit? Where
>> to start and what should I focus on?
This may get a little longer... but I knew I'll have to write it down
In Ada, the code is organized in so called `packages`. In the way they
are used in libgfxinit, one can simply see them as compilation units.
Each package has a specification (.ads) file with declarations and a
body (.adb) with code. Much like a header and a c file. Packages form
a hierarchy and the name of the file has to reflect the package name,
including its parents (stupid, imho).
Libgfxinit has two major mechanisms in place to support different
1. Alternative implementations of packages. These are organized in
sub-directories (also because every alternative package body has
to have the same file name). For instance, we have different
implementations for the package `HW.GFX.GMA.Connectors` in g45/,
ironlake/, haswell_shared/ (the latter is shared with all newer
generations since Haswell).
Having alternative implementations of packages also means we can't
build one binary that supports all generations. Luckily, we don't
have to, so far :)
2. Configuration flags that are tested in shared code. Much like we
have `if (CONFIG(FOO_BAR))` in coreboot, we have `if Config.Foo_Bar
then` in libgfxinit.
All these flags are gathered in a single package `HW.GFX.GMA.Config`
which keeps conditions on specific hardware generations in a central
place. The file, `hw-gfx-gma-config.ads.template`, is pre-processed
with some sed-foo (see `common/Makefile.inc`). The comment from
`hw-gfx-gma-config.ads.template:99` on explains some of the rea-
How much code sharing makes sense depends on the similarity to other
hardware generations. I wouldn't be surprised if Bay Trail and Braswell
end up using the g45/ code (no PCH and probably pre DDI which was intro-
duced with Haswell), but I don't know that yet.
Some more about the central packages:
HW.GFX* (excluding HW.GFX.GMA*)
There's some vendor-agnostic code around. Mostly for DP training and
This exposes the primary interface (procedure Update_Outputs())
and contains the overall control flow for setting up displays.
Update_Outputs() takes a list of configurations for each graphics
pipeline (up to three) and will try to set things up according to
Assuming a pipe is unconfigured, roughly the following steps are
performed (by procedure Enable_Output()):
* Optionally select a link configuration (e.g. for DP, how many lanes at
* Allocate a PLL for the pixel/DP clock.
* Try to train the selected link configuration (if there is none, the
loops simply run once):
- Prepare output connectors (Pre_On)
- Enable the graphics pipeline (On)
- Finalize the output-connector configuration (Post_On)
This usually doesn't need changes for new hardware.
HW.GFX.GMA.Pipe_Setup* (formerly Display_Controller)
At the heart of the display engine is the pipe setup. Here we configure
the framebuffer format (how to interpret bytes from DRAM), image pro-
cessing (e.g. scaling) and the `Transcoders` that turn the image into
a continuous stream of bits (including blank times) for a given pixel
clock. IOW, everything from the framebuffer to a modeline.
This was called `Display_Controller` earlier (probably for historical
Linux reasons) and is still inside `hw-gfx-gma.adb` (easy to fix, but
I didn't care to so far).
It's mostly configured by flags from the `Config` package. Configu-
ration of scalers is often implemented very differently, but most of
it didn't change much over the years.
The `Connectors` package dispatches the Pre_On() and Post_On() calls
(before and after configuring the graphics pipeline) to sub-packages
for the individual connector types.
This is a bit subtle. In a sense, `Connectors` reflect the outputs of
the CPU package. In the first generations with a PCH (Ironlake including
Sandy and Ivy Bridge) the CPU didn't have actual display outputs (like
VGA, LVDS, HDMI etc.) but only links to the PCH which contained the
final outputs. Later, the final outputs went back onto the CPU die. So
we have three very different versions of this package:
* g45/ outputs are in the GMCH (or CPU if one would add Bay Trail,
it shouldn't matter).
* ironlake/ FDI links in the CPU and (most) outputs in the PCH.
* haswell_shared/ newer outputs (DDI) in the CPU (no legacy interfaces
like VGA/LVDS, and HDMI/DP configuration changed since g45/).
If none of these match the hardware to be added, one would have to
write a new one.
Usually there are some similarities but often changes between hardware
This started with some setup for generation specific things that didn't
find another place. Newer generations have configurable clocks and can
turn individual parts of the display engine on and off. Older ones often
just have to report a pre-set Core Display Clock (CDClk).
To wrap it up, `Power_And_Clocks` and `PLLs` most often need changes for
new hardware. Followed by `Connectors` if these changed significantly,
but most often one can add some code controlled by `Config` flags here.
And, not to forget, all flags in the `Config` package need to be checked
how they should be set for the new hardware.
>> Haven't written anything in SPARK/Ada yet. It will be a new adventure
>> for me.
Can be fun but can also be exhausting ;) Depends much on how you can
cope with nagging compilers and related tools.
For some time now I've been trying to port my laptop with no luck, yet.
Here's what I did:
• I recovered all the log's from the system, as per
Motherboard_Porting_Guide and coreboot-collector.
• Took apart my laptop and dumped eeproms via soldering off, it
appears I have w25q80dv - 8mbit and w25q64fv - 64mbit. I made sure the
dumps are valid, doublechecked via diff and purged the eeproms, system
booted normally when I flashed the dumps back.
• I made an amature coreboot config based on Mimoja's Razer Blade
Stealth (2016) H2U which is now merged. I failed in adapting
devicetree.cb and left it as is. The laptop showed no signs of life
(dead PB and no lights) after externally flashing w25q64fv - 64mbit
with coreboot combined with original Descriptor and stripped down ME
via nconfig (probably should not have done that for 1st boot). Flashed
the dumps back, no bork just yet =)
• I have yet to create a position on Gerrit.
P.S. not including the eeprom dumps, too heavy for a public mailing
list. Will send on demand.
I would be glad to receive any help, please do guide me.
I am new to coreboot build environment and need your help in using gdb with coreboot.
I want to use gdb to take a closer look at the stages in coreboot and the order they are executed in. I also want to single step through the code to see what functions are being called in each stage and during transition from one stage to another. Firstly, I am not even sure if gdb works during transition. Does it?
These are the steps I followed:
1. First I set up the coreboot environment by following this tutorial. https://doc.coreboot.org/tutorial/part1.html. (I also enabled Gdb Wait by going to Debugging menu in coreboot's configuration.)
2. Then I ran the image on qemu
$ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -s -S
3. In another terminal, I started gdb and entered the following command
$ target remote localhost:1234
4. From here, I am able to single step using 'si' but I am not able to set a breakpoint using 'break' at say romstage.c or hardwaremain.c.
I get the following error:
''No symbol table is loaded. Use the "file" command.
Make breakpoint pending on future shared library load? (y or [n])''
Can anyone tell me where I went wrong?
I have almost tried everything these days trying to boot Windows 10 using T440p with coreboot, but still haven't succeed.
I had created my Windows 10 installer usb by writing the en_windows_10_business_editions_version_1909_updated_jan_2020_x64_dvd_e9cb5542.iso to usb drive through Rufus, and checked this usb works on a T420 with coreboot. But this usb does not work on T440p.
I have tried SeaBIOS, Tianocore, and with/without VGA BIOS but still not work.
When using SeaBIOS without VGA BIOS, I can see a loading bar at the bottom but then hanging there.
When using SeaBIOS with VGA BIOS, the backlight is on but the screen shows nothing.
I tried extract data.vbt from vendor BIOS and replaced the one from source with it, still not work.
I did see one post on reddit mentioned that he had been able to boot Windows 10. https://www.reddit.com/r/coreboot/comments/enor0h/t440p_tianocore_and_windo…
I was wondering is my hardware different from others' T440p? Then I tried cherry-pick this patch (git fetch https://review.coreboot.org/coreboot refs/changes/90/30890/10 && git cherry-pick FETCH_HEAD) and using autoport to generate source of my T440p. Then I compared it with masters' source, but there is not much difference.
I tried changed CPU and RAM but still not work.
Since I make a fresh install of Windows on the T440p, I tried install it on T420 and then change the hard disk to T440p. It still does not work.
When I use Tianocore, the circle stopped spin and hangs at "Preparing Automatic Repair":
Sometimes it hangs shows a BSOD of "MACHINE CHECK EXCEPTION" But there is no further information https://imgur.com/HKio1QY (I tried to find if there are mce error logs under linux using rasdaemon but I get nothing https://wiki.archlinux.org/index.php/Machine-check_exception) I also checked C:\Windows\minidump to see if there are BSOD dumps but there is none.
I almost out of idea, I will attach all my files, original BIOS (a modded one with ME cleaned, advanced menu unlocked, and whitelist unlocked), auto port generated logs and sources, and the mrc.bin, data.vbt, defconfig, and also my build coreboot.rom. https://mega.nz/#!TNlCFKjA!rXDhP5K4S8FZpSif8Ntj-NUGKML4kFYtwAG_70XTpsU
Could anyone help me with this? Could anyone successfully using T440p to boot Windows share the steps you did it and your config or your coreboot.rom (last 4MB)?
Firstly, I want to introduce myself. I'm Jan Dabros and I'm working for
Semihalf - embedded system company based in Poland. I am a big fan of
coreboot and the idea of open firmware in general, that's why would really
like to contribute to this project. Let's see how it goes :)
My proposal is to start unit testing coreboot codebase to some possible
extent, in order to improve its reliability, prepare subsystem for enabling
quick tests and to make test-driven-development possible. Hopefully this
makes sense to (at least some) of you.
For this purpose, it's necessary to select some C unit test framework -
unless we want to create something completely new. I have done evaluation
of couple of such libraries and described its results in the document 
along with my selected candidate and implementation proposal. This may be a
good starting point for a discussion about what framework do you think fit
the most and how unit testing may be applied to coreboot codebase.
Together with above doc, I also created a simple example of unit test and
sent it for review . Commit message comprises steps for running it.
Any comments and remarks are very appreciated, both to the doc and the
code. Thanks in advance!