March 2005 - coreboot - mail.coreboot.org

Re: [PROPOSAL] enhanced table dumping

by YhLu

About APIC and ACPI. Some chipset has problems with apic and the workaround must to be used with acpi BIOS. YH

14 years, 3 months

3
2
0 0

[LinuxBIOS] New version of ROM posting app

by Jon Smirl

I put two new posting apps, a vm86 version and emu86 version out on: bk://mesa3d.bkbits.net/rom Get klibc from: http://kernel.org/pub/linux/libs/klibc/ Install it somewhere and build it. You need to make a link to the kernel source in the top level klibc directory. In this directory make a link from the klibc-xxx directory to klibc. Both projects will then build. v86bios uses vm86 to run the rom post uses emu86 Use an environment variable to pick the card to be acted on: export DEVPATH=/bus/pci/devices/0000:01:00.0 vm86 is 20K non-debug emu86 is 40K non-debug Currently they don't use Ben's VGA arbiter which isn't ready yet. When finished these app will automatically be triggered on driver load as part of the hotplug process. The source to vm86 is from the linux BIOS project where is has been worked on to make it substantially smaller. I like to keep everyone on the same source code base if possible. Once we get these cleaned up and working I'm hoping to get them added to the klibc project. Once in klibc, klibc is schedule to go into the kernel sooner or later. They are both partially working but fail part way through the posting process. I've been playing with them a couple of days and I can't figure out why they are failing. They are both failing for different reasons. Can anyone help? -- Jon Smirl jonsmirl(a)gmail.com

14 years, 6 months

7
29
0 0

RE: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC address in linux bios

by YhLu

Should be in BIOS.because different MB use different MAC assigned in Factory. But in MB design, it should use another SEEPROM to store that. So the BIOS or NIC get it. YH > -----Original Message----- > From: Li-Ta Lo [mailto:ollie@lanl.gov] > Sent: Thursday, March 31, 2005 11:11 AM > To: Tao Liu > Cc: LinuxBIOS > Subject: Re: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC > address in linuxbios > > On Thu, 2005-03-31 at 15:29 +0800, Tao Liu wrote: > > Hello, > > > > this patch sets 8111NIC's mac. The 48-bit mac address is > saved in OEM > > ROM, in nic_init() the driver gets the mac address through register > > oem_mac_offset, and copy it to 8111NIC's PADR register. > > > > > > Is it store is it own serial EEPROM or in the same ROM as > BIOS? If it is stored in it won EEPROM, this code sould be > in the kernel driver than BIOS. > > Ollie > > > > diff -Nur > > > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c > > freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c > > --- > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd81 > 11_nic.c 2004-10-21 > > 18:44:04.000000000 +0800 > > +++ > freebios2-20050305-0000/src/southbridge/amd/amd8111/amd811 > 1_nic.c 2005-03-31 > > 12:50:56.000000000 +0800 > > @@ -6,20 +6,99 @@ > > #include <device/pci.h> > > #include <device/pci_ids.h> > > #include <device/pci_ops.h> > > +#include <delay.h> > > #include "amd8111.h" > > > > +#undef writel > > +#undef writeb > > +#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val)) > > +#define writeb(val,addr) (*(volatile uint8_t *)(addr) = (val)) > > > > +#define CMD3 0x54 > > +#define PADR 0x160 > > + > > +typedef enum { > > + VAL3 = (1 << 31), /* VAL bit for byte 3 */ > > + VAL2 = (1 << 23), /* VAL bit for byte 2 */ > > + VAL1 = (1 << 15), /* VAL bit for byte 1 */ > > + VAL0 = (1 << 7), /* VAL bit for byte 0 */ > > +}VAL_BITS; > > + > > +typedef enum { > > + /* VAL3 */ > > + ASF_INIT_DONE_ALIAS = (1 << 29), > > + /* VAL2 */ > > + JUMBO = (1 << 21), > > + VSIZE = (1 << 20), > > + VLONLY = (1 << 19), > > + VL_TAG_DEL = (1 << 18), > > + /* VAL1 */ > > + EN_PMGR = (1 << 14), > > + INTLEVEL = (1 << 13), > > + FORCE_FULL_DUPLEX = (1 << 12), > > + FORCE_LINK_STATUS = (1 << 11), > > + APEP = (1 << 10), > > + MPPLBA = (1 << 9), > > + /* VAL0 */ > > + RESET_PHY_PULSE = (1 << 2), > > + RESET_PHY = (1 << 1), > > + PHY_RST_POL = (1 << 0), > > +}CMD3_BITS; > > + > > +static void nic_init(struct device *dev) { > > + struct southbridge_amd_amd8111_config *conf; > > + struct resource *resource; > > + void *mmio; > > + unsigned char *oem_mac_addr; > > + int i; > > + > > + conf = dev->chip_info; > > + resource = find_resource(dev, PCI_BASE_ADDRESS_0); > > + mmio = (void *)(unsigned long)resource->base; > > + > > + /* Hard Reset PHY */ > > + printk_debug("Reseting PHY... "); > > + if (conf->phy_lowreset) { > > + writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3); > > + } else { > > + writel(VAL0 | RESET_PHY, mmio + CMD3); > > + } > > + mdelay(15); > > + writel(RESET_PHY, mmio + CMD3); > > + printk_debug("Done\n"); > > + > > + /* Set MAC address */ > > + printk_debug("Mac Addr "); > > + oem_mac_addr = (unsigned char *)(ROM_OEM_START + > conf->oem_mac_offset); > > + for (i = 0; i < 6; i++) { > > + printk_debug("%02X%c", oem_mac_addr[i], i == 5 > ? '\n' : ':'); > > + writeb(oem_mac_addr[i], mmio + PADR + i); > > + } > > +} > > + > > +static void lpci_set_subsystem(device_t dev, unsigned vendor, > > +unsigned device) { > > + pci_write_config32(dev, 0xc8, > > + ((device & 0xffff) << 16) | (vendor & 0xffff)); } > > + > > +static struct pci_operations lops_pci = { > > + .set_subsystem = lpci_set_subsystem, }; > > + > > static struct device_operations nic_ops = { > > .read_resources = pci_dev_read_resources, > > .set_resources = pci_dev_set_resources, > > .enable_resources = pci_dev_enable_resources, > > - .enable = amd8111_enable, > > - .init = 0, > > + .init = nic_init, > > .scan_bus = 0, > > + .enable = amd8111_enable, > > + .ops_pci = &lops_pci, > > }; > > > > static struct pci_driver nic_driver __pci_driver = { > > .ops = &nic_ops, > > .vendor = PCI_VENDOR_ID_AMD, > > - .device = 0x7462, > > + .device = PCI_DEVICE_ID_AMD_8111_NIC, > > }; > > diff -Nur > > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h > > freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h > > --- > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111 > /chip.h 2004-10-21 > > 18:44:04.000000000 +0800 > > +++ > freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h > 2005-03-31 > > 12:49:32.000000000 +0800 > > @@ -5,6 +5,8 @@ > > { > > unsigned int ide0_enable : 1; > > unsigned int ide1_enable : 1; > > + unsigned int phy_lowreset : 1; > > + unsigned long oem_mac_offset; > > }; > > > > struct chip_operations; > > > > > -- > Li-Ta Lo <ollie(a)lanl.gov> > Los Alamos National Lab > > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

14 years, 6 months

2
1
0 0

[LinuxBIOS] [PATCH] small fixes

by Tao Liu

Hello, this patch fixes two small program errors, one is loop condition always true, the other is return 1 in void type function. --- freebios2-20050305-0000-orig/src/drivers/generic/debug/debug_dev.c 2004-12-11 04:50:42.000000000 +0800 +++ freebios2-20050305-0000/src/drivers/generic/debug/debug_dev.c 2005-03-31 13:54:00.000000000 +0800 @@ -35,9 +35,10 @@ static void print_pci_regs_all(void) { struct device *dev; - unsigned char bus, device, function; + unsigned int bus; + unsigned char device, function; - for(bus=0; bus<=256; bus++) { + for(bus=0; bus<=0xff; bus++) { for(device=0; device<=0x1f; device++) { for (function=0; function<=7; function++){ unsigned devfn; --- freebios2-20050305-0000-orig/src/devices/emulator/biosemu.c 2005-01-20 07:19:26.000000000 +0800 +++ freebios2-20050305-0000/src/devices/emulator/biosemu.c 2005-03-31 13:24:26.000000000 +0800 @@ -122,7 +122,8 @@ void do_int(int num) case 0x6D: if (getIntVect(num) == 0x0000) { printk_debug("un-inited int vector\n"); - return 1; + //return 1; + ret = 1; } if (getIntVect(num) == 0xFF065) { //ret = int42_handler(); -- Liu Tao

14 years, 6 months

2
2
0 0

[LinuxBIOS] Mount linux elf image for netboot as loop device

by Tony Cheng

I used mkelfImage to combined Linux Kernel 2.4.20 and initrd into elf image for netboot. then I try to use "mount -o loop my_elfImage" to mount this image as a loop device. I get a error message like this: #mount: you must specify the filesystem type I have specified the my_elfImage in /etc/fstab as this: (I add a line in fstab because mount ask me to do that) /root/loop/my_elfImage /root/loop/tl auto noauto,owner,kudzu 0 0 I changed the file type from auto to ext3 and etc. but nothing work for me. Could anybody kindly help me on this? Thanks tony

14 years, 6 months

2
2
0 0

[LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC address in linuxbios

by Tao Liu

Hello, this patch sets 8111NIC's mac. The 48-bit mac address is saved in OEM ROM, in nic_init() the driver gets the mac address through register oem_mac_offset, and copy it to 8111NIC's PADR register. diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c --- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c 2004-10-21 18:44:04.000000000 +0800 +++ freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c 2005-03-31 12:50:56.000000000 +0800 @@ -6,20 +6,99 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <delay.h> #include "amd8111.h" +#undef writel +#undef writeb +#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val)) +#define writeb(val,addr) (*(volatile uint8_t *)(addr) = (val)) +#define CMD3 0x54 +#define PADR 0x160 + +typedef enum { + VAL3 = (1 << 31), /* VAL bit for byte 3 */ + VAL2 = (1 << 23), /* VAL bit for byte 2 */ + VAL1 = (1 << 15), /* VAL bit for byte 1 */ + VAL0 = (1 << 7), /* VAL bit for byte 0 */ +}VAL_BITS; + +typedef enum { + /* VAL3 */ + ASF_INIT_DONE_ALIAS = (1 << 29), + /* VAL2 */ + JUMBO = (1 << 21), + VSIZE = (1 << 20), + VLONLY = (1 << 19), + VL_TAG_DEL = (1 << 18), + /* VAL1 */ + EN_PMGR = (1 << 14), + INTLEVEL = (1 << 13), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), + /* VAL0 */ + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), +}CMD3_BITS; + +static void nic_init(struct device *dev) +{ + struct southbridge_amd_amd8111_config *conf; + struct resource *resource; + void *mmio; + unsigned char *oem_mac_addr; + int i; + + conf = dev->chip_info; + resource = find_resource(dev, PCI_BASE_ADDRESS_0); + mmio = (void *)(unsigned long)resource->base; + + /* Hard Reset PHY */ + printk_debug("Reseting PHY... "); + if (conf->phy_lowreset) { + writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3); + } else { + writel(VAL0 | RESET_PHY, mmio + CMD3); + } + mdelay(15); + writel(RESET_PHY, mmio + CMD3); + printk_debug("Done\n"); + + /* Set MAC address */ + printk_debug("Mac Addr "); + oem_mac_addr = (unsigned char *)(ROM_OEM_START + conf->oem_mac_offset); + for (i = 0; i < 6; i++) { + printk_debug("%02X%c", oem_mac_addr[i], i == 5 ? '\n' : ':'); + writeb(oem_mac_addr[i], mmio + PADR + i); + } +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0xc8, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, + .init = nic_init, .scan_bus = 0, + .enable = amd8111_enable, + .ops_pci = &lops_pci, }; static struct pci_driver nic_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7462, + .device = PCI_DEVICE_ID_AMD_8111_NIC, }; diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h --- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h 2004-10-21 18:44:04.000000000 +0800 +++ freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h 2005-03-31 12:49:32.000000000 +0800 @@ -5,6 +5,8 @@ { unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; + unsigned int phy_lowreset : 1; + unsigned long oem_mac_offset; }; struct chip_operations; -- Liu Tao

14 years, 6 months

2
1
0 0

[LinuxBIOS] [PATCH 1/2] src/config/Options.lb: Add OEM ROM section definitions

by Tao Liu

Hello, this patch adds following options, for the use of OEM ROM section, eg: onboard PCI device's BIOS in boot ROM or MAC address saved in boot ROM ROM_TOTAL_SIZE: the total size of boot ROM ROM_OEM_SIZE: the size of boot ROM used by OEM_ROM section ROM_SIZE: the size of boot ROM used by LinuxBIOS ROM_OEM_START: OEM_ROM start address OEM ROM exists in the low address end of boot ROM, so default ROM_OEM_SIZE = 0 default ROM_SIZE = ROM_TOTAL_SIZE - ROM_OEM_SIZE default ROM_OEM_START = 0xffffffff - ROM_TOTAL_SIZE + 1 OEM devices should know the offset of their data in OEM ROM, so they can visit their data at address (ROM_OEM_START + oem_my_data_offset) to use OEM ROM, one should define ROM_TOTAL_SIZE and ROM_OEM_SIZE in mainboard's Options.lb file. this patch won't break mainboards which defines ROM_SIZE and don't mentions ROM_TOTAL_SIZE and ROM_OEM_SIZE. --- freebios2-20050305-0000-orig/src/config/Options.lb 2005-01-15 05:54:16.000000000 +0800 +++ freebios2-20050305-0000/src/config/Options.lb 2005-03-30 20:49:16.000000000 +0800 @@ -190,11 +190,29 @@ export used comment "Default fallback image size" end -define ROM_SIZE +define ROM_TOTAL_SIZE default none format "0x%x" export used - comment "Size of your ROM" + comment "Size of your boot ROM" +end +define ROM_OEM_SIZE + default 0 + format "0x%x" + export used + comment "Size of your ROM used by OEM vendors" +end +define ROM_OEM_START + default {0xffffffff - ROM_TOTAL_SIZE + 1} + format "0x%x" + export used + comment "OEM ROM start location" +end +define ROM_SIZE + default {ROM_TOTAL_SIZE - ROM_OEM_SIZE} + format "0x%x" + export used + comment "Size of your ROM used by LinuxBIOS" end define ROM_IMAGE_SIZE default 65535 -- Liu Tao

14 years, 6 months

2
1
0 0

[LinuxBIOS] USB 2.0 booting

by Jun OKAJIMA

Hello Linux BIOS developers. As far as I understand, current Linux BIOS does not boot from USB memory stick if it is USB 2.0, Right?. But, I also understand that EHCI (= USB 2.0) can also work as UHCI/OHCI( = USB1.1). Then, if I use a M/B which has EHCI and put USB 2.0 stick to it, and put Linux kernel supports EHCI driver there. And if I boot it with Etherboot/FILO with USB 1.1 support in this case, can it boot as USB 1.1? and can I switch USB mode to 2.0 after booting? What I want to do is like this. 1. Boot linux kernel by Etherboot/FILO/USB1.1 from USB stick. 2. Reading Linux kernel itself is slow. But after that, it works with 2.0 performance?. --- Okajima, Jun. Tokyo, Japan.

14 years, 6 months

2
1
0 0

[LinuxBIOS] Athlon64 939

by YhLu

The Athlon 64 939 support dual channel. but in the test in s2865 with d0 Athlon64 939 in LinuxBIOS, it only work with one DIMM in socket 1. weird.... the same code with Opteron d0 .... YH > -----Original Message----- > From: YhLu > Sent: Wednesday, March 30, 2005 3:09 PM > To: ebiederman(a)lnxi.com; Kevin O'Connor > Cc: linuxbios(a)openbios.org > Subject: RE: [LinuxBIOS] Re: Error in compiling STPC Consumer > > Eric, > > the code in raminit.c is_opteron will treat my athlon 64 > (939) as Opteron too. > > YH > > static int is_opteron(const struct mem_controller *ctrl) { > /* Test to see if I am an Opteron. > * FIXME Testing dual channel capability is correct for now > * but a beter test is probably required. > */ > #warning "FIXME implement a better test for opterons" > uint32_t nbcap; > nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); > return !!(nbcap & NBCAP_128Bit); } > > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

14 years, 6 months

3
2
0 0

[LinuxBIOS] Simulator to test BIOS

by Ramesh Chhaba

Hi all , I want any simulator that i can use as virtual machine to test my romimage without burning it in to actual chip. I there is any such software or alternative . Thank you Ramesh Chander Yahoo! India Matrimony: Find your life partneronline.

14 years, 6 months

2
1
0 0

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2005