coreboot March 2005

coreboot@coreboot.org

51 participants
93 discussions

[LinuxBIOS] [PATCH] amd8111_nic init
by Tao Liu 18 Mar '05

18 Mar '05

Hello, This patch handles the phy reset pin's polarity. AMD8111's PHY_RESET pin is active high by default, but some PHY requires active low reset signal. On mainboards which use 8111's PHY_RESET pin to reset PHY the bios must select the correct PHY_RST_POL for 8111, otherwise the PHY chip would always be held in reset state and can't be accessed by software. I sent a similar patch several months ago but no response on this list, would someone who has cvs commit right check and apply it? -- Tao diff -Naur freebios2-20050305-0000/src/include/device/pci_ids.h freebios2-20050305-0000-lt/src/include/device/pci_ids.h --- freebios2-20050305-0000/src/include/device/pci_ids.h 2004-12-11 04:50:43.000000000 +0800 +++ freebios2-20050305-0000-lt/src/include/device/pci_ids.h 2005-03-07 15:43:04.000000000 +0800 @@ -418,6 +418,7 @@ #define PCI_DEVICE_ID_AMD_8111_SMB 0x746a #define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b +#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 #define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 #define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450 #define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451 diff -Naur freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/amd8111_nic.c --- freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c 2004-10-21 18:44:04.000000000 +0800 +++ freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/amd8111_nic.c 2005-03-18 16:17:04.000000000 +0800 @@ -8,18 +8,82 @@ #include <device/pci_ops.h> #include "amd8111.h" +#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val)) +#define CMD3 0x54 + +typedef enum { + VAL3 = (1 << 31), /* VAL bit for byte 3 */ + VAL2 = (1 << 23), /* VAL bit for byte 2 */ + VAL1 = (1 << 15), /* VAL bit for byte 1 */ + VAL0 = (1 << 7), /* VAL bit for byte 0 */ +}VAL_BITS; + +typedef enum { + /* VAL3 */ + ASF_INIT_DONE_ALIAS = (1 << 29), + /* VAL2 */ + JUMBO = (1 << 21), + VSIZE = (1 << 20), + VLONLY = (1 << 19), + VL_TAG_DEL = (1 << 18), + /* VAL1 */ + EN_PMGR = (1 << 14), + INTLEVEL = (1 << 13), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), + /* VAL0 */ + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), +}CMD3_BITS; + +static void nic_init(struct device *dev) +{ + struct southbridge_amd_amd8111_config *conf; + struct resource *resource; + void *mmio; + + conf = dev->chip_info; + resource = find_resource(dev, PCI_BASE_ADDRESS_0); + mmio = (void *)resource->base; + + /* Hard Reset PHY */ + printk_debug("Reseting PHY... "); + if (conf->phy_lowreset) { + writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3); + } else { + writel(VAL0 | RESET_PHY, mmio + CMD3); + } + mdelay(15); + writel(RESET_PHY, mmio + CMD3); + printk_debug("Done\n"); +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0xc8, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, + .init = nic_init, .scan_bus = 0, + .enable = amd8111_enable, + .ops_pci = &lops_pci, }; static struct pci_driver nic_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7462, + .device = PCI_DEVICE_ID_AMD_8111_NIC, }; diff -Naur freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/chip.h --- freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h 2004-10-21 18:44:04.000000000 +0800 +++ freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/chip.h 2005-03-07 16:12:27.000000000 +0800 @@ -5,6 +5,7 @@ { unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; + unsigned int phy_lowreset : 1; }; struct chip_operations;

2 1

[LinuxBIOS] Re: Does a System BIOS do some kind of initialization on a Ethernet card?
by Peter Stuge 17 Mar '05

17 Mar '05

This is completely off-topic for the LinuxBIOS mailing list. On Thu, Mar 17, 2005 at 09:54:18AM -0600, DongWook Kim wrote: > I have a problem with activating the ethernet in my embedded linux. > I am using realtek 8100c(It is one of the realteck's 8139 compatible NIC). > > Our company designed a board and a some kind of system BIOS for our board. > And after I installed a linux on the board with the BIOS and upload the > firmware of the realtek 8100c into its rom. The only ROM I see close to the 8100C is the EEPROM that contains configuration and MAC address. This should only have to be written to once. [..] > > Does my System BIOS need some kind of initialization on the > realteck 8100c? Besides normal PCI init required for all PCI devices I very much doubt that. But speak with your hardware department and your supplier. And check out the chip data sheet. //Peter

1 0

[LinuxBIOS] cutting over
by Ronald G. Minnich 17 Mar '05

17 Mar '05

linuxbios(a)openbios.org is the new mailing list. I will shut the old one down in a day or two. Hope you call get this. ron

5 7

[LinuxBIOS] Linux vs. Open?
by Dale Harris 17 Mar '05

17 Mar '05

So this is likely a dumb question. But what is the difference between LinuxBIOS and OpenBIOS? Dale Harris

11 21

[LinuxBIOS] STPC support
by Ramesh Chhaba 17 Mar '05

17 Mar '05

Hi All , I want to use linuxbios for STPC Atlas . Weather it is supported or what I have to do to use linux bios for STPC Atlas. Thank You Ramesh Chander Yahoo! India Matrimony: Find your life partneronline.

1 0

[LinuxBIOS] RE: Tyan K7M (S2498) for AMD Geode? NX CPU
by YhLu 16 Mar '05

16 Mar '05

I will get one to play. > -----Original Message----- > From: Bari Ari [mailto:bari@onelabs.com] > Sent: Tuesday, March 15, 2005 5:29 PM > To: linuxbios(a)openbios.org > Cc: YhLu > Subject: Tyan K7M (S2498) for AMD Geode NX CPU > > Tyan has two new Geode boards that use the VIA KN400A, VT8237 > SB chipset, Winbond W83697HF LPC I/O chip and Realtek ALC655 > AC'97 codec. > One version even offers Gb ethernet. Any news on LinuxBIOS > support or help with support for it? > > http://www.tyan.com/products/html/tomcatk7m_spec.html > > -Bari >

1 0

[LinuxBIOS] Tyan K7M (S2498) for AMD Geode™ NX CPU
by Bari Ari 16 Mar '05

16 Mar '05

Tyan has two new Geode boards that use the VIA KN400A, VT8237 SB chipset, Winbond W83697HF LPC I/O chip and Realtek ALC655 AC'97 codec. One version even offers Gb ethernet. Any news on LinuxBIOS support or help with support for it? http://www.tyan.com/products/html/tomcatk7m_spec.html -Bari

1 0

[LinuxBIOS] Re: Flash package images [was: ELAN SC520]
by Peter Stuge 15 Mar '05

15 Mar '05

On Mon, Mar 14, 2005 at 11:47:42PM -0700, David Hendricks wrote: > Is there a way to save those images of the flash chips somewhere on > openbios.org? The images are a great idea, but I'm not sure if > hotlinking to other sites is a good idea. I suppose if someone > bitches or they take the image down, the wiki can be changed easily > as well. Right. There are ways to upload to the wiki, but that naturally requires proper copyright things. I found it easier just to link to some good images that I found through google images. If only I could find my digital camera I'd be happy to take some pictures and donate them to the wiki, but it's been missing for a while. :( Anyone else with loose flash parts, please beat me to it. If you don't have wiki write access, just send me the images and I'll upload them. //Peter

1 0

[LinuxBIOS] about the epia M10000
by Amaury Jacquot 14 Mar '05

14 Mar '05

hey guys. I am running a raid5 array out of an epia M10000, netbooted via the official bios' PXE. I have a problem, in that I have to power cycle the thing to get the PXE thing to boot. if I use the "reboot" command, the PXE fails with Exiting PXE boot rom or something similar. would replacing the original bios with LinuxBios solve my problem ?

1 0

Asus TX97-E
by Michal Szwaczko 08 Mar '05

08 Mar '05

Hello, I'm tracking the list, CVS, listening to some really kind folks at Freenode's #openbios (Stepan et al) for some time now, but still did't find a working Asus TX97 configuration. To the point: I have an Asus TX97-_E_ which seems to be really diferent from the one that is claimed supported in the v1 tree (tx97-le) The difference - from what I can gather not being a hw level programmer - is the cache chips and superIO. I tried many many config options but still, no serial output, the board is just plain dead after flashing. Has anyone tried/succeeded in getting this board to work? Or can anyone point my mistakes if it should be working and isn't because I might be making some fundamental errors? The cache chips are two of tmtech t35l6432a-60 The IO chip is: Winbond w83877af The config I use is here: <URL:http://m.wirelabs.net/mb-config> And a little modified (for a different superio)tx97le/Config: <URL:http://m.wirelabs.net/Config> The image builds ok, but I am not sure if it is even workable at minimum with those options on that motherboard. There was a discussion some time ago on this list about similar problem, but I don't think I could track down any voice from the developers about this. Can anyone shed some light on this matter? Point me to any direction? Thanks -- [ .O. | Michał 'Mikey' Szwaczko | GPG Key#:0x653CBD53 ] [ ..O | Developer/Troubleshooter | GNU Generation Now! ] [ OOO | There's no spoon. ]

1 0

← Newer
1
2
3
4
5
6
7
8
9
10
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2005