coreboot March 2019

coreboot@coreboot.org

49 participants
47 discussions

OpenBSD won't install on an x220 Thinkpad with Coreboot

by Robert Milton

I'm trying to get OpenBSD to install on an x220 Thinkpad with Coreboot/SeaBIOS but I'm running into two problems: the ethernet device doesn't work and OpenBSD doesn't detect my HDD. dmesg said em0 wouldn't load because the EEPROM had an invalid signature. I have no idea why OpenBSD doesn't see my HDD though. It's strange because everything works fine under Linux. And I cannot seem to mount a usb drive under the OpenBSD installer to attach dmesg errors. I originally posted this as a bug report to bug report mailing list but Theo said it would be better suited for Coreboot's and wasn't a bug in OpenBSD.

5 months, 2 weeks

Optiplex 790 now has preliminary support by coreboot

by Taiidan＠gmx.com

https://review.coreboot.org/21774 In case anyone else didn't notice - It is a sandy/ivy system with IOMMU. This is great and should help get coreboot in to the corporate user world.

8 months, 2 weeks

BUG: Seabios choose the wrong option rom when two are available

by akjuxr3＠dismail.de

In this thread https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/FTHN… we found a bug in seabios. Its choosing the wrong option rom in the case when for example on a Intel G41 board you have the internal Intel GPU and have added a external PCIe GPU. Then coreboot switches over to the external GPU for the graphical output but seabios use the option rom for the Intel G41 GPU. In case of x4x/G41 this results in no ability to have a graphical boot mode and thus its not possible to boot some linux live images. In the linked thread a workaround is been found: "In the "Devices" menu of coreboot, set "Graphics initialization" to "None" ". This breaks the functionality to have coreboot output with the internal GPU when you pull out the PCIe GPU. The switch should happen automaticly and without the need to recompile/reconfigure coreboot. Changes like https://review.coreboot.org/c/coreboot/+/18504 was made to make this happen. Would be great if this seabios issue could be fixes. Thanks!

1 year, 3 months

IME: Alternatives for large companies?

by Philipp Stanner

Recently I had an interesting discussion with a system administrator who is responsible for several hundred PCs, Routers etc. His argument was: Imagine it would take you 15 minutes to install a patch on a computer (all windows machines of course...). If your company has 1000 computers and you send one admin to install the patches, it will take him >31 work days, working 8h a day. That's why, he said, companies are interested in software allowing them to install stuff on the OS / hard drive remotely through the firmware I, not dealing with large networks, had never thought about it this way. But it does make a lot of sense to me, it's about real money (as usual). So I guess that's indeed a huge reason why Intel and AMD created Frankenstein, running below UEFI and Kernel. It probably doesn't explain so much why it's necessary to disallow you switching IME off or why it needs control about absolutely everything, but that's a different story. So I'm wondering: What would you do about this reality? Could there be a different solution other than software in Ring -1 having its sausage fingers on everything? Sure, the programmers in a company could install their stuff on their own, but the office folks, the HR and PR guys and the lawyers? Hmm. And whether we like it or not, even awesome companies almost exclusively supply their employees with windows machines and they just demand solutions allowing their IT-departements to fix everything as cheap and as easy as possible P.

1 year, 3 months

Shubhendra - GSoC proposal Inquiry about "Port payloads to RISC-V"

by Shubhendra Singhal

Dear Sir/Ma'am, I am Shubhendra Pal Singhal, currently third year in Computer Science at NIT Trichy, India. I wish to apply for Google Summer of Code. I looked into the profile of coreboot 4.9 and found out the project idea "*Port payloads to ARM, AArch64, MIPS or RISC-V*" to be very interesting. I have worked in the similar field on *RISCV architecture at IIT Madras where I helped in porting real time OS eChronos*, on RISCV architecture. I will be undergoing a *project in Embedded systems offered by USC Los Angeles in solving the SAT Solvers using OS and Digital Logic*. Furthermore, I am currently working on a *long term project with under Prof. N.Ramasubramanium on the AI chip* where we are trying to solve the processing speeds by efficiently reducing the number of writes in the cache for faster access. I am also *undergoing Microcontrollers and Microprocessors* as my core subject in my current semester and have already* undergone OS, Real time Systems* in my B.Tech IV semester. I have included my further details in my Linkedin : * <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/>https://www.linkedin.com/in/ <https://www.linkedin.com/in/>shubhendra-singhal-7378a9131/* I want to contribute to the open source community in the field of Operating Systems and this can prove to be an excellent platform for gaining experience in field of systems. This opportunity can pave my career, towards applied research in the field of Systems. *While browsing through the link, I saw the mailing list assigned for the project. It would be very useful if you could guide me as to what is expected in the project proposal and how can I serve the open source community in the best possible way. *Any guidance would be very useful and I hope to receive a reply soon. Thanking you for your time and consideration. Regards Shubhendra Pal Singhal National Institute Of Technology, Trichy, India Phone number : +91 9787888015 Email-id : shubhendrapalsinghal(a)gmail.com Linkedin : <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/> https://www.linkedin.com/in/shubhendra-singhal-7378a9131/

1 year, 5 months

FSP2.0 DQ byte map

by Michal Zygowski

Hi, I am wondering what is the format of CPU-DRAM DQ byte map for FSP-M configuration. Typically there are 64 DQ lanes per non-ECC SODIMM/DIMM (correct me if I'm wrong) for DDR4 for example. But the DQ map is an 2x12 array, so I assume 12 bytes for each channel (why not 8 bytes?). My questions are: 1. Why there are more bytes in array than DQ lanes? 2. How should I define the DQ map? Does 0xFF or 0x00 mean 1 to 1 mapping? 3. Some FSP2.0 mainboards have values like 0x0F and 0xF0 in their mappings which looks like 1 byte swap, but there are also 0xCC and 0x33. What is the difference? The DQS mapping is clear to me (rather obvious as there are only 8 DQS which matches the 2x8 array). I know about 3 Rcomp resistors of the chipset and what they are for, but what RcompTarget is? In the code I can see function `mainboard_fill_rcomp_strength_data` and begin to wonder what rcomp strength is (not Rcomp Target?). How to correctly fill RcompTarget FSP-M configuration? Any tips and pointers appreciated. Regards, -- Michał Żygowski Firmware Engineer http://3mdeb.com | @3mdeb_com

1 year, 5 months

GSoC 2019 - HW bringup

by Alex James

Hello, I am a student interested in contributing to coreboot as part of GSoC 2019. I have seen the ideas list on the documentation page, and I am considering working on fixing issues reported by Coverity Scan, and maybe additional work on firmware RE tools. However, I would like to know if ports to new mainboards/systems would be an acceptable project. I have an Ivy Bridge desktop (Gigabyte GA-Z77X-UD5H) as well as a Arrandale laptop (HP Pavilion dv7), and I am interested in porting coreboot to these platforms. I do have some experience with UEFI programming in C (as well as x86(_64) ASM). Thank you. Alex James

1 year, 6 months

Help with devicetree.cb

by nic.c3.14＠gmail.com

Hello! I'm new to coreboot, and I'm trying to port it to the Dell Latitude E6400. It is fairly similar to the Thinkpad T400, so I thought this would be a relatively easy first project. I currently have all code copied from the T400. Right now I'm working on the devicetree.cb, but I can't seem to figure out exactly what everything means and what to set it to. Some things, like device, chip, and subsystemid are fairly obvious, but other things, such as register and ioapic_irq are less so. I understand what register does, I just don't know where to get the values I should set them to, such as for gfx.did and pirqa_routing. I have no idea where to find what values go into ioapic_irq Can someone point me in the right direction?

1 year, 6 months

BIOS chip address range?

by Rafael Send

Hi, If I theoretically had a flash chip that was larger than 128Mb, it requires 3-4 byte addressing. Does / could coreboot support such large memory, or would the limitation live somewhere else in the system? Cheers, R

1 year, 6 months

GSoC 2019

by Daniel Lim

Hi, I am Daniel, a computer engineering student at the National University of Singapore. I am interested in extending Ghidra to support the analysis of firmware images. However, I am unsure whether this would be a sufficiently big project for GSoC, and whether I should have an additional one. If that's the case, I would like to also work on porting the GRUB2 payload to the RISC-V architecture. Apart from that, to familiarize myself with the code review process of coreboot, I have made a simple change to cpu/ti/am335x, fixing warnings from checkpatch. May I know who can I add to review it? The patch can be found at https://review.coreboot.org/c/coreboot/+/32119 . Last but not least, may I ask for the scope of GSoC, should I ask questions more on the mailing list or IRC? I am looking forward to learning from you all. Thanks. Regards, Daniel Lim

1 year, 6 months

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coreboot March 2019