Hello All novice here
In my journey to live life with a very high threat model at all times.
I'm in the process of building a desktop/workstation & server that avoids Intel ME and can be corebooted.
Like ive stated before i am new to all of this.I have recently ordered a 2 KGPE-D16 boards from (https://store.vikings.net)
with Coreboot already installed since ive never corebooted anything before and im somewhat afraid to spend alot of $ on hardware.
that i might mess up.The challenges i see myself running into is in regard to what is listed in the installation notes linked here https://www.coreboot.org/Board:asus/kgpe-d16
Specifically the OpenBMC,EHCI debug console,& using "at least one real 8PIN EPS12V cable" per cpu talking points.Especially OpenBMC how do i even remove the proprietary BMC and flash OpenBMC? Also has anyone succesfully installed QubesOs R4.0 on this board with minimal issues?
Sorry if i carried on too long i feel kinda bad with the amateur questions seeing as this mailing list has alot of experts that are very knowledgeable in my eyes.Hopefully you all can help me out or guide me in the right direction to the best option for achieving my goal?
Sent from Seattle, by way of Ann Arbor on Tapatalk: The Remix.
I need to change one UPD data (SpsIccClkSscSetting) of FSP-M structure in Coreboot 4.8.1. I am not sure if it is correct to use HECI message to modify it. Does anyone know how to do it in Coreboot? Actually I have changed that setting in BCT but it was reinited to default when executing in FSP. That’s why I need to change it again in Coreboot. Please help. Thanks.
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On the motherboard developed by our company (intel atom denverton 3538), there is a low performance of the processor and memory. When trying to monitor the exchange of the SVID bus lines with the oscilloscope (SVID_CLK, SVID_DATA and SVID_ALERT), no activity was noticed. Circuit design is correct (passed Intel review).
Could this be the reason for the slow speed of the processor and memory? Do I need to activate this technology in coreboot or FSP? Is there any way to check the operation of the sVID controller from Linux?
For some reason, gfx wont init on Sandybridge P8H61-M PRO with i5-2500T
on coreboot 4.9
Following a recommendation from Icon in coreboot IRC chat, the following
debug was added to check the value of reg16
> printk(BIOS_DEBUG, "%lx\n", (long)reg16);
The serial log shows
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019
romstage starting (log level: 7)...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Graphics not supported by this CPU/chipset.
Back from sandybridge_early_initialization()
lspci with manufacturers BIOS and linux shows the display controller at
00:02.0 as 8086:0102 . There are no other display controllers connected
to the system.
Build log, defconfig, flash log and boot log are attached
Any pointers are greatly appreciated!
I needed to upgrade my laptop about a month earlier. This new one is
one of those who supports Linux via that WSL function. I've got SuSe
SLES12 installed. Has anyone gotten builds to work using something
appropriate from the same setup?
If need be I'll snag a different WSL set.
Gregg C Levine gregg.drwho8(a)gmail.com
"This signature fought the Time Wars, time and again."
I am a sophomore student willing to apply to coreboot as part of Google
Summer of Code 2019.
I have done lot of programming in C and I have a course this semester,
where I will be doing assignments in Assembly language.
I wanted to work on "Fully support building coreboot with the Clang
compiler", however I had a query on the hardware requirements listed on
"hardware requirements: If you have your own hardware that is already
supported by coreboot that can be a good test target, but you will debug
other people’s hardware, too."
Hmm, I have a Ubuntu laptop, and I can buy a Raspberry Pi, if you want ARM
architecture as well, but I didn't get the "you will debug other people’s
hardware, too" part. Could you please explain?