I need to change one UPD data (SpsIccClkSscSetting) of FSP-M structure in Coreboot 4.8.1. I am not sure if it is correct to use HECI message to modify it. Does anyone know how to do it in Coreboot? Actually I have changed that setting in BCT but it was reinited to default when executing in FSP. That’s why I need to change it again in Coreboot. Please help. Thanks.
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On the motherboard developed by our company (intel atom denverton 3538), there is a low performance of the processor and memory. When trying to monitor the exchange of the SVID bus lines with the oscilloscope (SVID_CLK, SVID_DATA and SVID_ALERT), no activity was noticed. Circuit design is correct (passed Intel review).
Could this be the reason for the slow speed of the processor and memory? Do I need to activate this technology in coreboot or FSP? Is there any way to check the operation of the sVID controller from Linux?
For some reason, gfx wont init on Sandybridge P8H61-M PRO with i5-2500T
on coreboot 4.9
Following a recommendation from Icon in coreboot IRC chat, the following
debug was added to check the value of reg16
> printk(BIOS_DEBUG, "%lx\n", (long)reg16);
The serial log shows
coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019
romstage starting (log level: 7)...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Graphics not supported by this CPU/chipset.
Back from sandybridge_early_initialization()
lspci with manufacturers BIOS and linux shows the display controller at
00:02.0 as 8086:0102 . There are no other display controllers connected
to the system.
Build log, defconfig, flash log and boot log are attached
Any pointers are greatly appreciated!
I needed to upgrade my laptop about a month earlier. This new one is
one of those who supports Linux via that WSL function. I've got SuSe
SLES12 installed. Has anyone gotten builds to work using something
appropriate from the same setup?
If need be I'll snag a different WSL set.
Gregg C Levine gregg.drwho8(a)gmail.com
"This signature fought the Time Wars, time and again."
I am a sophomore student willing to apply to coreboot as part of Google
Summer of Code 2019.
I have done lot of programming in C and I have a course this semester,
where I will be doing assignments in Assembly language.
I wanted to work on "Fully support building coreboot with the Clang
compiler", however I had a query on the hardware requirements listed on
"hardware requirements: If you have your own hardware that is already
supported by coreboot that can be a good test target, but you will debug
other people’s hardware, too."
Hmm, I have a Ubuntu laptop, and I can buy a Raspberry Pi, if you want ARM
architecture as well, but I didn't get the "you will debug other people’s
hardware, too" part. Could you please explain?
Interesting discovery about the AtomBIOS files at " g505s-atombios "
repository - https://github.com/g505s-opensource-researcher/g505s-atombios
While there was the same "clean" proprietary UEFI image flashed both
to "G505S with HD 8570M" and to "G505S with R5 M230" before the
AtomBIOS extraction, their AtomBIOSes for _ integrated HD 8650G _
turned out as slightly different! (see sha256)
So I made their full disassembly with this AtomDis tool -
https://cgit.freedesktop.org/~mhopf/AtomDis/ , and compared, diff
results here - https://pastebin.com/eewzswnD . As you could see from
these diff results, for some reason "G505S R5 version" sets a slightly
higher voltages for its' integrated GPU :
compared to "G505S HD version" it is 1.8% - 3.2% higher if these 0x3e
/ 0x40 / 0x6e / 0x70 values are linear and 0x0 = 0 volts.
(usNBP0Voltage / usNBP1Voltage / usVoltageID )
What do you think: would it be okay to use the integrated VGA BIOS
obtained from "G505S R5 version" for "G505S HD version" ?
This voltage difference seems small enough and the integrated GPU is
the same part after all ---> I think that it should be fine.