coreboot March 2019

coreboot@coreboot.org

49 participants
47 discussions

Qubes OS R4.0 & OpenBMC on Corebooted KGPE-D16 questions.
by deonte.street.23＠protonmail.com 24 Mar '19

24 Mar '19

Hello All novice here In my journey to live life with a very high threat model at all times. I'm in the process of building a desktop/workstation & server that avoids Intel ME and can be corebooted. Like ive stated before i am new to all of this.I have recently ordered a 2 KGPE-D16 boards from (https://store.vikings.net) with Coreboot already installed since ive never corebooted anything before and im somewhat afraid to spend alot of $ on hardware. that i might mess up.The challenges i see myself running into is in regard to what is listed in the installation notes linked here https://www.coreboot.org/Board:asus/kgpe-d16 Specifically the OpenBMC,EHCI debug console,& using "at least one real 8PIN EPS12V cable" per cpu talking points.Especially OpenBMC how do i even remove the proprietary BMC and flash OpenBMC? Also has anyone succesfully installed QubesOs R4.0 on this board with minimal issues? Sorry if i carried on too long i feel kinda bad with the amateur questions seeing as this mailing list has alot of experts that are very knowledgeable in my eyes.Hopefully you all can help me out or guide me in the right direction to the best option for achieving my goal? Thanks Sent from Seattle, by way of Ann Arbor on Tapatalk: The Remix.

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Mailinglist confim
by Deonte.Street.23 23 Mar '19

23 Mar '19

sending this email in order to post on the mailing list thanks Sent with [ProtonMail](https://protonmail.com) Secure Email.

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 22 Mar '19

22 Mar '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 3 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 1400227: Control flow issues (NO_EFFECT) /src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: 94 in mp_startup_this_ap() ________________________________________________________________________________________________________ *** CID 1400227: Control flow issues (NO_EFFECT) /src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: 94 in mp_startup_this_ap() 88 89 static efi_return_status_t mp_startup_this_ap(const 90 efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, 91 efi_ap_procedure procedure, efi_uintn_t processor_number, 92 efi_uintn_t timeout_usec, void *argument) 93 { >>> CID 1400227: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "cpu_index() < 0UL". 94 if (cpu_index() < 0) 95 return FSP_DEVICE_ERROR; 96 97 if (processor_number > get_cpu_count()) 98 return FSP_NOT_FOUND; 99 ** CID 1400226: Control flow issues (NO_EFFECT) /src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: 48 in mp_get_processor_info() ________________________________________________________________________________________________________ *** CID 1400226: Control flow issues (NO_EFFECT) /src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: 48 in mp_get_processor_info() 42 43 static efi_return_status_t mp_get_processor_info(const 44 efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, 45 efi_uintn_t processor_number, 46 efi_processor_information *processor_info_buffer) 47 { >>> CID 1400226: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "cpu_index() < 0UL". 48 if (cpu_index() < 0) 49 return FSP_DEVICE_ERROR; 50 51 if (processor_info_buffer == NULL) 52 return FSP_INVALID_PARAMETER; 53 ** CID 1400225: Control flow issues (NO_EFFECT) /src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: 74 in mp_startup_all_aps() ________________________________________________________________________________________________________ *** CID 1400225: Control flow issues (NO_EFFECT) /src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: 74 in mp_startup_all_aps() 68 69 static efi_return_status_t mp_startup_all_aps(const 70 efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, 71 efi_ap_procedure procedure, efi_boolean_t ignored3, 72 efi_uintn_t timeout_usec, void *argument) 73 { >>> CID 1400225: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "cpu_index() < 0UL". 74 if (cpu_index() < 0) 75 return FSP_DEVICE_ERROR; 76 77 if (procedure == NULL) 78 return FSP_INVALID_PARAMETER; 79 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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how to change FSP-M UPD data in coreboot
by Hilbert Tu(杜睿哲_Pegatron) 21 Mar '19

21 Mar '19

Hi, I need to change one UPD data (SpsIccClkSscSetting) of FSP-M structure in Coreboot 4.8.1. I am not sure if it is correct to use HECI message to modify it. Does anyone know how to do it in Coreboot? Actually I have changed that setting in BCT but it was reinited to default when executing in FSP. That’s why I need to change it again in Coreboot. Please help. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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FSP memory init hang on Apollolake MRB
by madeeha＠gmail.com 20 Mar '19

20 Mar '19

I am trying to boot Coreboot on Apollolake (Gordon Peak) MRB board. I have been able to build and flash the binary and it starts to boot but hangs in FSP memory initialization. As per the documents I have, the board has an LPDDR4 memory module. So I dumped the MRC settings from the boot loader that was already running on the board and configured UPD to match it but did not have any success. Now I have run out of options. Can anyone help here? Below is the log from serial console: coreboot-4.9-1001-g285ae69-dirty Wed Mar 13 06:58:21 UTC 2019 bootblock starting (log level: 8)... FMAP: Found "FLASH" version 1.1 at 321000. FMAP: base = 0 size = 800000 #areas = 11 FMAP: area COREBOOT found @ 321800 (3145728 bytes) CBFS @ 321800 size 300000 CBFS: 'IAFW Locator' located CBFS at [321800:621800) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 8914 coreboot-4.9-1001-g285ae69-dirty Wed Mar 13 06:58:21 UTC 2019 romstage starting (log level: 8)... pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 prsts: 00000000 tco_sts: 0000 0000 gen_pmcon1: 08004004 gen_pmcon2: 00003a00 gen_pmcon3: 00000000 prev_sleep_state 5 FMAP: Found "FLASH" version 1.1 at 321000. FMAP: base = 0 size = 800000 #areas = 11 FMAP: area COREBOOT found @ 321800 (3145728 bytes) CBFS @ 321800 size 300000 CBFS: 'IAFW Locator' located CBFS at [321800:621800) CBFS: Locating 'fspm.bin' CBFS: Found @ offset 27500 size 59000 Spec version: v2.0 Revision: 1.4.3, Build Number 1 Type: release/test image ID: $APLFSP$, base 0xfef40000 + 0x59000 Config region 0x124 + 0x200 Memory init offset 0x3f0 POST: 0x34 FMAP: area RW_MRC_CACHE found @ 631800 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' bootmode is set to :0 FMAP: area RW_VAR_MRC_CACHE found @ 641800 (4096 bytes) MRC: no data in 'RW_VAR_MRC_CACHE' POST: 0x36 Architectural UPD values for MemoryInit at: 0xfef044d0 0x01: Revision 0x00000000: NvsBufferPtr 0xfef16000 --> 0xfef96000: StackBase 0x0002a000: StackSize 0x00000000 --> 0x00002000: BootLoaderTolumSize 0x00000000: BootMode UPD values for MemoryInit: fef044b0: 41 50 4c 55 50 44 5f 4d 01 00 00 00 00 00 00 00 APLUPD_M........ fef044c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef044d0: 01 00 00 00 00 00 00 00 00 60 f9 fe 00 a0 02 00 .........`...... fef044e0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 . .............. fef044f0: 00 00 00 00 02 02 02 00 01 02 01 03 00 01 0b 01 ................ fef04500: 00 00 01 02 36 00 09 00 00 00 01 00 00 18 00 00 ....6........... fef04510: 00 00 00 00 00 03 01 02 03 00 00 00 00 03 01 02 ................ fef04520: 03 00 00 00 00 03 01 02 03 00 00 00 00 03 01 02 ................ fef04530: 03 00 00 00 00 00 00 00 09 0e 0c 0d 0a 0b 08 0f ................ fef04540: 05 06 01 00 02 07 04 03 1a 1f 1c 1b 1d 19 18 1e ................ fef04550: 14 16 17 11 12 13 10 15 06 07 05 04 03 01 00 02 ................ fef04560: 0c 0a 0b 0d 0e 08 09 0f 14 10 16 15 12 11 13 17 ................ fef04570: 1e 1c 1d 19 18 1a 1b 1f 0f 09 08 0b 0c 0d 0e 0a ................ fef04580: 05 02 00 03 06 07 01 04 19 1c 1e 1f 1a 1b 18 1d ................ fef04590: 14 17 16 15 12 13 10 11 03 04 06 05 00 01 02 07 ................ fef045a0: 0b 0a 08 09 0e 0c 0f 0d 11 17 13 10 15 16 14 12 ................ fef045b0: 1c 1d 1a 19 1e 1b 18 1f 00 00 00 00 00 00 00 00 ................ fef045c0: 00 00 00 00 00 00 00 00 00 01 00 00 00 00 d0 7a ...............z fef045d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fef045e0: 00 00 00 00 00 01 03 01 04 00 01 01 00 00 00 00 ................ fef045f0: 00 00 00 00 01 00 02 01 01 00 00 00 00 00 00 00 ................ fef04600: 00 28 f4 ff 00 00 00 00 00 00 00 00 00 00 00 00 .(.............. fef04610: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... fef046a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa 55 ...............U Calling FspMemoryInit: 0xfef403f0 0xfef044b0: raminit_upd 0xfef05668: &hob_list_ptr POST: 0x92

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Intel sVID controller and SVID bus.
by dponamorev＠gmail.com 20 Mar '19

20 Mar '19

On the motherboard developed by our company (intel atom denverton 3538), there is a low performance of the processor and memory. When trying to monitor the exchange of the SVID bus lines with the oscilloscope (SVID_CLK, SVID_DATA and SVID_ALERT), no activity was noticed. Circuit design is correct (passed Intel review). Could this be the reason for the slow speed of the processor and memory? Do I need to activate this technology in coreboot or FSP? Is there any way to check the operation of the sVID controller from Linux?

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Atom Denverton processor and memory are very slow.
by Дмитрий Понаморев 20 Mar '19

20 Mar '19

The processor and memory are very slow. Compiling the ixgbe network card driver takes 10 minutes. The maximum read speed of DDR4 2133 SODIMM is 742 MB / sec. Custom motherboard with Atom Denverton C3538 processor, quad cores 2.1 GHz. SODIMM module: Crucial DDR4 8Gb 2400MHz CT8G4SFS824A. BIOS: coreboot 4.9 + intel FSP + seabios. WD Blue WDS250G2B0B 250GB, M.2 2280, SATA III Hard Drive. Debian 7 (Linux version 3.2.0-4-amd64 ( debian-kernel(a)lists.debian.org) (gcc version 4.6.3 (Debian 4.6.3-14) ) #1 SMP Debian 3.2.96-2). Why the slow operation of the processor and memory is possible? What settings can be changed in Intel FSP and coreboot to speed up the processor and memory? Full boot log in attached file: putty_com5_coreboot_seabios_debian.zip Bandwidth64 memory test: This is bandwidth version 1.5.1. Copyright (C) 2005-2017 by Zack T Smith. This software is covered by the GNU Public License. It is provided AS-IS, use at your own risk. See the file COPYING for more information. CPU family: GenuineIntel CPU features: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES XD Intel64 Cache 0: L1 data cache, line size 64, 6-ways, 64 sets, size 24k Cache 1: L1 instruction cache, line size 64, 8-ways, 64 sets, size 32k Cache 2: L2 unified cache, line size 64, 16-ways, 2048 sets, size 2048k Notation: B = byte, kB = 1024 B, MB = 1048576 B. CPU speed is 2099.99 MHz. Sequential read (64-bit), size = 128 B, loops = 30408704, 741.4 MB/s Sequential read (64-bit), size = 256 B, loops = 15204352, 741.2 MB/s Sequential read (64-bit), size = 384 B, loops = 10136196, 741.4 MB/s Sequential read (64-bit), size = 512 B, loops = 7602176, 740.9 MB/s Sequential read (64-bit), size = 640 B, loops = 6186563, 742.6 MB/s Sequential read (64-bit), size = 768 B, loops = 5155479, 742.7 MB/s Sequential read (64-bit), size = 896 B, loops = 4418982, 742.7 MB/s Sequential read (64-bit), size = 1024 B, loops = 3866624, 742.7 MB/s Sequential read (64-bit), size = 1280 B, loops = 3040824, 742.3 MB/s Sequential read (64-bit), size = 2 kB, loops = 1933312, 742.7 MB/s Sequential read (64-bit), size = 3 kB, loops = 1288855, 742.5 MB/s Sequential read (64-bit), size = 4 kB, loops = 966656, 742.6 MB/s Sequential read (64-bit), size = 6 kB, loops = 644398, 742.6 MB/s Sequential read (64-bit), size = 8 kB, loops = 475136, 742.4 MB/s Sequential read (64-bit), size = 12 kB, loops = 316738, 735.7 MB/s Sequential read (64-bit), size = 16 kB, loops = 237568, 736.2 MB/s Sequential read (64-bit), size = 20 kB, loops = 190008, 734.7 MB/s Sequential read (64-bit), size = 24 kB, loops = 152880, 708.7 MB/s Sequential read (64-bit), size = 28 kB, loops = 70200, 374.0 MB/s Sequential read (64-bit), size = 32 kB, loops = 61440, 371.4 MB/s Sequential read (64-bit), size = 34 kB, loops = 57810, 371.2 MB/s Sequential read (64-bit), size = 36 kB, loops = 52780, 371.1 MB/s Sequential read (64-bit), size = 40 kB, loops = 49140, 371.2 MB/s Sequential read (64-bit), size = 48 kB, loops = 40950, 371.3 MB/s Sequential read (64-bit), size = 64 kB, loops = 30720, 371.3 MB/s Sequential read (64-bit), size = 128 kB, loops = 14848, 368.6 MB/s Sequential read (64-bit), size = 192 kB, loops = 9889, 368.9 MB/s Sequential read (64-bit), size = 256 kB, loops = 7424, 368.9 MB/s Sequential read (64-bit), size = 320 kB, loops = 5916, 369.6 MB/s Sequential read (64-bit), size = 384 kB, loops = 4930, 369.6 MB/s Sequential read (64-bit), size = 512 kB, loops = 3712, 369.6 MB/s Sequential read (64-bit), size = 768 kB, loops = 2465, 369.6 MB/s Sequential read (64-bit), size = 1 MB, loops = 1856, 369.6 MB/s Sequential read (64-bit), size = 1.25 MB, loops = 1479, 369.5 MB/s Sequential read (64-bit), size = 1.5 MB, loops = 1260, 369.4 MB/s Sequential read (64-bit), size = 1.75 MB, loops = 1080, 366.9 MB/s Sequential read (64-bit), size = 2 MB, loops = 896, 356.9 MB/s Sequential read (64-bit), size = 2.25 MB, loops = 784, 350.9 MB/s Sequential read (64-bit), size = 2.5 MB, loops = 725, 351.2 MB/s Sequential read (64-bit), size = 2.75 MB, loops = 644, 351.0 MB/s Sequential read (64-bit), size = 3 MB, loops = 588, 351.3 MB/s Sequential read (64-bit), size = 3.25 MB, loops = 551, 351.1 MB/s Sequential read (64-bit), size = 3.5 MB, loops = 504, 351.2 MB/s Sequential read (64-bit), size = 4 MB, loops = 448, 351.3 MB/s Sequential read (64-bit), size = 5 MB, loops = 360, 351.4 MB/s Sequential read (64-bit), size = 6 MB, loops = 300, 351.4 MB/s Sequential read (64-bit), size = 7 MB, loops = 252, 351.5 MB/s Sequential read (64-bit), size = 8 MB, loops = 224, 351.4 MB/s Random read (64-bit), size = 256 B, loops = 13893632, 678.4 MB/s Random read (64-bit), size = 512 B, loops = 6946816, 677.2 MB/s Random read (64-bit), size = 768 B, loops = 4631193, 677.1 MB/s Random read (64-bit), size = 1024 B, loops = 3473408, 677.2 MB/s Random read (64-bit), size = 1280 B, loops = 2778684, 677.7 MB/s Random read (64-bit), size = 2 kB, loops = 1769472, 678.6 MB/s Random read (64-bit), size = 3 kB, loops = 1179630, 678.6 MB/s Random read (64-bit), size = 4 kB, loops = 868352, 677.1 MB/s Random read (64-bit), size = 6 kB, loops = 578866, 677.5 MB/s Random read (64-bit), size = 8 kB, loops = 442368, 679.0 MB/s Random read (64-bit), size = 12 kB, loops = 289433, 672.9 MB/s Random read (64-bit), size = 16 kB, loops = 217088, 673.4 MB/s Random read (64-bit), size = 20 kB, loops = 173628, 673.1 MB/s Random read (64-bit), size = 24 kB, loops = 128310, 596.1 MB/s Random read (64-bit), size = 28 kB, loops = 79560, 434.8 MB/s Random read (64-bit), size = 32 kB, loops = 69632, 430.8 MB/s Random read (64-bit), size = 34 kB, loops = 65518, 431.5 MB/s Random read (64-bit), size = 36 kB, loops = 61880, 432.0 MB/s Random read (64-bit), size = 40 kB, loops = 55692, 431.7 MB/s Random read (64-bit), size = 48 kB, loops = 46410, 430.6 MB/s Random read (64-bit), size = 64 kB, loops = 34816, 430.5 MB/s Random read (64-bit), size = 128 kB, loops = 16896, 420.3 MB/s Random read (64-bit), size = 192 kB, loops = 11253, 412.6 MB/s Random read (64-bit), size = 256 kB, loops = 8192, 405.5 MB/s Random read (64-bit), size = 320 kB, loops = 6528, 402.1 MB/s Random read (64-bit), size = 384 kB, loops = 5440, 398.5 MB/s Random read (64-bit), size = 512 kB, loops = 3968, 395.5 MB/s Random read (64-bit), size = 768 kB, loops = 2635, 392.6 MB/s Random read (64-bit), size = 1 MB, loops = 1984, 390.9 MB/s Random read (64-bit), size = 1.25 MB, loops = 1581, 389.6 MB/s Random read (64-bit), size = 1.5 MB, loops = 1302, 388.2 MB/s Random read (64-bit), size = 1.75 MB, loops = 1008, 347.2 MB/s Random read (64-bit), size = 2 MB, loops = 768, 297.0 MB/s Random read (64-bit), size = 2.25 MB, loops = 560, 248.7 MB/s Random read (64-bit), size = 2.5 MB, loops = 450, 221.8 MB/s Random read (64-bit), size = 2.75 MB, loops = 391, 207.7 MB/s Random read (64-bit), size = 3 MB, loops = 336, 198.0 MB/s Random read (64-bit), size = 3.25 MB, loops = 304, 192.9 MB/s Random read (64-bit), size = 3.5 MB, loops = 270, 188.8 MB/s Random read (64-bit), size = 4 MB, loops = 240, 183.5 MB/s Random read (64-bit), size = 5 MB, loops = 180, 176.1 MB/s Random read (64-bit), size = 6 MB, loops = 150, 171.7 MB/s Random read (64-bit), size = 7 MB, loops = 126, 168.5 MB/s Random read (64-bit), size = 8 MB, loops = 104, 166.1 MB/s

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p8h61-m pro gfx no init sandybridge
by Simon Newton 18 Mar '19

18 Mar '19

Hi folks, For some reason, gfx wont init on Sandybridge P8H61-M PRO with i5-2500T on coreboot 4.9 Following a recommendation from Icon in coreboot IRC chat, the following debug was added to check the value of reg16 diff ../core2/src/northbridge/intel/sandybridge/early_init.c ./src/northbridge/intel/sandybridge/early_init.c 86c86 < --- > 102a103 > printk(BIOS_DEBUG, "%lx\n", (long)reg16); The serial log shows coreboot-4.9-1050-gebd8a4f90c-dirty Sat Mar 16 16:22:16 UTC 2019 romstage starting (log level: 7)... Setting up static southbridge registers... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. ffff Graphics not supported by this CPU/chipset. Back from sandybridge_early_initialization() lspci with manufacturers BIOS and linux shows the display controller at 00:02.0 as 8086:0102 . There are no other display controllers connected to the system. Build log, defconfig, flash log and boot log are attached Any pointers are greatly appreciated!

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Using WSL to build coreboot
by Gregg Levine 17 Mar '19

17 Mar '19

Hello! I needed to upgrade my laptop about a month earlier. This new one is one of those who supports Linux via that WSL function. I've got SuSe SLES12 installed. Has anyone gotten builds to work using something appropriate from the same setup? If need be I'll snag a different WSL set. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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Applying for Google Summer of Code 2019
by Swapnil Rustagi 17 Mar '19

17 Mar '19

Hi I am a sophomore student willing to apply to coreboot as part of Google Summer of Code 2019. I have done lot of programming in C and I have a course this semester, where I will be doing assignments in Assembly language. I wanted to work on "Fully support building coreboot with the Clang compiler", however I had a query on the hardware requirements listed on https://doc.coreboot.org/contributing/project_ideas.html: "hardware requirements: If you have your own hardware that is already supported by coreboot that can be a good test target, but you will debug other people’s hardware, too." Hmm, I have a Ubuntu laptop, and I can buy a Raspberry Pi, if you want ARM architecture as well, but I didn't get the "you will debug other people’s hardware, too" part. Could you please explain?

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coreboot March 2019