In order to (better) support other than X86 to have PCI support, headers
with primitive low-level accessors have been re-organised as follows:
For any MMIO access, <device/mmio.h>
For any PCI configurations, <device/pci_ops.h>
For X86 (or other) IO space, <arch/io.h>
For PNP configuration (pre-ram), <device/pnp_ops.h>
My current advice is you don't need to include <device/pci_type.h> or
Dear Coreboot developers,
I installed Coreboot with ThinkPad X60s and Debian 9 and they run
successfully, but I observe a weird behavior.
Even though I had enabled blob for microcode update, the system seems
to run without it. I saw the following message in dmesg:
(I think this is not fatal since this is related to temperature
> coretemp: Errata AE18 not fixed, update BIOS or microcode of the CPU!
For comparison, I had installed `intel-microcode` package to the
system and then the message disappeared.
Is this intended behavior, misconfiguration, or a real bug?
For reference, I uploaded the content of /proc/cpuinfo before and
after the installation of `intel-microcode` package:
Also, I uploaded a report to board-status:
(I had also tried to install FreeBSD 12.0 and OpenBSD 6.4 but both of
their installers failed to boot just after the kernel is loaded and
located. I am not sure if this is related to this or not.)
I am Shubhendra Pal Singhal, currently third year in Computer Science at
NIT Trichy, India. I wish to apply for Google Summer of Code. I looked into
the profile of coreboot 4.9 and found out the project idea "*Port payloads
to ARM, AArch64, MIPS or RISC-V*" to be very interesting.
I have worked in the similar field on *RISCV architecture at IIT Madras
where I helped in porting real time OS eChronos*, on RISCV architecture. I
will be undergoing a *project in Embedded systems offered by USC Los
Angeles in solving the SAT Solvers using OS and Digital Logic*.
Furthermore, I am currently working on a *long term project with under
Prof. N.Ramasubramanium on the AI chip* where we are trying to solve the
processing speeds by efficiently reducing the number of writes in the cache
for faster access. I am also *undergoing Microcontrollers and
Microprocessors* as my core subject in my current semester and have
OS, Real time Systems* in my B.Tech IV semester.
I have included my further details in my Linkedin : *
I want to contribute to the open source community in the field of Operating
Systems and this can prove to be an excellent platform for gaining
experience in field of systems. This opportunity can pave my career,
towards applied research in the field of Systems.
*While browsing through the link, I saw the mailing list assigned for the
project. It would be very useful if you could guide me as to what is
expected in the project proposal and how can I serve the open source
community in the best possible way. *Any guidance would be very useful and
I hope to receive a reply soon. Thanking you for your time and
Shubhendra Pal Singhal
National Institute Of Technology, Trichy, India
Phone number : +91 9787888015
Email-id : shubhendrapalsinghal(a)gmail.com
Linkedin : <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/>
Why BMP? It's a lossless image format which could be LZMA compressed
quite well depending on the image's variety of colours. And finally I
found out how to get a working splash screen - instructions tested on
AMD Lenovo G505S laptop with 1366x768 screen resolution :
1) Install the ImageMagick package, it has a "convert" tool.
2) Find a cool image, preferably in a lossless format like PNG
(certainly not a lossy JPEG!), resize it to your screen resolution -
e.g. to 1366x768 in this particular case - and save it, preferably as
3) Now you could convert this image into BMP format recognizable by SeaBIOS:
convert ./wallpaper.png -alpha set -verbose -depth 32 ./bootsplash.bmp
4) Then add it to your coreboot.rom image, with LZMA compression of
course - because without a compression those BMPs are too large:
./coreboot/build/cbfstool ./coreboot/build/coreboot.rom add -f
~/Downloads/bootsplash.bmp -n bootsplash.bmp.lzma -t raw -c lzma
5) And finally flash the updated image, e.g. at G505S it could be
sudo ./flashrom/flashrom -p
Hope it's helpful!
I'm working on Intel Braswell implementation and uploaded several patches.
It seems that the maintainer of the Intel Braswell is not active for review/merge/reply of the uploads.
Is the maintainer in MAINTAINERS document correct and still active?
Met vriendelijke groet / Best regards,