coreboot March 2019

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 05 Mar '19

05 Mar '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 9 new defect(s) introduced to coreboot found with Coverity Scan. 2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 9 of 9 defect(s) ** CID 1399155: Null pointer dereferences (REVERSE_INULL) /src/soc/intel/skylake/acpi.c: 521 in generate_cpu_entries() ________________________________________________________________________________________________________ *** CID 1399155: Null pointer dereferences (REVERSE_INULL) /src/soc/intel/skylake/acpi.c: 521 in generate_cpu_entries() 515 else 516 max_c_state = ARRAY_SIZE(cstate_set_non_s0ix); 517 518 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", 519 numcpus, cores_per_package); 520 >>> CID 1399155: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "config" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 521 if (config && config->eist_enable && config->speed_shift_enable) { 522 struct cppc_config cppc_config; 523 cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); 524 acpigen_write_CPPC_package(&cppc_config); 525 } 526 ** CID 1399154: Uninitialized variables (UNINIT) /src/mainboard/sifive/hifive-unleashed/fixup_fdt.c: 102 in fixup_fdt() ________________________________________________________________________________________________________ *** CID 1399154: Uninitialized variables (UNINIT) /src/mainboard/sifive/hifive-unleashed/fixup_fdt.c: 102 in fixup_fdt() 96 /* convert the tree to a flat dt */ 97 void *dt = malloc(dt_flat_size(tree)); 98 dt_flatten(tree, dt); 99 100 /* update HLS */ 101 for (int i = 0; i < CONFIG_MAX_CPUS; i++) >>> CID 1399154: Uninitialized variables (UNINIT) >>> Using uninitialized value "sp". 102 OTHER_HLS(i)->fdt = dt; 103 } 104 ** CID 1399153: Uninitialized variables (UNINIT) ________________________________________________________________________________________________________ *** CID 1399153: Uninitialized variables (UNINIT) /src/arch/x86/acpi.c: 166 in acpi_create_madt_lapics() 160 if (!cpu->enabled) 161 continue; 162 if (num_cpus >= ARRAY_SIZE(apic_ids)) 163 break; 164 apic_ids[num_cpus++] = cpu->path.apic.apic_id; 165 } >>> CID 1399153: Uninitialized variables (UNINIT) >>> Using uninitialized element of array "apic_ids" when calling "bubblesort". 166 bubblesort(apic_ids, num_cpus, NUM_ASCENDING); 167 for (index = 0; index < num_cpus; index++) { 168 current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 169 index, apic_ids[index]); 170 } 171 ** CID 1399152: (UNINIT) /src/arch/riscv/stages.c: 41 in stage_entry() /src/arch/riscv/stages.c: 42 in stage_entry() ________________________________________________________________________________________________________ *** CID 1399152: (UNINIT) /src/arch/riscv/stages.c: 41 in stage_entry() 35 { 36 /* 37 * Save the FDT pointer before entering ramstage, because mscratch 38 * might be overwritten in the trap handler, and there is code in 39 * ramstage that generates misaligned access faults. 40 */ >>> CID 1399152: (UNINIT) >>> Using uninitialized value "sp". 41 HLS()->hart_id = hart_id; 42 HLS()->fdt = fdt; 43 smp_pause(CONFIG_RISCV_WORKING_HARTID); 44 45 main(); /src/arch/riscv/stages.c: 42 in stage_entry() 36 /* 37 * Save the FDT pointer before entering ramstage, because mscratch 38 * might be overwritten in the trap handler, and there is code in 39 * ramstage that generates misaligned access faults. 40 */ 41 HLS()->hart_id = hart_id; >>> CID 1399152: (UNINIT) >>> Using uninitialized value "sp". 42 HLS()->fdt = fdt; 43 smp_pause(CONFIG_RISCV_WORKING_HARTID); 44 45 main(); ** CID 1399151: Integer handling issues (DIVIDE_BY_ZERO) ________________________________________________________________________________________________________ *** CID 1399151: Integer handling issues (DIVIDE_BY_ZERO) /src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c: 145 in init_octeon_dram_interface() 139 140 restart_lmc_init: 141 142 /* Poke the watchdog timer so it doesn't expire during DRAM init */ 143 bdk_watchdog_poke(); 144 >>> CID 1399151: Integer handling issues (DIVIDE_BY_ZERO) >>> In function call "init_octeon3_ddr3_interface", division by expression "ddr_hertz" which may be zero has undefined behavior. 145 mem_size_mbytes = init_octeon3_ddr3_interface(node, 146 ddr_configuration, 147 ddr_hertz, 148 cpu_hertz, 149 ddr_ref_hertz, 150 board_type, ** CID 1399150: Insecure data handling (TAINTED_SCALAR) /src/mainboard/emulation/qemu-i440fx/fw_cfg.c: 70 in fw_cfg_find_file() ________________________________________________________________________________________________________ *** CID 1399150: Insecure data handling (TAINTED_SCALAR) /src/mainboard/emulation/qemu-i440fx/fw_cfg.c: 70 in fw_cfg_find_file() 64 uint32_t count = 0; 65 66 fw_cfg_select(FW_CFG_FILE_DIR); 67 fw_cfg_read(&count, sizeof(count)); 68 count = be32_to_cpu(count); 69 >>> CID 1399150: Insecure data handling (TAINTED_SCALAR) >>> Using tainted variable "count" as a loop boundary. 70 for (int i = 0; i < count; i++) { 71 fw_cfg_read(file, sizeof(*file)); 72 if (strcmp(file->name, name) == 0) { 73 file->size = be32_to_cpu(file->size); 74 file->select = be16_to_cpu(file->select); 75 return 0; ** CID 1399149: Null pointer dereferences (REVERSE_INULL) /src/southbridge/intel/i82801gx/pcie.c: 198 in root_port_commit_config() ________________________________________________________________________________________________________ *** CID 1399149: Null pointer dereferences (REVERSE_INULL) /src/southbridge/intel/i82801gx/pcie.c: 198 in root_port_commit_config() 192 193 for (i = 0; i < rpc.num_ports; i++) { 194 struct device *pcie_dev; 195 196 pcie_dev = rpc.ports[i]; 197 >>> CID 1399149: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "dev" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 198 if (dev == NULL) { 199 printk(BIOS_ERR, "Root Port %d device is NULL?\n", 200 i + 1); 201 continue; 202 } 203 ** CID 1399148: (UNINIT) /src/arch/riscv/boot.c: 42 in do_arch_prog_run() /src/arch/riscv/boot.c: 50 in do_arch_prog_run() ________________________________________________________________________________________________________ *** CID 1399148: (UNINIT) /src/arch/riscv/boot.c: 42 in do_arch_prog_run() 36 37 /* 38 * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS 39 * instead. 40 */ 41 if (fdt == NULL) >>> CID 1399148: (UNINIT) >>> Using uninitialized value "sp". 42 fdt = HLS()->fdt; 43 44 if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { 45 run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); 46 return; 47 } /src/arch/riscv/boot.c: 50 in do_arch_prog_run() 44 if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { 45 run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); 46 return; 47 } 48 49 doit = prog_entry(prog); >>> CID 1399148: (UNINIT) >>> Using uninitialized value "sp". 50 hart_id = HLS()->hart_id; 51 52 doit(hart_id, fdt); 53 } 54 55 void arch_prog_run(struct prog *prog) 56 { 57 smp_resume((void (*)(void *))do_arch_prog_run, prog); ** CID 1399147: Null pointer dereferences (NULL_RETURNS) ________________________________________________________________________________________________________ *** CID 1399147: Null pointer dereferences (NULL_RETURNS) /src/mainboard/sifive/hifive-unleashed/fixup_fdt.c: 90 in fixup_fdt() 84 struct device_tree *tree; 85 86 /* load flat dt from cbfs */ 87 fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL); 88 89 /* Expand DT into a tree */ >>> CID 1399147: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be null "fdt_rom" when calling "fdt_unflatten". 90 tree = fdt_unflatten(fdt_rom); 91 92 /* fixup tree */ 93 fixup_mac(tree->root); 94 fixup_memory(tree->root); 95 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

1 0

Primitive low-level header file changes
by Kyösti Mälkki 05 Mar '19

05 Mar '19

Hi folks! In order to (better) support other than X86 to have PCI support, headers with primitive low-level accessors have been re-organised as follows: For any MMIO access, <device/mmio.h> read8/16/32/64() write8/16/32/64() For any PCI configurations, <device/pci_ops.h> pci_read_config8/16/32() pci_write_config8/16/32() pci_or_config8/16/32() pci_update_config8/16/32() For X86 (or other) IO space, <arch/io.h> inb(),inw(),inl(),insb(),insw(),insl() outb(),outw(),outl(),outsb(),outsw(),outsl() For PNP configuration (pre-ram), <device/pnp_ops.h> pnp_read_config(), pnp_write_config() pnp_set_XX(), pnp_read_XX() My current advice is you don't need to include <device/pci_type.h> or <device/pnp_type.h> explicitly. Regards, Kyösti

1 0

t420s USB 3.0 port
by Jason Andryuk 05 Mar '19

05 Mar '19

Hi, I have a Lenovo Thinkpad t420s on which I've installed coreboot. However, the USB 3.0 port is not active and the controller is not listed under lspci. Under the original Lenovo bios, the xhci device was at pci address 0d:00.0 behind bridge 00:1c.4. It looks like the t420s devicetree.cb is set up for the xhci controller to be behind 00:1c.6. I changed that to 00:1c.4 and that got the xhci pci device to show up as 03:00.0. Strangely, booting into linux, it shows 001c.3 as the bridge to 03:00.0. Additionally, plugged in USB devices were not detected. Here's where it gets weird. I had a mouse plugged in, and I was looking in sysfs. cat /sys/devices/pci0000\:00/0000\:00\:1c.3/0000\:03\:00.0/enable 0 So the xhci pci device is disabled. I ran `lspci -vvnn` a few times in quick sucession - I was looking to see if it showed disabled - and the mouse lit up! Plugging in a USB Flash drive, it was again not detected. The lspci trigger worked. Later, promptly switching USB devices resulted in the new USB device still being detected. Is "PCH: PCIe map 1c.4 -> 1c.3" the remapping from the device tree 1c.4 to the 1c.3 that I see? Below I've included the cbmem -c output and a snippet from an old lenovo BIOS dmesg w/ the pci address. Does anyone have an idea of what is going on, or what I should investigate next? A total guess, but could poking the PCI device with lspci turn it on so that it may detect an attached device and then stay active? Maybe something with power management? Again, I'm just guessing. Any suggestions are appreciated. Thanks, Jason Old linux dmesg from Lenovo BIOS: Dec 6 01:55:52 ubuntu kernel: [ 10.077337] pci 0000:0d:00.0: >[1033:0194] type 00 class 0x0c0330 Dec 6 01:55:52 ubuntu kernel: [ 10.077382] pci 0000:0d:00.0: >reg 10: [mem 0xf0c00000-0xf0c01fff 64bit] Dec 6 01:55:52 ubuntu kernel: [ 10.077610] pci 0000:0d:00.0: >PME# supported from D0 D3hot D3cold Dec 6 01:55:52 ubuntu kernel: [ 10.077701] pci 0000:00:1c.4: >PCI bridge to [bus 0d-0d] Dec 6 01:55:52 ubuntu kernel: [ 10.077714] pci 0000:00:1c.4: > bridge window [mem 0xf0c00000-0xf0cfffff] cbmem -c dump: *** Pre-CBMEM romstage console overflowed, log truncated! *** 666 MHz Selected CAS latency : 9T PLL busy... done in 50 us MCU frequency is set at : 666 MHz Done dimm mapping Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 4 PCI(0, 0, 0)[bc] = 82a00000 PCI(0, 0, 0)[a8] = 7d600000 PCI(0, 0, 0)[ac] = 4 PCI(0, 0, 0)[b8] = 80000000 PCI(0, 0, 0)[b0] = 80a00000 PCI(0, 0, 0)[b4] = 80800000 Done memory map Done io registers t123: 1912, 9120, 500 ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Debug or Disabled by AltDisableBit ME: Error Code : No Error ME: Progress Phase : BUP Phase ME: Power Management Event : Clean Moff->Mx wake ME: Progress Phase State : Check to see if straps say ME DISABLED ME: Wrong mode : 2 ME: FWS2: 0x100a0000 ME: Bist in progress: 0x0 ME: ICC Status : 0x0 ME: Invoke MEBx : 0x0 ME: CPU replaced : 0x0 ME: MBP ready : 0x0 ME: MFS failure : 0x0 ME: Warm reset req : 0x0 ME: CPU repl valid : 0x0 ME: (Reserved) : 0x0 ME: FW update req : 0x0 ME: (Reserved) : 0x0 ME: Current state : 0xa ME: Current PM event: 0x0 ME: Progress code : 0x1 Waited long enough, or CPU was not replaced, continue... PASSED! Tell ME that DRAM is ready ME: ME is reporting as disabled, so not waiting for a response. ME: FWS2: 0x100a0000 ME: Bist in progress: 0x0 ME: ICC Status : 0x0 ME: Invoke MEBx : 0x0 ME: CPU replaced : 0x0 ME: MBP ready : 0x0 ME: MFS failure : 0x0 ME: Warm reset req : 0x0 ME: CPU repl valid : 0x0 ME: (Reserved) : 0x0 ME: FW update req : 0x0 ME: (Reserved) : 0x0 ME: Current state : 0xa ME: Current PM event: 0x0 ME: Progress code : 0x1 ME: Requested BIOS Action: No DID Ack received ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Debug or Disabled by AltDisableBit ME: Error Code : No Error ME: Progress Phase : BUP Phase ME: Power Management Event : Clean Moff->Mx wake ME: Progress Phase State : Check to see if straps say ME DISABLED memcfg DDR3 ref clock 133 MHz memcfg DDR3 clock 1330 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00620020): ECC inactive enhanced interleave mode on rank interleave on DIMMA 8192 MB width x8 dual rank, selected DIMMB 0 MB width x8 single rank memcfg channel[1] config (00620020): ECC inactive enhanced interleave mode on rank interleave on DIMMA 8192 MB width x8 dual rank, selected DIMMB 0 MB width x8 single rank CBMEM: IMD: root @ 7ffff000 254 entries. IMD: root @ 7fffec00 62 entries. External stage cache: IMD: root @ 803ff000 254 entries. IMD: root @ 803fec00 62 entries. CBMEM entry for DIMM info: 0x7fffea40 MTRR Range: Start=ff800000 End=0 (Size 800000) MTRR Range: Start=0 End=1000000 (Size 1000000) MTRR Range: Start=7f800000 End=80000000 (Size 800000) MTRR Range: Start=80000000 End=80800000 (Size 800000) CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 3a580 size 3ce4 Decompressing stage fallback/postcar @ 0x7ffcffc0 (32208 bytes) Loading module at 7ffd0000 with entry 7ffd0000. filesize: 0x3ad0 memsize: 0x7d90 Processing 110 relocs. Offset value of 0x7dfd0000 coreboot-4.9-dirty Wed Dec 19 18:05:51 UTC 2018 postcar starting... CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 19e40 size 1895c Decompressing stage fallback/ramstage @ 0x7ff86fc0 (293432 bytes) Loading module at 7ff87000 with entry 7ff87000. filesize: 0x33a30 memsize: 0x479f8 Processing 3449 relocs. Offset value of 0x7f187000 coreboot-4.9-dirty Wed Dec 19 18:05:51 UTC 2018 ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 Enumerating buses... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0104] enabled PCI: Static device PCI: 00:01.0 not found, disabling it. PCI: 00:02.0 [8086/0126] enabled PCI: 00:04.0 [8086/0103] enabled PCI: 00:16.0: Disabling device PCI: 00:16.0 [8086/1c3a] disabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:19.0 [8086/1502] enabled PCI: 00:1a.0 [8086/1c2d] enabled PCI: 00:1b.0 [8086/1c20] enabled PCH: PCIe Root Port coalescing is enabled PCI: 00:1c.0: Disabling device PCI: 00:1c.0: check set enabled PCH: Remap PCIe function 1 to 0 PCI: 00:1c.1 [8086/1c12] enabled PCI: 00:1c.2: Disabling device PCH: Remap PCIe function 3 to 0 PCI: 00:1c.3 [8086/1c16] enabled PCH: Remap PCIe function 4 to 0 PCI: 00:1c.4 [8086/1c18] enabled PCI: 00:1c.5: Disabling device PCI: 00:1c.6: Disabling device PCI: 00:1c.7: Disabling device PCH: PCIe map 1c.0 -> 1c.4 PCH: PCIe map 1c.1 -> 1c.0 PCH: PCIe map 1c.3 -> 1c.1 PCH: PCIe map 1c.4 -> 1c.3 PCI: 00:1d.0 [8086/1c26] enabled PCI: 00:1e.0: Disabling device PCI: 00:1e.0 [8086/2448] disabled PCI: 00:1f.0 [8086/1c4f] enabled PCI: 00:1f.2 [8086/1c01] enabled PCI: 00:1f.3 [8086/1c22] enabled PCI: 00:1f.5: Disabling device PCI: 00:1f.6 [8086/1c24] enabled PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [8086/4238] enabled Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Failed to enable LTR for dev = PCI: 01:00.0 scan_bus: scanning of bus PCI: 00:1c.0 took 301 usecs PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [1180/e823] enabled Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Failed to enable LTR for dev = PCI: 02:00.0 scan_bus: scanning of bus PCI: 00:1c.1 took 255 usecs PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [1033/0194] enabled Enabling Common Clock Configuration ASPM: Enabled L0s and L1 scan_bus: scanning of bus PCI: 00:1c.3 took 238 usecs PMH7: ID 04 Revision 01 PNP: 00ff.1 enabled PNP: 0c31.0 enabled EC Firmware ID 8CHT27WW-3.20, Version 0.01C H8: BDC installed H8: WWAN detection not implemented. Assuming WWAN installed PNP: 00ff.2 enabled Hybrid graphics: Not installed PNP: 00ff.f disabled scan_bus: scanning of bus PCI: 00:1f.0 took 5243 usecs bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled scan_bus: scanning of bus PCI: 00:1f.3 took 28 usecs scan_bus: scanning of bus DOMAIN: 0000 took 6378 usecs scan_bus: scanning of bus Root Device took 6385 usecs done FMAP: Found "FLASH" version 1.1 at 700000. FMAP: base = ff800000 size = 800000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 710000 (65536 bytes) MRC: No data in cbmem for 'RW_MRC_CACHE'. BS: BS_DEV_ENUMERATE times (us): entry 0 run 6425 exit 26 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. PNP: 00ff.1 missing read_resources PNP: 00ff.2 missing read_resources Done reading resources. skipping PNP: 00ff.2@60 fixed resource, size=0! skipping PNP: 00ff.2@62 fixed resource, size=0! skipping PNP: 00ff.2@64 fixed resource, size=0! skipping PNP: 00ff.2@66 fixed resource, size=0! Setting resources... TOUUD 0x47d600000 TOLUD 0x82a00000 TOM 0x400000000 MEBASE 0x7ffff00000 IGD decoded, subtracting 32M UMA and 2M GTT TSEG base 0x80000000 size 8M Available memory below 4GB: 2048M Available memory above 4GB: 14294M PCI: 00:02.0 10 <- [0x00e1400000 - 0x00e17fffff] size 0x00400000 gran 0x16 mem64 PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io PCI: 00:04.0 10 <- [0x00e1a20000 - 0x00e1a27fff] size 0x00008000 gran 0x0f mem64 PCI: 00:19.0 10 <- [0x00e1a00000 - 0x00e1a1ffff] size 0x00020000 gran 0x11 mem PCI: 00:19.0 14 <- [0x00e1a2c000 - 0x00e1a2cfff] size 0x00001000 gran 0x0c mem PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io PCI: 00:1a.0 10 <- [0x00e1a2f000 - 0x00e1a2f3ff] size 0x00000400 gran 0x0a mem PCI: 00:1b.0 10 <- [0x00e1a28000 - 0x00e1a2bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x00e1800000 - 0x00e18fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 10 <- [0x00e1800000 - 0x00e1801fff] size 0x00002000 gran 0x0d mem64 PCI: 00:1c.1 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:1c.1 24 <- [0x00e0c00000 - 0x00e13fffff] size 0x00800000 gran 0x14 bus 02 prefmem PCI: 00:1c.1 20 <- [0x00e0000000 - 0x00e08fffff] size 0x00900000 gran 0x14 bus 02 mem PCI: 02:00.0 10 <- [0x00e0800000 - 0x00e08000ff] size 0x00000100 gran 0x08 mem NONE missing set_resources PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:1c.3 20 <- [0x00e1900000 - 0x00e19fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x00e1900000 - 0x00e1901fff] size 0x00002000 gran 0x0d mem64 PCI: 00:1d.0 10 <- [0x00e1a30000 - 0x00e1a303ff] size 0x00000400 gran 0x0a mem PNP: 00ff.1 missing set_resources PNP: 00ff.2 missing set_resources PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00e1a2e000 - 0x00e1a2e7ff] size 0x00000800 gran 0x0b mem PCI: 00:1f.3 10 <- [0x00e1a31000 - 0x00e1a310ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.6 10 <- [0x00e1a2d000 - 0x00e1a2dfff] size 0x00001000 gran 0x0c mem64 Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1912 exit 0 Enabling resources... PCI: 00:00.0 subsystem <- 17aa/21d2 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 17aa/21d3 PCI: 00:02.0 cmd <- 03 PCI: 00:04.0 cmd <- 02 PCI: 00:19.0 subsystem <- 17aa/21ce PCI: 00:19.0 cmd <- 103 PCI: 00:1a.0 subsystem <- 17aa/21d2 PCI: 00:1a.0 cmd <- 102 PCI: 00:1b.0 subsystem <- 17aa/21d2 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 17aa/21d2 PCI: 00:1c.0 cmd <- 106 PCI: 00:1c.1 bridge ctrl <- 0003 PCI: 00:1c.1 subsystem <- 17aa/21d2 PCI: 00:1c.1 cmd <- 107 PCI: 00:1c.3 bridge ctrl <- 0003 PCI: 00:1c.3 subsystem <- 17aa/21d2 PCI: 00:1c.3 cmd <- 106 PCI: 00:1d.0 subsystem <- 17aa/21d2 PCI: 00:1d.0 cmd <- 102 pch_decode_init PCI: 00:1f.0 subsystem <- 17aa/21d2 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 17aa/21d2 PCI: 00:1f.2 cmd <- 03 PCI: 00:1f.3 subsystem <- 17aa/21d2 PCI: 00:1f.3 cmd <- 103 PCI: 00:1f.6 subsystem <- 17aa/21d2 PCI: 00:1f.6 cmd <- 02 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 cmd <- 06 PCI: 03:00.0 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 0 run 340 exit 0 Found TPM ST33ZP24 by ST Microelectronics TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 TPM: setup succeeded Initializing devices... Root Device init ... Root Device init finished in 1 usecs CPU_CLUSTER: 0 init ... start_eip=0x00001000, code_size=0x00000031 Setting up SMI for CPU Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7ffa38a6(7ffca8c0) Installing SMM handler to 0x80000000 Loading module at 80010000 with entry 80010112. filesize: 0x13d0 memsize: 0x53f0 Processing 48 relocs. Offset value of 0x80010000 Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x80008000 SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd SMM Module: placing jmp sequence at 80007800 rel16 0x07fd SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd SMM Module: stub loaded at 80008000. Will call 80010112(00000000) Initializing southbridge SMI... SMI_STS: MCSMI PM1 GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 TCO_STS: In relocation handler: cpu 0 New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 Writing SMRR. base = 0x80000006, mask=0xff800800 Relocation complete. Locking SMM. Initializing CPU #0 CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 Enabling cache CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 139c0 size 6400 microcode: sig=0x206a7 pf=0x10 revision=0x2d CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. CPU: platform id 4 CPU: cpuid(1) 0x206a7 CPU: AES supported CPU: TXT supported CPU: VT supported MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000047d600000 size 0x37d600000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 36 bits MTRR: default type WB/UC MTRR counts: 4/5. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0 MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x00 done. VMX status: enabled, locked model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2500 Turbo is available but hidden Turbo has been enabled CPU: 0 has 2 cores, 2 threads per core CPU: 0 has core 1 In relocation handler: cpu 1 New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 Writing SMRR. base = 0x80000006, mask=0xff800800 Initializing CPU #1 CPU: 0 has core 2 CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 Enabling cache CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 139c0 size 6400 microcode: sig=0x206a7 pf=0x10 revision=0x2d CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. CPU: platform id 4 CPU: cpuid(1) 0x206a7 CPU: AES supported CPU: TXT supported CPU: VT supported MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 36 bits MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x01 done. VMX status: enabled, locked model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2500 CPU #1 initialized In relocation handler: cpu 2 New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 Writing SMRR. base = 0x80000006, mask=0xff800800 CPU: 0 has core 3 Initializing CPU #2 CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 Enabling cache CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 139c0 size 6400 microcode: sig=0x206a7 pf=0x10 revision=0x0 microcode: updated to revision 0x2d date=2018-02-07 CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. CPU: platform id 4 CPU: cpuid(1) 0x206a7 CPU: AES supported CPU: TXT supported CPU: VT supported MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 36 bits MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x02 done. VMX status: enabled, locked model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2500 CPU #2 initialized In relocation handler: cpu 3 New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 Writing SMRR. base = 0x80000006, mask=0xff800800 CPU #0 initialized Waiting for 1 CPUS to stop Initializing CPU #3 CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 Enabling cache CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 139c0 size 6400 microcode: sig=0x206a7 pf=0x10 revision=0x2d CPU: Intel(R) Core(TM) i5-2520M CPU @ 2.50GHz. CPU: platform id 4 CPU: cpuid(1) 0x206a7 CPU: AES supported CPU: TXT supported CPU: VT supported MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 36 bits MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x03 done. VMX status: enabled, locked model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2500 CPU #3 initialized All AP CPUs stopped (558 loops) CPU_CLUSTER: 0 init finished in 61525 usecs PCI: 00:00.0 init ... Disabling PEG12. Disabling PEG11. Disabling PEG10. Disabling PEG60. Disabling Device 7. Disabling PEG IO clock. Set BIOS_RESET_CPL CPU TDP: 35 Watts PCI: 00:00.0 init finished in 1020 usecs PCI: 00:02.0 init ... GT Power Management Init SNB GT2 Power Meter Weights GT Power Management Init (post VBIOS) bringing up panel at resolution 1600 x 900 Borders 0 x 0 Blank 410 x 12 Sync 42 x 3 Front porch 64 x 3 Spread spectrum clock Dual channel Polarities 1, 1 Data M1=1922389, N1=8388608 Link frequency 270000 kHz Link M1=213598, N1=524288 Pixel N=6, M1=14, M2=7, P1=2 Pixel clock 110000 kHz waiting for panel powerup panel powered up PCI: 00:02.0 init finished in 28062 usecs PCI: 00:04.0 init ... PCI: 00:04.0 init finished in 0 usecs PCI: 00:19.0 init ... PCI: 00:19.0 init finished in 0 usecs PCI: 00:1a.0 init ... EHCI: Setting up controller.. done. PCI: 00:1a.0 init finished in 12 usecs PCI: 00:1b.0 init ... Azalia: base = e1a28000 Azalia: codec_mask = 09 Azalia: Initializing codec #3 Azalia: codec viddid: 80862805 Azalia: No verb! Azalia: Initializing codec #0 Azalia: codec viddid: 14f1506e Azalia: verb_size: 52 Azalia: verb loaded. PCI: 00:1b.0 init finished in 4307 usecs PCI: 00:1c.0 init ... Initializing PCH PCIe bridge. PCI: 00:1c.0 init finished in 10 usecs PCI: 00:1c.1 init ... Initializing PCH PCIe bridge. PCI: 00:1c.1 init finished in 13 usecs PCI: 00:1c.3 init ... Initializing PCH PCIe bridge. PCI: 00:1c.3 init finished in 8 usecs PCI: 00:1d.0 init ... EHCI: Setting up controller.. done. PCI: 00:1d.0 init finished in 12 usecs PCI: 00:1f.0 init ... pch: lpc_init PCH: detected QM67, device id: 0x1c4f, rev id 0x5 IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 Set power off after power failure. NMI sources disabled. CougarPoint PM init RTC: failed = 0x0 RTC Init Disabling ACPI via APMC: done. pch_spi_init PCI: 00:1f.0 init finished in 591 usecs PCI: 00:1f.2 init ... SATA: Initializing... SATA: Controller in AHCI mode. ABAR: e1a2e000 PCI: 00:1f.2 init finished in 94 usecs PCI: 00:1f.3 init ... PCI: 00:1f.3 init finished in 7 usecs PCI: 00:1f.6 init ... PCI: 00:1f.6 init finished in 0 usecs PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 0 usecs PCI: 02:00.0 init ... PCI: 02:00.0 init finished in 0 usecs PCI: 03:00.0 init ... PCI: 03:00.0 init finished in 0 usecs PNP: 00ff.2 init ... PNP: 00ff.2 init finished in 0 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ... I2C: 01:54 init finished in 1 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ... I2C: 01:55 init finished in 1 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ... I2C: 01:56 init finished in 1 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ... I2C: 01:57 init finished in 1 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ... Locking EEPROM RFID init EEPROM done I2C: 01:5c init finished in 26193 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ... I2C: 01:5d init finished in 1 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ... I2C: 01:5e init finished in 1 usecs smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ... I2C: 01:5f init finished in 1 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 16019 run 121991 exit 0 Finalize devices... PCI: 00:1f.0 final Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 47 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3 exit 0 CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 3e2c0 size 35d2 CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 7ff4a000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * SSDT Found 1 CPU(s) with 4 core(s) each. PSS: 2501MHz power 35000 control 0x2000 status 0x2000 PSS: 2500MHz power 35000 control 0x1900 status 0x1900 PSS: 2000MHz power 26404 control 0x1400 status 0x1400 PSS: 1600MHz power 20160 control 0x1000 status 0x1000 PSS: 1200MHz power 14397 control 0xc00 status 0xc00 PSS: 800MHz power 9139 control 0x800 status 0x800 PSS: 2501MHz power 35000 control 0x2000 status 0x2000 PSS: 2500MHz power 35000 control 0x1900 status 0x1900 PSS: 2000MHz power 26404 control 0x1400 status 0x1400 PSS: 1600MHz power 20160 control 0x1000 status 0x1000 PSS: 1200MHz power 14397 control 0xc00 status 0xc00 PSS: 800MHz power 9139 control 0x800 status 0x800 PSS: 2501MHz power 35000 control 0x2000 status 0x2000 PSS: 2500MHz power 35000 control 0x1900 status 0x1900 PSS: 2000MHz power 26404 control 0x1400 status 0x1400 PSS: 1600MHz power 20160 control 0x1000 status 0x1000 PSS: 1200MHz power 14397 control 0xc00 status 0xc00 PSS: 800MHz power 9139 control 0x800 status 0x800 PSS: 2501MHz power 35000 control 0x2000 status 0x2000 PSS: 2500MHz power 35000 control 0x1900 status 0x1900 PSS: 2000MHz power 26404 control 0x1400 status 0x1400 PSS: 1600MHz power 20160 control 0x1000 status 0x1000 PSS: 1200MHz power 14397 control 0xc00 status 0xc00 PSS: 800MHz power 9139 control 0x800 status 0x800 Generating ACPI PIRQ entries \_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0 ACPI: * H8 H8: BDC installed H8: WWAN detection not implemented. Assuming WWAN installed \_SB.PCI0.RP01.WIFI: PCI: 01:00.0 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at 7ff39000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = 7ff4f460 ACPI: * DMAR ACPI: added table 6/32, length now 60 current = 7ff4f510 CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'vbt.bin' CBFS: Found @ offset 397c0 size 572 Found a VBT of 3985 bytes after decompression GMA: Found VBT in CBFS GMA: Found valid VBT in CBFS ACPI: * HPET ACPI: added table 7/32, length now 64 ACPI: done. ACPI tables: 30032 bytes. smbios_write_tables: 7ff38000 Create SMBIOS type 17 PCI: 01:00.0 (unknown) SMBIOS tables: 662 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9fe7 Writing coreboot table at 0x7ff6e000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000001fffffff: RAM 4. 0000000020000000-00000000201fffff: RESERVED 5. 0000000020200000-000000003fffffff: RAM 6. 0000000040000000-00000000401fffff: RESERVED 7. 0000000040200000-000000007ff37fff: RAM 8. 000000007ff38000-000000007ff86fff: CONFIGURATION TABLES 9. 000000007ff87000-000000007ffcefff: RAMSTAGE 10. 000000007ffcf000-000000007fffffff: CONFIGURATION TABLES 11. 0000000080000000-00000000829fffff: RESERVED 12. 00000000f0000000-00000000f3ffffff: RESERVED 13. 00000000fed40000-00000000fed44fff: RESERVED 14. 00000000fed90000-00000000fed91fff: RESERVED 15. 0000000100000000-000000047d5fffff: RAM Manufacturer: c2 SF: Detected MX25L6405D with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [720000:800000) Wrote coreboot table at: 7ff6e000, 0x384 bytes, checksum 8cd2 coreboot table: 924 bytes. IMD ROOT 0. 7ffff000 00001000 IMD SMALL 1. 7fffe000 00001000 CONSOLE 2. 7ffde000 00020000 TIME STAMP 3. 7ffdd000 00000910 ROMSTG STCK 4. 7ffd8000 00005000 AFTER CAR 5. 7ffcf000 00009000 RAMSTAGE 6. 7ff86000 00049000 SMM BACKUP 7. 7ff76000 00010000 COREBOOT 8. 7ff6e000 00008000 ACPI 9. 7ff4a000 00024000 ACPI GNVS 10. 7ff49000 00001000 TCPA TCGLOG11. 7ff39000 00010000 SMBIOS 12. 7ff38000 00000800 IMD small region: IMD ROOT 0. 7fffec00 00000400 MEM INFO 1. 7fffea40 000001a9 ROMSTAGE 2. 7fffea20 00000004 COREBOOTFWD 3. 7fffe9e0 00000028 BS: BS_WRITE_TABLES times (us): entry 0 run 26414 exit 0 CBFS: 'Master Header Locator' located CBFS at [720000:800000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 41900 size 109ca Checking segment from ROM address 0xfff61938 Payload being loaded at below 1MiB without region being marked as RAM usable. Checking segment from ROM address 0xfff61954 Loading segment from ROM address 0xfff61938 code (compression=1) New segment dstaddr 0x000e0620 memsize 0x1f9e0 srcaddr 0xfff61970 filesize 0x10992 Loading Segment: addr: 0x000e0620 memsz: 0x000000000001f9e0 filesz: 0x0000000000010992 using LZMA Loading segment from ROM address 0xfff61954 Entry Point 0x000fec22 BS: BS_PAYLOAD_LOAD times (us): entry 0 run 32682 exit 0 PCH: watchdog disabled Jumping to boot code at 000fec22(7ff6e000) SeaBIOS (version rel-1.12.0-0-ga698c89) BUILD: gcc: (coreboot toolchain v1.50 October 15th, 2017) 6.3.0 binutils: (GNU Binutils) 2.29.1 Found coreboot cbmem console @ 7ffde000 Found mainboard LENOVO ThinkPad T420s Relocating init from 0x000e1c80 to 0x7feeb140 (size 52672) Found CBFS header at 0xfff20038 multiboot: eax=7ffba200, ebx=7ffba1b4 Found 17 PCI devices (max PCI bus is 03) Copying SMBIOS entry point from 0x7ff38000 to 0x000f6620 Copying ACPI RSDP from 0x7ff4a000 to 0x000f65f0 Using pmtimer, ioport 0x508 Scan for VGA option rom Running option rom at c000:0003 pmm call arg1=0 Turning on vga text mode console SeaBIOS (version rel-1.12.0-0-ga698c89) Machine UUID a6cb3501-43e8-11cb-bb58-981377c501c4 XHCI init on dev 03:00.0: regs @ 0xe1900000, 4 ports, 32 slots, 32 byte contexts XHCI extcap 0x1 @ 0xe1900500 XHCI protocol USB 3.00, 2 ports (offset 1), def 0 XHCI protocol USB 2.00, 2 ports (offset 3), def 0 EHCI init on dev 00:1a.0 (regs=0xe1a2f020) EHCI init on dev 00:1d.0 (regs=0xe1a30020) AHCI controller at 00:1f.2, iobase 0xe1a2e000, irq 10 Searching bootorder for: /pci@i0cf8/pci-bridge@1c,1/*@0 Found 0 lpt ports Found 0 serial ports Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0 AHCI/1: registering: "DVD/CD [AHCI/1: MATSHITADVD-RAM UJ8A2 ATAPI-7 DVD/CD]" XHCI no devices found Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 AHCI/0: Set transfer mode to UDMA-6 AHCI/0: registering: "AHCI/0: SAMSUNG SSD 830 Series ATA-9 Hard-Disk (119 GiBytes)" Initialized USB HUB (0 ports used) WARNING - Timeout at ps2_recvbyte:182! WARNING - Timeout at ps2_recvbyte:182! Discarding ps2 data aa (status=11) WARNING - Timeout at ps2_recvbyte:182! WARNING - Timeout at ps2_keyboard_setup:498! WARNING - Timeout at ehci_wait_td:516! ehci pipe=0x7fee9000 cur=7fed7dc0 tok=80080d80 next=7fed7e00 td=0x7fed7dc0 status=80080d80 Initialized USB HUB (0 ports used) All threads complete. Scan for option roms Press ESC for boot menu. Searching bootorder for: HALT drive 0x000f6530: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=250069680 Space available for UMB: c7000-ed000, f5e40-f6500 Returned 245760 bytes of ZoneHigh e820 map has 13 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000020000000 = 1 RAM 4: 0000000020000000 - 0000000020200000 = 2 RESERVED 5: 0000000020200000 - 0000000040000000 = 1 RAM 6: 0000000040000000 - 0000000040200000 = 2 RESERVED 7: 0000000040200000 - 000000007ff34000 = 1 RAM 8: 000000007ff34000 - 0000000082a00000 = 2 RESERVED 9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED 10: 00000000fed40000 - 00000000fed45000 = 2 RESERVED 11: 00000000fed90000 - 00000000fed92000 = 2 RESERVED 12: 0000000100000000 - 000000047d600000 = 1 RAM enter handle_19: NULL Booting from DVD/CD... Device reports MEDIUM NOT PRESENT scsi_is_ready returned -1 Boot failed: Could not read from CDROM (code 0003) enter handle_18: NULL Booting from Hard Disk... Booting from 0000:7c00

2 2

Microcode in ROM is not loaded with X60s
by Masanori Ogino 04 Mar '19

04 Mar '19

Dear Coreboot developers, I installed Coreboot with ThinkPad X60s and Debian 9 and they run successfully, but I observe a weird behavior. Even though I had enabled blob for microcode update, the system seems to run without it. I saw the following message in dmesg: (I think this is not fatal since this is related to temperature monitoring, though.) > coretemp: Errata AE18 not fixed, update BIOS or microcode of the CPU! For comparison, I had installed `intel-microcode` package to the system and then the message disappeared. Is this intended behavior, misconfiguration, or a real bug? For reference, I uploaded the content of /proc/cpuinfo before and after the installation of `intel-microcode` package: https://gist.github.com/omasanori/4a1316bd78d95069f287431f5bd3a176 Also, I uploaded a report to board-status: https://review.coreboot.org/cgit/board-status.git/commit/?id=af91ae4946fec9… (I had also tried to install FreeBSD 12.0 and OpenBSD 6.4 but both of their installers failed to boot just after the kernel is loaded and located. I am not sure if this is related to this or not.) Best regards, Masanori -- Masanori Ogino

2 3

Shubhendra - GSoC proposal Inquiry about "Port payloads to RISC-V"
by Shubhendra Singhal 04 Mar '19

04 Mar '19

Dear Sir/Ma'am, I am Shubhendra Pal Singhal, currently third year in Computer Science at NIT Trichy, India. I wish to apply for Google Summer of Code. I looked into the profile of coreboot 4.9 and found out the project idea "*Port payloads to ARM, AArch64, MIPS or RISC-V*" to be very interesting. I have worked in the similar field on *RISCV architecture at IIT Madras where I helped in porting real time OS eChronos*, on RISCV architecture. I will be undergoing a *project in Embedded systems offered by USC Los Angeles in solving the SAT Solvers using OS and Digital Logic*. Furthermore, I am currently working on a *long term project with under Prof. N.Ramasubramanium on the AI chip* where we are trying to solve the processing speeds by efficiently reducing the number of writes in the cache for faster access. I am also *undergoing Microcontrollers and Microprocessors* as my core subject in my current semester and have already* undergone OS, Real time Systems* in my B.Tech IV semester. I have included my further details in my Linkedin : * <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/>https://www.linkedin.com/in/ <https://www.linkedin.com/in/>shubhendra-singhal-7378a9131/* I want to contribute to the open source community in the field of Operating Systems and this can prove to be an excellent platform for gaining experience in field of systems. This opportunity can pave my career, towards applied research in the field of Systems. *While browsing through the link, I saw the mailing list assigned for the project. It would be very useful if you could guide me as to what is expected in the project proposal and how can I serve the open source community in the best possible way. *Any guidance would be very useful and I hope to receive a reply soon. Thanking you for your time and consideration. Regards Shubhendra Pal Singhal National Institute Of Technology, Trichy, India Phone number : +91 9787888015 Email-id : shubhendrapalsinghal(a)gmail.com Linkedin : <https://www.linkedin.com/in/shubhendra-singhal-7378a9131/> https://www.linkedin.com/in/shubhendra-singhal-7378a9131/

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Get a working bootsplash.bmp BMP splashscreen for SeaBIOS with this ImageMagick command
by Mike Banon 02 Mar '19

02 Mar '19

Why BMP? It's a lossless image format which could be LZMA compressed quite well depending on the image's variety of colours. And finally I found out how to get a working splash screen - instructions tested on AMD Lenovo G505S laptop with 1366x768 screen resolution : 1) Install the ImageMagick package, it has a "convert" tool. 2) Find a cool image, preferably in a lossless format like PNG (certainly not a lossy JPEG!), resize it to your screen resolution - e.g. to 1366x768 in this particular case - and save it, preferably as PNG. 3) Now you could convert this image into BMP format recognizable by SeaBIOS: convert ./wallpaper.png -alpha set -verbose -depth 32 ./bootsplash.bmp 4) Then add it to your coreboot.rom image, with LZMA compression of course - because without a compression those BMPs are too large: ./coreboot/build/cbfstool ./coreboot/build/coreboot.rom add -f ~/Downloads/bootsplash.bmp -n bootsplash.bmp.lzma -t raw -c lzma 5) And finally flash the updated image, e.g. at G505S it could be flashed internally: sudo ./flashrom/flashrom -p internal:laptop=force_I_want_a_brick,amd_imc_force=yes -w ./coreboot/build/coreboot.rom Hope it's helpful! Best regards, Mike Banon

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Intel Braswell uploads
by Frans Hendriks 01 Mar '19

01 Mar '19

Hi, I'm working on Intel Braswell implementation and uploaded several patches. It seems that the maintainer of the Intel Braswell is not active for review/merge/reply of the uploads. Is the maintainer in MAINTAINERS document correct and still active? Met vriendelijke groet / Best regards, Frans Hendriks Eltan B.V.

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coreboot March 2019