coreboot June 2007

coreboot@coreboot.org

76 participants
285 discussions

[LinuxBIOS] Add initial support for intel i855gme northbridge
by Jon Dufresne 20 Jan '09

20 Jan '09

Add initial support for i855gme. This is a work in progress and I don't expect it to work on all boards, or even any besides mine. This is based heavily on i855pm. Signed off by Jon Dufresne <jon.dufresne(a)gmail.com>

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[LinuxBIOS] [RFC] i82801 generic patch
by Corey Osgood 30 Dec '07

30 Dec '07

The attached patch is a unified version of the current ports of the i82801 series currently in LinuxBIOS. Since most of the ports are nearly identical, I've taken for each file and chosen the cleanest or best version of the code, then checked over the datasheets to *some* of the series, including the aa, ba, ca, and db, to make sure that it would work. I've also made some changes here and there, mostly cleanup and clarification. The only things left to look at are the huge difference between this version's lpc init and the i82801er's, finding a better way to select which chip is present on the board, and gpl headers in all files. Anyways, comments, suggestions, even flames are welcome ;) Testing on other chips can be done at this point as well, this is tested and working on one model, the i82801aa. -Corey

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[LinuxBIOS] [PATCH] Remove Bitworks IMS
by Corey Osgood 01 Dec '07

01 Dec '07

Well, as there seems to be a lot of cleaning up going on lately, might as well add this to the docket. The attached patch removes the Bitworks IMS, as 1) there's no video support for it, 2) no one objected when this was discussed previously, and 3) no one seems to have one, and they aren't readily available. Any comments are welcome. Signed-off-by: Corey Osgood <corey_osgood(a)verizon.net>

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[LinuxBIOS] my zepto.se laptop info
by Peter Brännvall 14 Oct '07

14 Oct '07

2 1

[LinuxBIOS] [patch] flashrom: add support for Asus P5A
by Luc Verhaegen 26 Aug '07

26 Aug '07

Here's the chip_enable code for the ALI M1533 and the board_enable for the Asus P5A, an ALI M1541+M1533 socket 7 motherboard. It's quite nasty: It does an SMBUS read/write to a yet unidentified device, i think it is the superio, but i'm not sure. The Asus P5A also seriously messes up pci-ids, there is nothing dependable there, so people who want to use flashrom on this board should use -m asus:p5a but it works :) This is a board i own myself and this has been tested successfully. Luc Verhaegen.

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[LinuxBIOS] [PATCH] Reimplementation/fixing of CS5530/CS5530A southbridge code
by Uwe Hermann 16 Aug '07

16 Aug '07

See patch. This is also required to make the JUKI-511P code work AFAICT (won't build otherwise). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] PIRQ REF DES AMD LXUVCRDK
by Otávio Alcântara 01 Aug '07

01 Aug '07

Hello to all, I'm porting a linuxbios v2 version for a board ref des LXUVCRDK ( http://www.amd.com/geodelxuvcrdk) based on norwich board. I've already got to boot linux from HD, but it seems to halt in some point (see log below captured from serial). Although, I'm using VSA (lx_vsa.36k.bin) and I got no output from video VGA. I'd like some help for setting up the PIRQ table and for VGA setup. PS: The schematics for this board are publicly available from AMD Embedded Developer Web Site. Thanks, -- Otávio Alcântara "I'll never cross to the Dark Side." LinuxBIOS-2.0.0.0Fallback Qua Jun 20 07:45:43 BRT 2007 starting... _MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000498:00001820 Configuring PLL LinuxBIOS-2.0.0.0Fallback Qua Jun 20 07:45:43 BRT 2007 starting... _MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000498:07de0020 Done cpuRegInit SMBUS READ ERROR:03 device:a2 Ram1.00 Ram2.00 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 Ram3 DRAM controller init done. RAM DLL lock Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Fallback Qua Jun 20 08:56:35 BRT 2007 booting... clocks_per_usec: 432 Enumerating buses... >> Entering northbridge.c: pci_domain_enable Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 writeglmsr: MSR 0x1000002c, val 0x20000000:0x00000003 sizeram: _MSR MC_CF07_DATA: 10076112:00004840 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10076112:00004840 sizeram: sizem 0x100MB SMMGL0Init: 268304384 bytes SMMGL0Init: offset is 0x80400000 SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 writeglmsr: MSR 0x4000002e, val 0x20000000:0x00000003 sizeram: _MSR MC_CF07_DATA: 10076112:00004840 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 L2 cache enabled Enabling cache GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 Exit northbridge_init_early Done cpubug fixes Not Doing ChipsetFlashSetup() <<<WARNING>>> Graphics init... <<WARNING!!!>>> VRC_VG value: 0xffff Before VSA: do_vsmbios buf ilen 35441 olen60466 buf 00060000 *buf 186 buf[256k] 0 buf[0x20] signature is b0:10:e6:80 Call real_mode_switch_call_vsm biosint: INT# 0x15 biosint: eax 0xbea7 ebx 0x4e53 ecx 0x10000026 edx 0x10000028 biosint: ebp 0x15ed4 esp 0xff0 edi 0x8a71 esi 0x38 biosint: ip 0x5b3 cs 0x6000 flags 0x46 biosint: gs 0x0 fs 0x0 ds 0x6000 es 0x0 handleint21, eax 0xbea7 biosint: INT# 0x15 biosint: eax 0xbea4 ebx 0x4e53 ecx 0x10000026 edx 0x10000028 biosint: ebp 0x15ed4 esp 0xfee edi 0x8a71 esi 0x38 biosint: ip 0x5c1 cs 0x6000 flags 0x46 biosint: gs 0x0 fs 0x0 ds 0x6000 es 0x0 handleint21, eax 0xbea4 do_vsmbios: VSA2 VR signature verified After VSA: <<<WARNING>>> Graphics init... <<WARNING!!!>>> VRC_VG value: 0x2808 Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [1022/2080] enabled PCI: 00:01.1 [1022/2081] enabled PCI: 00:01.2 [1022/2082] enabled PCI: 00:0d.0 [10ec/8139] enabled PCI: 00:0f.0 [1022/2090] enabled PCI: 00:0f.2 [1022/209a] enabled PCI: 00:0f.3 [1022/2093] enabled PCI: 00:0f.4 [1022/2094] enabled PCI: 00:0f.5 [1022/2095] enabled PCI: 00:0f.6 [1022/2096] enabled PCI: 00:0f.7 [1022/2097] enabled PCI: pci_scan_bus returning with max=000 done Allocating resources... Reading resources... Done reading resources. Setting resources... PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] mem PCI: 00:01.1 14 <- [0x00fe000000 - 0x00fe003fff] mem PCI: 00:01.1 18 <- [0x00fe004000 - 0x00fe007fff] mem PCI: 00:01.1 1c <- [0x00fe008000 - 0x00fe00bfff] mem PCI: 00:01.1 20 <- [0x00fe00c000 - 0x00fe00ffff] mem PCI: 00:01.2 10 <- [0x00fe010000 - 0x00fe013fff] mem PCI: 00:0d.0 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:0d.0 14 <- [0x00fe019000 - 0x00fe0190ff] mem PCI: 00:0f.0 10 <- [0x0000001cb0 - 0x0000001cb7] io PCI: 00:0f.0 14 <- [0x0000001400 - 0x00000014ff] io PCI: 00:0f.0 18 <- [0x0000001c00 - 0x0000001c3f] io PCI: 00:0f.0 1c <- [0x0000001c80 - 0x0000001c9f] io PCI: 00:0f.0 20 <- [0x0000001800 - 0x000000187f] io PCI: 00:0f.0 24 <- [0x0000001c40 - 0x0000001c7f] io PCI: 00:0f.2 20 <- [0x0000001ca0 - 0x0000001caf] io PCI: 00:0f.3 10 <- [0x0000001880 - 0x00000018ff] io PCI: 00:0f.4 10 <- [0x00fe016000 - 0x00fe016fff] mem PCI: 00:0f.5 10 <- [0x00fe017000 - 0x00fe017fff] mem PCI: 00:0f.6 10 <- [0x00fe014000 - 0x00fe015fff] mem PCI: 00:0f.7 10 <- [0x00fe018000 - 0x00fe018fff] mem Done setting resources. Done allocating resources. Enabling resources... PCI: 00:01.0 cmd <- 145 PCI: 00:01.1 subsystem <- 00/00 PCI: 00:01.1 cmd <- 142 PCI: 00:01.2 cmd <- 142 PCI: 00:0d.0 cmd <- 143 cs5536: cs5536_pci_dev_enable_resources() PCI: 00:0f.0 cmd <- 149 PCI: 00:0f.2 cmd <- 141 PCI: 00:0f.3 cmd <- 141 PCI: 00:0f.4 cmd <- 142 PCI: 00:0f.5 cmd <- 142 PCI: 00:0f.6 cmd <- 142 PCI: 00:0f.7 cmd <- 142 done. Initializing devices... Root Device init Norwich ENTER init Norwich EXIT init PCI: 00:01.0 init PCI: 00:01.1 init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device 5a2 CPU: family 05, model 0a, stepping 02 model_lx_init Enabling cache A20 (0x92): 2 A20 (0x92): 2 CPU model_lx_init DONE CPU #0 Initialized PCI: 00:01.2 init PCI: 00:0d.0 init PCI: 00:0f.0 init cs5536: southbridge_init RTC Init rct_init finished cs5536: southbridge_init: enable_ide_nand_flash is 36 Disabling VPCI device: 0x0000106C Disabling VPCI device: 0x00001075 Disabling VPCI device: 0x0000107E Disabling VPCI device: 0x00001087 Disabling VPCI device: 0x00001090 Disabling VPCI device: 0x00001099 Disabling VPCI device: 0x000010A2 Disabling VPCI device: 0x000010AB PCI: 00:0f.2 init PCI: 00:0f.3 init PCI: 00:0f.4 init PCI: 00:0f.5 init PCI: 00:0f.6 init PCI: 00:0f.7 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 /home/otavio/LinuxBIOSv2/src/arch/i386/boot/pirq_routing.c: 36:check_pirq_routing_table() - checksum is: 0x00 but should be: 0xfd done. write_pirq_routing_table(8000785C, BAAA) PIR Entry 0 Dev/Fn: 8 Slot: 0 INT: A bitmap: 400 PIRQ: 10 INT: B bitmap: 0 PIRQ: 0 INT: C bitmap: 0 PIRQ: 0 INT: D bitmap: 0 PIRQ: 0 Assigning IRQ 10 to 0:1.1 Readback = 10 Assigning IRQ 10 to 0:1.2 Readback = 10 PIR Entry 1 Dev/Fn: 78 Slot: 0 INT: A bitmap: 400 PIRQ: 10 INT: B bitmap: 400 PIRQ: 10 INT: C bitmap: 400 PIRQ: 10 INT: D bitmap: 800 PIRQ: 11 Assigning IRQ 10 to 0:f.3 Readback = 10 Assigning IRQ 11 to 0:f.4 Readback = 11 Assigning IRQ 11 to 0:f.5 Readback = 11 PIR Entry 2 Dev/Fn: 68 Slot: 1 INT: A bitmap: 400 PIRQ: 10 INT: B bitmap: 400 PIRQ: 10 INT: C bitmap: 800 PIRQ: 11 INT: D bitmap: 400 PIRQ: 10 Assigning IRQ 10 to 0:d.0 Readback = 10 PIR Entry 3 Dev/Fn: 70 Slot: 2 INT: A bitmap: 400 PIRQ: 10 INT: B bitmap: 800 PIRQ: 11 INT: C bitmap: 400 PIRQ: 10 INT: D bitmap: 400 PIRQ: 10 PIR Entry 4 Dev/Fn: 58 Slot: 3 INT: A bitmap: 800 PIRQ: 11 INT: B bitmap: 400 PIRQ: 10 INT: C bitmap: 400 PIRQ: 10 INT: D bitmap: 400 PIRQ: 10 PIR Entry 5 Dev/Fn: 60 Slot: 4 INT: A bitmap: 400 PIRQ: 10 INT: B bitmap: 400 PIRQ: 10 INT: C bitmap: 400 PIRQ: 10 INT: D bitmap: 800 PIRQ: 11 Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote linuxbios table at: 00000530 - 000006c4 checksum fba9 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfff89000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x306e0 offset 0xc0 filesize 0xb248 (cleaned up) New segment addr 0x100000 size 0x306e0 offset 0xc0 filesize 0xb248 New segment addr 0x1306e0 size 0x48 offset 0xb320 filesize 0x48 (cleaned up) New segment addr 0x1306e0 size 0x48 offset 0xb320 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000306e0 filesz: 0x000000000000b248 Clearing Segment: addr: 0x000000000010b248 memsz: 0x0000000000025498 Loading Segment: addr: 0x00000000001306e0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x108bdc FILO version 0.5 (otavio@labdes15) Wed Jun 20 08:56:24 BRT 2007 collect_linuxbios_info: Searching for LinuxBIOS tables... find_lb_table: Found canidate at: 00000530 find_lb_table: header checksum o.k. find_lb_table: table checksum o.k. find_lb_table: record count o.k. collect_linuxbios_info: Found LinuxBIOS table at: 00000530 convert_memmap: 0x00000000000000 0x00000000001000 16 convert_memmap: 0x00000000001000 0x0000000009f000 1 convert_memmap: 0x000000000f0000 0x00000000010000 16 convert_memmap: 0x00000000100000 0x0000000f6e0000 1 Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/boot/vmlinuz root=/dev/hda1 initrd=/boot/initrd console=tty0 console=ttyS0,115200 hda: LBA 40GB: ST340014A Mounted ext2fs Found Linux version 2.6.8-2-386 (horms(a)tabatha.lab.ultramonkey.org) #1 Thu May 19 17:40:50 JST 2005 (protocol 0x203) (loadflags 0x1) bzImage. init_linux_params: Setting up paramters at 0x90000 set_memory_size: 0000000000001000 - 00000000000a0000 set_memory_size: 0000000000100000 - 000000000f7e0000 set_memory_size: ramtop=0xf7e0000 set_memory_size: ext_mem_k=64512, alt_mem_k=252800 parse_command_line: original command line: "root=/dev/hda1 initrd=/boot/initrd console=tty0 console=ttyS0,115200" parse_command_line: kernel command line at 0x91000 parse_command_line: initrd=/boot/initrd parse_command_line: kernel command line (48 bytes): "root=/dev/hda1 console=tty0 console=ttyS0,115200" load_linux_kernel: offset=0x1600 addr=0x100000 size=0x10a8cb Loading kernel... ok load_initrd: start=0xf391000 end=0xf7af000 Loading initrd... ok start_linux: eip=0x100000 Jumping to entry point... Linux version 2.6.8-2-386 (horms(a)tabatha.lab.ultramonkey.org) (gcc version 3.3.5 (Debian 1:3.3.5-12)) #1 Thu May 19 17:40:50 JST 2005 BIOS-provided physical RAM map: BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) BIOS-e820: 0000000000100000 - 000000000f7e0000 (usable) 247MB LOWMEM available. DMI not present. ACPI: Unable to locate RSDP Built 1 zonelists Kernel command line: root=/dev/hda1 console=tty0 console=ttyS0,115200 No local APIC present or hardware disabled Initializing CPU#0 PID hash table entries: 1024 (order 10: 8192 bytes) Detected 431.857 MHz processor. Using tsc for high-res timesource Console: colour dummy device 80x25 Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) Memory: 244168k/253824k available (1336k kernel code, 8916k reserved, 732k data, 204k init, 0k highmem) Checking if this processor honours the WP bit even in supervisor mode... Ok. Calibrating delay loop... 845.82 BogoMIPS Security Scaffold v1.0.0 initialized Mount-cache hash table entries: 512 (order: 0, 4096 bytes) CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line) CPU: L2 Cache: 128K (32 bytes/line) CPU: AMD Geode(TM) Integrated Processor by AMD PCS stepping 02 Checking 'hlt' instruction... OK. Checking for popad bug... OK. checking if image is initramfs...it isn't (ungzip failed); looks like an initrd Freeing initrd memory: 4216k freed NET: Registered protocol family 16 EISA bus registered PCI: Using configuration type 1 mtrr: v2.0 (20020519) ACPI: Subsystem revision 20040326 ACPI: Interpreter disabled. Linux Plug and Play Support v0.97 (c) Adam Belay PnPBIOS: Scanning system for PnP BIOS support... PnPBIOS: PnP BIOS support was not detected. PCI: Probing PCI hardware PCI: Probing PCI hardware (bus 00) PCI: Using IRQ router default [1022/2090] at 0000:00:0f.0 VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) devfs: 2004-01-31 Richard Gooch (rgooch(a)atnf.csiro.au) devfs: boot_options: 0x0 Initializing Cryptographic API isapnp: Scanning for PnP cards... isapnp: No Plug & Play device found Serial: 8250/16550 driver $Revision: 1.90 $ 54 ports, IRQ sharing enabled ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize i8042.c: Can't read CTR while initializing i8042. EISA: Probing bus 0 at eisa0 Cannot allocate resource for EISA slot 1 EISA: Detected 0 cards. NET: Registered protocol family 2 IP: routing cache hash table of 2048 buckets, 16Kbytes TCP: Hash tables configured (established 16384 bind 32768) NET: Registered protocol family 8 NET: Registered protocol family 20 RAMDISK: cramfs filesystem found at block 0 RAMDISK: Loading 4216 blocks [1 disk] into ram disk... |/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\done. VFS: Mounted root (cramfs filesystem) readonly. Freeing unused kernel memory: 204k freed vesafb: probe of vesafb0 failed with error -6 NET: Registered protocol family 1 Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx hda: ST340014A, ATA DISK drive Using anticipatory io scheduler ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 hda: max request size: 128KiB hda: 78165360 sectors (40020 MB) w/2048KiB Cache, CHS=65535/16/63 /dev/ide/host0/bus0/target0/lun0: p1 p2 < p5 >

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[LinuxBIOS] new target iei juki-511p/rocky-512
by Nikolay Petukhov 25 Jul '07

25 Jul '07

Hi, 2007/6/3, Stefan Reinauer <stepan(a)coresystems.de>: > Please sign off the patch according to > http://www.linuxbios.org/Development_Guidelines#Sign-off_Procedure > so we can check this patch in! Add sign-off. 2007/6/3, Juergen Beisert <juergen127(a)kreuzholzen.de>: > As your dmesg output shows, the graphical console is active. I missed > something to setup correctly. When my LinuxBIOS activates the VGA the linux > console runs as expected. Without it, everything seems ok, but no output > occures. I don't know why, yet. How You activates VGA in LinuxBios? 2007/6/3, Uwe Hermann <uwe(a)hermann-uwe.de>: > On Sun, Jun 03, 2007 at 12:20:10AM +0600, Nikolay Petukhov wrote: > > Problems: > > Filo load bzImage only from ide0. > > What does not work? ide1? AFAICS the boards only have one IDE port!? The this boards has two IDE ports. IDE0 has 40-pin IDE connector. IDE1 has CF connector. > > diff -Nru LinuxBIOSv2-2700/src/mainboard/iei/juki511p/auto.c LinuxBIOSv2-2700-juki/src/mainboard/iei/juki511p/auto.c > > --- LinuxBIOSv2-2700/src/mainboard/iei/juki511p/auto.c 1970-01-01 05:00:00.000000000 +0500 > > +++ LinuxBIOSv2-2700-juki/src/mainboard/iei/juki511p/auto.c 2007-06-02 20:02:10.000000000 +0600 > > Please rename the directory to 'juki-511p' if possible, as that seems to be > the canonical (lowercase'd) name used by the vendor. I had change directory name to 'juki_511p'. > > +#include "superio/winbond/w83977fa/w83977fa_early_serial.c" > > Maybe this should be 'w83977f' (without the 'a')? IIRC, we omitted any > '-A' or '-AW' suffix from other Super I/Os, too. Comments anyone? I agree. I did it. > > > > +void udelay(int usecs) > > +{ > > + int i; > > + for(i = 0; i < usecs; i++) > > + outb(i&0xff, 0x80); > > +} > > Is this needed? There's a global implementation in the repository > already. > I removed it. > > > + device pnp 3f0.4 on # RTC > > + end > > Is this ok if left empty? > > My 'lspnp -v' (on another mainboard) says: > > 00:04 PNP0b00 AT real-time clock > state = active > io 0x70-0x71 > irq 8 > > So maybe something like > > device pnp 3f0.4 on # RTC > io 0x60 = 0x70 > irq 0x70 = 8 > end > > is needed here? I'm just guessing, though, please correct me if I'm > wrong. > > > > + device pnp 3f0.5 on # Keyboard > > + io 0x60 = 0x60 > > + io 0x62 = 0x64 > > + irq 0x70 = 0x01 # int 1 for PS/2 keyboard > > + irq 0x72 = 0x0c # int 12 for PS/2 mouse > > Why not like this? Easier to read, IMHO: > > irq 0x70 = 1 # int 1 for PS/2 keyboard > irq 0x72 = 12 # int 12 for PS/2 mouse > > +const struct irq_routing_table intel_irq_routing_table = { > > + PIRQ_SIGNATURE, /* u32 signature */ > > + PIRQ_VERSION, /* u16 version */ > > + 32+16*2, /* There can be total 6 devices on the bus */ > ^ > typo? ---> 2? > > Maybe even > > 32+16*IRQ_SLOT_COUNT, /* There can be IRQ_SLOT_COUNT devices on the bus */ I corrected it. > > diff -Nru LinuxBIOSv2-2700/src/northbridge/amd/gx1/raminit.c LinuxBIOSv2-2700-juki/src/northbridge/amd/gx1/raminit.c > > --- LinuxBIOSv2-2700/src/northbridge/amd/gx1/raminit.c 2005-07-06 23:11:02.000000000 +0600 > > +++ LinuxBIOSv2-2700-juki/src/northbridge/amd/gx1/raminit.c 2007-05-31 16:06:40.000000000 +0600 > > @@ -324,6 +324,7 @@ > > outb(0x70, 0x80); > > > > setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */ > > +// setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92080000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=2.5 */ > > setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */ > > setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00700070); /* No DIMMS installed */ > > setGX1Mem(GX_BASE + MC_SYNC_TIM1, 0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */ > > OK, not sure what we should do with this. Will it break other GX1-based > mainboards? Or is it generic for all GX1s? I removed it. > > diff -Nru LinuxBIOSv2-2700/src/superio/winbond/w83977fa/chip.h LinuxBIOSv2-2700-juki/src/superio/winbond/w83977fa/chip.h > > --- LinuxBIOSv2-2700/src/superio/winbond/w83977fa/chip.h 1970-01-01 05:00:00.000000000 +0500 > > +++ LinuxBIOSv2-2700-juki/src/superio/winbond/w83977fa/chip.h 2007-06-02 18:52:57.000000000 +0600 > > Please provide an extra patch for the addition of the new Super I/O, > this is independant of the mainboards... > > > > diff -Nru LinuxBIOSv2-2700/targets/iei/juki511p/Config.lb LinuxBIOSv2-2700-juki/targets/iei/juki511p/Config.lb > > --- LinuxBIOSv2-2700/targets/iei/juki511p/Config.lb 1970-01-01 05:00:00.000000000 +0500 > > +++ LinuxBIOSv2-2700-juki/targets/iei/juki511p/Config.lb 2007-06-02 19:07:21.000000000 +0600 > > Please add a copyright header to this file, too. Signed-off-by: Nikolay Petukhov <nikolay.petukhov(a)gmail.com> -- Nikolay -----------------------------------------------------------------

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[LinuxBIOS] Flashrom move into global util/ directory
by Uwe Hermann 10 Jul '07

10 Jul '07

Hi all, please note that we're planning to create a new top-level directory 'util' in svn where independant utilities (which are not tied to a certain LinuxBIOS version) will reside. One of these utilities will be flashrom, but others will follow. The new repository layout will look like this: - trunk - LinuxBIOSv1 - LinuxBIOSv2 - LinuxBIOSv3 (later) - util - flashrom - ... The current trunk/LinuxBIOSv2/util/flashrom will be moved into trunk/util per 'svn mv', so the history will remain intact. trunk/LinuxBIOSv2/util/flashrom will then become a svn:externals entry, that is, it will still _look_ like it's in the LinuxBIOSv2 tree, but it'll actually be checked out from trunk/util/flashrom. LinuxBIOSv3 will probably also "get" flashrom via svn:externals into the util/flashrom directory. The transition should be painless (a simple 'svn up' should do), but just in case there are problems, please make sure you save all pending flashrom patches/modifications you may have. If there are problems please let us know (try a fresh checkout before, though). If nobody objects, I'll perform the required actions later this day or tomorrow. Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] Gigabyte contact
by Alan Carvalho de Assis 03 Jul '07

03 Jul '07

Hi guys, I am looking for gigabyte contacts to request a mainboard donation because I want add support to it on LBdistro. I contacted Gigabyte Brazil (Digitrom) but they don't manufacture this board here in Brazil and don't make efforts to contact Gigabyte international do request one. Then if someone has a channel of communication with Gigabyte let me know. Cheers, Alan

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coreboot June 2007