May 2019 - coreboot - mail.coreboot.org

by up6IfzRzvQCyv9AK4XvYirxDa8

Hello, I bought the motherboard ASUS KCMA-D8 to set up a coreboot + Qubes OS workstation. However, I don't find a combination of coreboot + CPU + RAM that works. I have also tried the latest libreboot and it works in most cases, but does not provide microcode updates. For test purposes I tried 41xx/42xx/43xx Opterons. The error message I get in most cases on the serial null-modem port is: DIMM training FAILED! Restarting system...soft_reset() called! I following RAM modules has been used: - M391B1G73BH0-CK0 (8GB PC3L-12800 UDIMM ECC) // NOK - NT8GC72B4NB1NK-CG (8GB PC3PC3-10600 RDIMM ECC) //NOK - HMT325U7BFR8A (2GB PC3-10600 UDIMM ECC ) //OK, see https://www.raptorengineering.com/coreboot/kcma-d8-status.php There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180. Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I tried many combinations of RAM modules + CPU + coreboot versions (4.6, 4.7, 4.8, 4.9) but get the above "DIMM training FAILED..." error message in most cases. Any ideas or recommendations for RAM modules that are supported so that a workstation with 32GB or better 64GB can be built? Or why libreboot works and coreboot doesn't? Thank you. 4225 / #005.log (1x NT8GC72B4NB1NK-CG) // NOK ====================================== coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting... .. .. AutoCycTiming_D: Start mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected mct_MaxLoadFreq: More than 1 registered DIMM on 1500mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done activate_spd_rom() for node 00 enable_spd_node0() DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 24000 TrainDQSReceiverEnCyc: ErrStatus 24000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done DQSTiming_D: Restarting training on algorithm request SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0004 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2205 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done activate_spd_rom() for node 00 enable_spd_node0() DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSReceiverEnCyc_D_Fam15: lane 0 failed to train! Training for receiver 2 on DCT 0 aborted TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 44000 TrainDQSReceiverEnCyc: ErrStatus 44000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done DIMM training FAILED! Restarting system...soft_reset() called! 4180 #002.log (1x NT8GC72B4NB1NK-CG) // OK ==================================== coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting... .. .. AutoCycTiming_D: Start mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected mct_MaxLoadFreq: 1 registered DIMM on 1500mV channel; limiting to DDR3-1333 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00090092 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 000000a0 AutoConfig_D: DramConfigLo: 00082100 AutoConfig_D: DramConfigHi: 0f48000b mct_SetDramConfigHi_D: Start mct_SetDramConfigHi_D: DramConfigHi: 1f48010b mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done InitPhyCompensation: DCT 0: Start InitPhyCompensation: DCT 0: Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:2400000 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done activate_spd_rom() for node 00 enable_spd_node0() activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start ChangeMemClk: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 2205 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 2205 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 2205 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECC enabled on node: 00 DCTMemClr_Sync_D: Start DCTMemClr_Sync_D: Waiting for memory clear to complete..............

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BUG: Seabios choose the wrong option rom when two are available

by akjuxr3＠dismail.de

In this thread https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/FT... we found a bug in seabios. Its choosing the wrong option rom in the case when for example on a Intel G41 board you have the internal Intel GPU and have added a external PCIe GPU. Then coreboot switches over to the external GPU for the graphical output but seabios use the option rom for the Intel G41 GPU. In case of x4x/G41 this results in no ability to have a graphical boot mode and thus its not possible to boot some linux live images. In the linked thread a workaround is been found: "In the "Devices" menu of coreboot, set "Graphics initialization" to "None" ". This breaks the functionality to have coreboot output with the internal GPU when you pull out the PCIe GPU. The switch should happen automaticly and without the need to recompile/reconfigure coreboot. Changes like https://review.coreboot.org/c/coreboot/+/18504 was made to make this happen. Would be great if this seabios issue could be fixes. Thanks!

1 week, 2 days

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Chainloading Windows from a Linux Payload

by Matt B

Greetings, From what I can find, Linux can only chainload another linux kernel. (via kexec) Does this mean that a Linux payload like LinuxBoot cannot be used to boot Windows or another OS, either directly or by chainloading another payload from CBFS? It's nice that a Linux payload can provide superior flexibility and configurability than UEFI with the added benefit of a battle-hardened environment, but the ability to only boot a Linux OS seems like a pretty significant limitation (if this is indeed the case). Sincerely, -Matt

1 week, 6 days

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How to enable the SMBus0 in coreboot for Intel Atom C2000?

by dponamorev＠gmail.com

There is motherboard based on the Intel Rangeley Atom C2000 (C2758) series processor. How to enable the SMBus0 in coreboot? If I use OEM BIOS or BIOS from Intel (EDVLCRB1.86B.0048.R00.1508181657_MPK) for mohon peak crb, then I see on the SMBus0 (i2c-1 in Fedora 28) memory DIMM spd (0x50 & 0x52), clock generator (0x69) and other devices. If I use a coreboot based bios for the Mohon peak platform - I do not see any devices on i2c-1. I see an data exchange on the SMBus0 with oscilloscope at boot time only. When I send "i2cdetect -y 1" command in Linux no activity on SMBus0 and no device found.

2 weeks, 1 day

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"remote: You need 'Create' rights to create new reference" when pushing to Gerrit

by Peter Lemenkov

Hello All, It seems that after the switch to a new UI some bits were missed in transition. Sulaco ~/work/coreboot (git::lenovo_z61t_no_ctrl_swap): git review remote: error: branch refs/publish/master/lenovo_z61t_no_ctrl_swap: remote: You need 'Create' rights to create new references. remote: User: lemenkov remote: Contact an administrator to fix the permissions remote: remote: Processing changes: refs: 1 remote: Processing changes: refs: 1, done To ssh://review.coreboot.org:29418/coreboot ! [remote rejected] HEAD -> refs/publish/master/lenovo_z61t_no_ctrl_swap (prohibited by Gerrit: not permitted: create) error: failed to push some refs to 'ssh://lemenkov@review.coreboot.org:29418/coreboot' Sulaco ~/work/coreboot (git::lenovo_z61t_no_ctrl_swap): I didn't change anything - so I guess the issue is on the Gerrit's side. -- With best regards, Peter Lemenkov.

2 weeks, 2 days

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IME: Alternatives for large companies?

by Philipp Stanner

Recently I had an interesting discussion with a system administrator who is responsible for several hundred PCs, Routers etc. His argument was: Imagine it would take you 15 minutes to install a patch on a computer (all windows machines of course...). If your company has 1000 computers and you send one admin to install the patches, it will take him >31 work days, working 8h a day. That's why, he said, companies are interested in software allowing them to install stuff on the OS / hard drive remotely through the firmware I, not dealing with large networks, had never thought about it this way. But it does make a lot of sense to me, it's about real money (as usual). So I guess that's indeed a huge reason why Intel and AMD created Frankenstein, running below UEFI and Kernel. It probably doesn't explain so much why it's necessary to disallow you switching IME off or why it needs control about absolutely everything, but that's a different story. So I'm wondering: What would you do about this reality? Could there be a different solution other than software in Ring -1 having its sausage fingers on everything? Sure, the programmers in a company could install their stuff on their own, but the office folks, the HR and PR guys and the lawyers? Hmm. And whether we like it or not, even awesome companies almost exclusively supply their employees with windows machines and they just demand solutions allowing their IT-departements to fix everything as cheap and as easy as possible P.

3 weeks, 1 day

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Starting the coreboot 4.10 release process

by Patrick Georgi

Hi everybody, with this mail I'm officially starting the 4.10 release process. As per the first step of our checklist (Documentation/releases/checklist.md), I hereby announce the intent to release coreboot 4.10 in about 2 weeks. I'm aiming for May 28th to avoid releasing into the weekend or on Memorial Day in the US, but I'll likely lock down the commit we'll designate 4.10 during those days to give some room for testing. I created a copy of the checklist on https://piratenpad.de/p/coreboot4.10-release-checklist, also including the current state of the 4.10 release notes. Please test the boards you have around and provide fixes, please be careful with intrusive changes (and maybe postpone them until after the release) and please update the release notes (Documentation/releases/ coreboot-4.10-relnotes.md or near the bottom of the etherpad doc, I'll carry them over into our git repo then). As promised with the 4.9 release there won't be deprecations after 4.10. However we need to finalize our set of deprecations we want to announce with 4.10 that will happen after the 4.11 release (those also belong in the release notes). Regards, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

3 weeks, 2 days

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New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 25 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1401717: Null pointer dereferences (FORWARD_NULL) ________________________________________________________________________________________________________ *** CID 1401717: Null pointer dereferences (FORWARD_NULL) /src/drivers/intel/fsp1_1/car.c: 175 in mainboard_romstage_entry() 169 } else { 170 /* This leaks a mapping which this code assumes is benign as 171 * the flash is memory mapped CPU's address space. */ 172 fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); 173 } 174 >>> CID 1401717: Null pointer dereferences (FORWARD_NULL) >>> Passing null pointer "fih" to "cache_as_ram_stage_main", which dereferences it. 175 cache_as_ram_stage_main(fih); 176 } 177 178 void __weak car_mainboard_pre_console_init(void) 179 { 180 } ** CID 1401394: Null pointer dereferences (NULL_RETURNS) /src/soc/intel/broadwell/romstage/raminit.c: 125 in raminit() ________________________________________________________________________________________________________ *** CID 1401394: Null pointer dereferences (NULL_RETURNS) /src/soc/intel/broadwell/romstage/raminit.c: 125 in raminit() 119 mrc_cache_stash_data(MRC_TRAINING_DATA, 0, 120 pei_data->data_to_save, 121 pei_data->data_to_save_size); 122 123 printk(BIOS_DEBUG, "create cbmem for dimm information\n"); 124 mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); >>> CID 1401394: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be null "mem_info" when calling "memset". [Note: The source code implementation of the function has been overridden by a builtin model.] 125 memset(mem_info, 0, sizeof(*mem_info)); 126 /* Translate pei_memory_info struct data into memory_info struct */ 127 mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; 128 for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) { 129 struct dimm_info *dimm = &mem_info->dimm[i]; 130 const struct pei_dimm_info *pei_dimm = ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0...

3 weeks, 5 days

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PSPTool – Display, extract, and manipulate PSP firmware

by Christian Werling

Hi everyone, over the past year I did some research on AMD’s controversial Secure Processor (formerly known as Platform Security Processor or PSP). Its firmware is stored in an undocumented area of UEFI images and so I wrote a tool that can parse it. I thought some of you might be interested in that: https://github.com/cwerling/psptool <https://github.com/cwerling/psptool> It is accompanied by PSPTrace, which can correlate an SPI capture of a boot procedure to the AMD firmware entries so you can deduct some boot logic from it. Cheers, Christian

3 weeks, 5 days

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nvramtool and CONFIG_HAVE_OPTION_TABLE (or CONFIG_USE_OPTION_TABLE)

by kevin＠trippers.org

A coworker noticed that nvramtool (and the nvramtool man page) both refer to the option CONFIG_HAVE_OPTION_TABLE as the option set to include cmos.layout into the coreboot tables. nofound_msg_cmos_opt_table[] = "%s: Item %s not found in coreboot table. Apparently, the " "coreboot installed on this system was built without specifying " "CONFIG_HAVE_OPTION_TABLE.\n"; However, CONFIG_HAVE_OPTION_TABLE is set by the board to indicate whether the board is cmos.layout capable. The actual option is CONFIG_USE_OPTION_TABLE, which depends upon CONFIG_HAVE_OPTION_TABLE. The code in src/lib/coreboot_table.c only adds the lb record to the coreboot tables if CONFIG_USE_OPTION_TABLE is set. The other choice is to make src/lib/coreboot_table.c add the lb record if the board has a cmos.layout (CONFIG_HAVE_OPTION_TABLE) but then userland will have access to a layout that is ignored. I suppose this is what happens if you set CONFIG_STATIC_OPTION_TABLE. This doesn't seem like the right answer to me. I think this is only cosmetic, but should I submit a patch to change this so that others are not also sidetracked? Thanks, Kevin

3 weeks, 5 days

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coreboot May 2019