coreboot May 2019

coreboot@coreboot.org

49 participants
56 discussions

PSPTool – Display, extract, and manipulate PSP firmware
by Christian Werling 31 May '19

31 May '19

Hi everyone, over the past year I did some research on AMD’s controversial Secure Processor (formerly known as Platform Security Processor or PSP). Its firmware is stored in an undocumented area of UEFI images and so I wrote a tool that can parse it. I thought some of you might be interested in that: https://github.com/cwerling/psptool <https://github.com/cwerling/psptool> It is accompanied by PSPTrace, which can correlate an SPI capture of a boot procedure to the AMD firmware entries so you can deduct some boot logic from it. Cheers, Christian

3 2

nvramtool and CONFIG_HAVE_OPTION_TABLE (or CONFIG_USE_OPTION_TABLE)
by kevin＠trippers.org 31 May '19

31 May '19

A coworker noticed that nvramtool (and the nvramtool man page) both refer to the option CONFIG_HAVE_OPTION_TABLE as the option set to include cmos.layout into the coreboot tables. nofound_msg_cmos_opt_table[] = "%s: Item %s not found in coreboot table. Apparently, the " "coreboot installed on this system was built without specifying " "CONFIG_HAVE_OPTION_TABLE.\n"; However, CONFIG_HAVE_OPTION_TABLE is set by the board to indicate whether the board is cmos.layout capable. The actual option is CONFIG_USE_OPTION_TABLE, which depends upon CONFIG_HAVE_OPTION_TABLE. The code in src/lib/coreboot_table.c only adds the lb record to the coreboot tables if CONFIG_USE_OPTION_TABLE is set. The other choice is to make src/lib/coreboot_table.c add the lb record if the board has a cmos.layout (CONFIG_HAVE_OPTION_TABLE) but then userland will have access to a layout that is ignored. I suppose this is what happens if you set CONFIG_STATIC_OPTION_TABLE. This doesn't seem like the right answer to me. I think this is only cosmetic, but should I submit a patch to change this so that others are not also sidetracked? Thanks, Kevin

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 29 May '19

29 May '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1399151: Integer handling issues (DIVIDE_BY_ZERO) ________________________________________________________________________________________________________ *** CID 1399151: Integer handling issues (DIVIDE_BY_ZERO) /src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c: 145 in init_octeon_dram_interface() 139 140 restart_lmc_init: 141 142 /* Poke the watchdog timer so it doesn't expire during DRAM init */ 143 bdk_watchdog_poke(); 144 >>> CID 1399151: Integer handling issues (DIVIDE_BY_ZERO) >>> In function call "init_octeon3_ddr3_interface", division by expression "ddr_hertz" which may be zero has undefined behavior. 145 mem_size_mbytes = init_octeon3_ddr3_interface(node, 146 ddr_configuration, 147 ddr_hertz, 148 cpu_hertz, 149 ddr_ref_hertz, 150 board_type, ** CID 1395725: Control flow issues (DEADCODE) /src/mainboard/intel/coffeelake_rvp/romstage.c: 23 in mainboard_memory_init_params() ________________________________________________________________________________________________________ *** CID 1395725: Control flow issues (DEADCODE) /src/mainboard/intel/coffeelake_rvp/romstage.c: 23 in mainboard_memory_init_params() 17 #include <baseboard/variants.h> 18 #include <soc/cnl_memcfg_init.h> 19 #include <soc/romstage.h> 20 21 void mainboard_memory_init_params(FSPM_UPD *memupd) 22 { >>> CID 1395725: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "spd.spd_smbus_address[spd@d...". 23 const struct spd_info spd = { 24 .spd_smbus_address[0] = 0xA0, 25 .spd_smbus_address[1] = 0xA2, 26 .spd_smbus_address[2] = 0xA4, 27 .spd_smbus_address[3] = 0xA6, 28 }; 29 30 cannonlake_memcfg_init(&memupd->FspmConfig, 31 variant_memcfg_config(), &spd); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Weird GPIO output when using inteltool, not sure what to make of it.
by justidl3＠uci.edu 28 May '19

28 May '19

Hi, I've been having a problem reading GPIO pins properly. As of now, I added CM238 to gpio.c and gpio_groups.c to get a reading on the gpio pins so I can add them to my own GPIO.h for my coreboot port. My current machine is weird. It uses a kaby lake cpu (7820hq) but a sky lake south bridge/PCH (CM238). I'm getting weird gpio readings, that are 16 bytes long, and i'm not sure if these are the correct right outputs. Further more, I want to use _PAD_CFG_STRUCT() so I can dump the raw values, but i'm not sure what the second and third arguments represent. I would like to get the correct GPIO output and place them in the arguments of the function _PAD_CFG_STRUCT() properly, but I'm not sure how. Any help is appreciated. Here is my dump: CPU: ID 0x906e9, Processor Type 0x0, Family 0x6, Model 0x9e, Stepping 0x9 Northbridge: 8086:5910 (unknown) Southbridge: 8086:a154 (CM238) IGD: 8086:591b (Intel(R) UHD Graphics 630) Trying to reveal Primary to Sideband Bridge (P2SB), let's hope the OS doesn't mind... done. SBREG_BAR = 0xfd000000 (MEM) Hiding Primary to Sideband Bridge (P2SB). ============= GPIOS ============= ------- GPIO Community 0 ------- PCR Port ID: 0xaf0000 ------- GPIO group GPP_A ------- 0x0400: 0x0000301844000502 GPP_A0 RCIN# 0x0408: 0x0000001944000402 GPP_A1 LAD0 0x0410: 0x0000001a44000402 GPP_A2 LAD1 0x0418: 0x0000001b44000402 GPP_A3 LAD2 0x0420: 0x0000001c44000402 GPP_A4 LAD3 0x0428: 0x0000001d44000600 GPP_A5 LFRAME# 0x0430: 0x0000241e44000400 GPP_A6 SERIRQ 0x0438: 0x0000001f44000900 GPP_A7 n/a 0x0440: 0x0000002044000500 GPP_A8 CLKRUN# 0x0448: 0x0000002144000600 GPP_A9 CLKOUT_LPC0 0x0450: 0x0000002244000600 GPP_A10 CLKOUT_LPC1 0x0458: 0x0000002344100102 GPP_A11 GPIO 0x0460: 0x0000002444000102 GPP_A12 GPIO 0x0468: 0x0000002544000600 GPP_A13 SUSWARN#/SUSPWRDNACK 0x0470: 0x0000302644000600 GPP_A14 SUS_STAT# 0x0478: 0x0000002744000502 GPP_A15 SUS_ACK# 0x0480: 0x0000002844000201 GPP_A16 GPIO 0x0488: 0x0000002944000201 GPP_A17 GPIO 0x0490: 0x0000002a44000402 GPP_A18 ISH_GP0 0x0498: 0x0000002b44000402 GPP_A19 ISH_GP1 0x04a0: 0x0000002c44000402 GPP_A20 ISH_GP2 0x04a8: 0x0000002d44000502 GPP_A21 ISH_GP3 0x04b0: 0x0000002e44000201 GPP_A22 GPIO 0x04b8: 0x0000002f44100102 GPP_A23 GPIO ------- GPIO Group GPP_B ------- 0x04c0: 0x0000003044000103 GPP_B0 GPIO 0x04c8: 0x0000003144000201 GPP_B1 GPIO 0x04d0: 0x0000003244000300 GPP_B2 GPIO 0x04d8: 0x0000003344000201 GPP_B3 GPIO 0x04e0: 0x0000003444000502 GPP_B4 CPU_GP3 0x04e8: 0x0000003504000102 GPP_B5 GPIO 0x04f0: 0x0000003644000700 GPP_B6 SRCCLKREQ1# 0x04f8: 0x0000003744000702 GPP_B7 SRCCLKREQ2# 0x0500: 0x0000003844000702 GPP_B8 SRCCLKREQ3# 0x0508: 0x0000003944000702 GPP_B9 SRCCLKREQ4# 0x0510: 0x0000003a44000700 GPP_B10 SRCCLKREQ5# 0x0518: 0x0000003b44000601 GPP_B11 EXT_PWR_GATE# 0x0520: 0x0000003c44000601 GPP_B12 SLP_S0# 0x0528: 0x0000003d44000601 GPP_B13 PLTRST# 0x0530: 0x0000003e42840101 GPP_B14 GPIO 0x0538: 0x0000003f44000300 GPP_B15 GPIO 0x0540: 0x0000004084800102 GPP_B16 GPIO 0x0548: 0x0000004144000201 GPP_B17 GPIO 0x0550: 0x0000004244000200 GPP_B18 GPIO 0x0558: 0x0000004344000200 GPP_B19 GPIO 0x0560: 0x0000004444000600 GPP_B20 GSPI1_CLK 0x0568: 0x0000004544000502 GPP_B21 GSPI1_MISO 0x0570: 0x0000004644000600 GPP_B22 GSPI1_MOSI 0x0578: 0x0000004744000201 GPP_B23 GPIO ------- GPIO Community 1 ------- PCR Port ID: 0xae0000 ------- GPIO Group GPP_C ------- 0x0400: 0x0000004844000602 GPP_C0 SMBCLK 0x0408: 0x0000004944000402 GPP_C1 SMBDATA 0x0410: 0x0000104a44000502 GPP_C2 SMBALERT# 0x0418: 0x0000304b44000602 GPP_C3 SML0CLK 0x0420: 0x0000304c44000402 GPP_C4 SML0DATA 0x0428: 0x0000004d44000200 GPP_C5 GPIO 0x0430: 0xffffffffffffffff GPP_C6 RESERVED 0x0438: 0xffffffffffffffff GPP_C7 RESERVED 0x0440: 0x0000005044000502 GPP_C8 UART0_RXD 0x0448: 0x0000005144000600 GPP_C9 UART0_TXD 0x0450: 0x0000005244000600 GPP_C10 UART0_RTS# 0x0458: 0x0000005344000502 GPP_C11 UART0_CTS# 0x0460: 0x0000005444000502 GPP_C12 UART1_RXD 0x0468: 0x0000005544000600 GPP_C13 UART1_TXD 0x0470: 0x0000005644000600 GPP_C14 UART1_RTS# 0x0478: 0x0000005744000502 GPP_C15 UART1_CTS# 0x0480: 0x0000305844000402 GPP_C16 I2C0_SDA 0x0488: 0x0000305944000602 GPP_C17 I2C0_SCL 0x0490: 0x0000305a44000402 GPP_C18 I2C1_SDA 0x0498: 0x0000305b44000602 GPP_C19 I2C1_SCL 0x04a0: 0x0000005c44000502 GPP_C20 UART2_RXD 0x04a8: 0x0000005d44000600 GPP_C21 UART2_TXD 0x04b0: 0x0000005e44000600 GPP_C22 UART2_RTS# 0x04b8: 0x0000005f44000502 GPP_C23 UART2_CTS# ------- GPIO Group GPP_D ------- 0x04c0: 0x0000006044000600 GPP_D0 SPI1_CS# 0x04c8: 0x0000006144000600 GPP_D1 SPI1_CLK 0x04d0: 0x0000006244000500 GPP_D2 SPI1_MISO 0x04d8: 0x0000006344000600 GPP_D3 SPI1_MOSI 0x04e0: 0x0000306444000402 GPP_D4 FLASHTRIG 0x04e8: 0x0000006544000602 GPP_D5 ISH_I2C0_SDA 0x04f0: 0x0000006644000600 GPP_D6 ISH_I2C0_SCL 0x04f8: 0x0000006744000502 GPP_D7 ISH_I2C1_SDA 0x0500: 0x0000006844000602 GPP_D8 ISH_I2C1_SCL 0x0508: 0x0000006944000300 GPP_D9 GPIO 0x0510: 0x0000006a44000201 GPP_D10 GPIO 0x0518: 0x0000006b44000300 GPP_D11 GPIO 0x0520: 0x0000006c44000300 GPP_D12 GPIO 0x0528: 0x0200006d44000502 GPP_D13 ISH_UART0_RXD 0x0530: 0x0200006e44000600 GPP_D14 ISH_UART0_TXD 0x0538: 0x0000006f44000600 GPP_D15 ISH_UART0_RTS# 0x0540: 0x0200007044000502 GPP_D16 ISH_UART0_CTS# 0x0548: 0x0000007144000600 GPP_D17 DMIC_CLK1 0x0550: 0x0000107244000400 GPP_D18 DMIC_DATA1 0x0558: 0x0000007344000600 GPP_D19 DMIC_CLK0 0x0560: 0x0000107444000400 GPP_D20 DMIC_DATA0 0x0568: 0x0000007544000400 GPP_D21 SPI1_IO2 0x0570: 0x0000007644000400 GPP_D22 SPI1_IO3 0x0578: 0x0000307744000602 GPP_D23 I2S_MCLK ------- GPIO Group GPP_E ------- 0x0580: 0x0000001844000502 GPP_E0 SATAXPCIE0 0x0588: 0x0000001944000f00 GPP_E1 n/a 0x0590: 0x0000001a44000f00 GPP_E2 n/a 0x0598: 0x0000001b44000500 GPP_E3 CPU_GP0 0x05a0: 0x0000001c04000600 GPP_E4 SATA_DEVSLP0 0x05a8: 0x0000001d44000300 GPP_E5 GPIO 0x05b0: 0x0000001e80880102 GPP_E6 GPIO 0x05b8: 0x0000001f44000300 GPP_E7 GPIO 0x05c0: 0x0000002044000600 GPP_E8 SATALED# 0x05c8: 0x0000302144000503 GPP_E9 USB2_OC0# 0x05d0: 0x0000302244000503 GPP_E10 USB2_OC1# 0x05d8: 0x0000302344000503 GPP_E11 USB2_OC2# 0x05e0: 0x0000302444000503 GPP_E12 USB2_OC3# 0x05e8: 0x0000002544000502 GPP_E13 DDPB_HPD0 0x05f0: 0x0000002644000502 GPP_E14 DDPC_HPD1 0x05f8: 0x0000002744000200 GPP_E15 GPIO 0x0600: 0x0000002844000201 GPP_E16 GPIO 0x0608: 0x0000002944000200 GPP_E17 GPIO 0x0610: 0x0000002a44100102 GPP_E18 GPIO 0x0618: 0x0000002b04000600 GPP_E19 DDPB_CTRLDATA 0x0620: 0x0000002c44000200 GPP_E20 GPIO 0x0628: 0x0000002d44000102 GPP_E21 GPIO 0x0630: 0x0000002e84000102 GPP_E22 GPIO 0x0638: 0x0000002f44000300 GPP_E23 GPIO ------- GPIO Community 2 ------- PCR Port ID: 0xad0000 -------- GPIO Group GPD -------- 0x0400: 0x0000001844000502 GPD0 BATLOW# 0x0408: 0x0000001944000502 GPD1 ACPRESENT 0x0410: 0x00003c1a04000602 GPD2 LAN_WAKE# 0x0418: 0x0000001b44000502 GPD3 PWRBTN# 0x0420: 0x0000001c44000600 GPD4 SLP_S3# 0x0428: 0x0000001d44000600 GPD5 SLP_S4# 0x0430: 0x0000001e44000600 GPD6 SLP_A# 0x0438: 0x0000001f44000201 GPD7 GPIO 0x0440: 0x0000002044000600 GPD8 SUSCLK 0x0448: 0x0000002144000600 GPD9 SLP_WLAN# 0x0450: 0x0000002244000600 GPD10 SLP_S5# 0x0458: 0x0000002344000600 GPD11 LANPHYPC ------- GPIO Community 3 ------- PCR Port ID: 0xac0000 ------- GPIO Group GPP_F ------- 0x0400: 0x0000006d44000500 GPP_F0 I2S2_SCLK 0x0408: 0x0000006e44000500 GPP_F1 I2S2_SFRM 0x0410: 0x0000106f44000500 GPP_F2 I2S2_TXD 0x0418: 0x0000107044000500 GPP_F3 I2S2_RXD 0x0420: 0x0000007144000502 GPP_F4 I2C2_SDA 0x0428: 0x0000007244000602 GPP_F5 I2C2_SCL 0x0430: 0x0000007344000402 GPP_F6 I2C3_SDA 0x0438: 0x0000007444000600 GPP_F7 I2C3_SCL 0x0440: 0x0000007544000400 GPP_F8 I2C4_SDA 0x0448: 0x0000007644000600 GPP_F9 I2C4_SCL 0x0450: 0x0000007744000400 GPP_F10 I2C5_SDA 0x0458: 0x0000000000000000 GPP_F11 GPIO 0x0460: 0x0000000000000000 GPP_F12 GPIO 0x0468: 0x0000000000000000 GPP_F13 GPIO 0x0470: 0x0000000000000000 GPP_F14 GPIO 0x0478: 0x0000000000000000 GPP_F15 GPIO 0x0480: 0x0000000000000000 GPP_F16 GPIO 0x0488: 0x0000000000000000 GPP_F17 GPIO 0x0490: 0x0000000000000000 GPP_F18 GPIO 0x0498: 0x0000000000000000 GPP_F19 GPIO 0x04a0: 0x0000000000000000 GPP_F20 GPIO 0x04a8: 0x0000000000000000 GPP_F21 GPIO 0x04b0: 0x0000000000000000 GPP_F22 GPIO 0x04b8: 0x0000000000000000 GPP_F23 GPIO ------- GPIO Group GPP_G ------- 0x04c0: 0x0000000000000000 GPP_G0 GPIO 0x04c8: 0x0000000000000000 GPP_G1 GPIO 0x04d0: 0x0000000000000000 GPP_G2 GPIO 0x04d8: 0x0000000000000000 GPP_G3 GPIO 0x04e0: 0x0000000000000000 GPP_G4 GPIO 0x04e8: 0x0000000000000000 GPP_G5 GPIO 0x04f0: 0x0000000000000000 GPP_G6 GPIO 0x04f8: 0x0000000000000000 GPP_G7 GPIO

1 0

Status of Board Asus KGPE-d16
by Kinky Nekoboi 27 May '19

27 May '19

Hello fellow corebooters, i have succesfully build an rom for the asus kgpe-d16, with microcode (FAM15h) enabled. Does anybody has experience with this systemboard. Is the current included ucode working with Opteron 63XX processors? best regards

2 3

Re: inteltool does not properly dump gpio values for south bridge CM238 chipset
by justidl3＠uci.edu 25 May '19

25 May '19

Thanks for the help, I was able to run -g -G and I got this output, its the same when you do -g ============= GPIOS ============= ------- GPIO Community 0 ------- PCR Port ID: 0xaf0000 ------- GPIO Group GPP_A ------- 0x0400: 0x0000301844000502 GPP_A0 RCIN# 0x0408: 0x0000001944000402 GPP_A1 LAD0 0x0410: 0x0000001a44000402 GPP_A2 LAD1 0x0418: 0x0000001b44000402 GPP_A3 LAD2 0x0420: 0x0000001c44000402 GPP_A4 LAD3 0x0428: 0x0000001d44000600 GPP_A5 LFRAME# 0x0430: 0x0000241e44000400 GPP_A6 SERIRQ 0x0438: 0x0000001f44000900 GPP_A7 n/a 0x0440: 0x0000002044000500 GPP_A8 CLKRUN# 0x0448: 0x0000002144000600 GPP_A9 CLKOUT_LPC0 0x0450: 0x0000002244000600 GPP_A10 CLKOUT_LPC1 0x0458: 0x0000002344100102 GPP_A11 GPIO 0x0460: 0x0000002444000102 GPP_A12 GPIO 0x0468: 0x0000002544000600 GPP_A13 SUSWARN#/SUSPWRDNACK 0x0470: 0x0000302644000600 GPP_A14 SUS_STAT# 0x0478: 0x0000002744000502 GPP_A15 SUS_ACK# 0x0480: 0x0000002844000201 GPP_A16 GPIO 0x0488: 0x0000002944000201 GPP_A17 GPIO 0x0490: 0x0000002a44000402 GPP_A18 ISH_GP0 0x0498: 0x0000002b44000402 GPP_A19 ISH_GP1 0x04a0: 0x0000002c44000402 GPP_A20 ISH_GP2 0x04a8: 0x0000002d44000502 GPP_A21 ISH_GP3 0x04b0: 0x0000002e44000201 GPP_A22 GPIO 0x04b8: 0x0000002f44100102 GPP_A23 GPIO ------- GPIO Group GPP_B ------- 0x04c0: 0x0000003044000101 GPP_B0 GPIO 0x04c8: 0x0000003144000201 GPP_B1 GPIO 0x04d0: 0x0000003244000300 GPP_B2 GPIO 0x04d8: 0x0000003344000201 GPP_B3 GPIO 0x04e0: 0x0000003444000502 GPP_B4 CPU_GP3 0x04e8: 0x0000003504000102 GPP_B5 GPIO 0x04f0: 0x0000003644000700 GPP_B6 SRCCLKREQ1# 0x04f8: 0x0000003744000700 GPP_B7 SRCCLKREQ2# 0x0500: 0x0000003844000702 GPP_B8 SRCCLKREQ3# 0x0508: 0x0000003944000702 GPP_B9 SRCCLKREQ4# 0x0510: 0x0000003a44000700 GPP_B10 SRCCLKREQ5# 0x0518: 0x0000003b44000601 GPP_B11 n/a 0x0520: 0x0000003c44000601 GPP_B12 SLP_S0# 0x0528: 0x0000003d44000601 GPP_B13 PLTRST# 0x0530: 0x0000003e42840101 GPP_B14 GPIO 0x0538: 0x0000003f44000300 GPP_B15 GPIO 0x0540: 0x0000004084800102 GPP_B16 GPIO 0x0548: 0x0000004144000201 GPP_B17 GPIO 0x0550: 0x0000004244000200 GPP_B18 GPIO 0x0558: 0x0000004344000200 GPP_B19 GPIO 0x0560: 0x0000004444000600 GPP_B20 GSPI1_CLK 0x0568: 0x0000004544000502 GPP_B21 GSPI1_MISO 0x0570: 0x0000004644000600 GPP_B22 GSPIO_MOSI 0x0578: 0x0000004744000201 GPP_B23 GPIO ------- GPIO Community 1 ------- PCR Port ID: 0xae0000 ------- GPIO Group GPP_C ------- 0x0400: 0x0000004844000602 GPP_C0 SMBCLK 0x0408: 0x0000004944000402 GPP_C1 SMBDATA 0x0410: 0x0000104a44000502 GPP_C2 SMBALERT# 0x0418: 0x0000304b44000602 GPP_C3 SML0CLK 0x0420: 0x0000304c44000402 GPP_C4 SML0DATA 0x0428: 0x0000004d44000200 GPP_C5 GPIO 0x0430: 0xffffffffffffffff GPP_C6 RESERVED 0x0438: 0xffffffffffffffff GPP_C7 RESERVED 0x0440: 0x0000005044000502 GPP_C8 UART0_RXD 0x0448: 0x0000005144000600 GPP_C9 UART0_TXD 0x0450: 0x0000005244000600 GPP_C10 UART0_RTS# 0x0458: 0x0000005344000502 GPP_C11 UART0_CTS# 0x0460: 0x0000005444000502 GPP_C12 UART1_RXD 0x0468: 0x0000005544000600 GPP_C13 UART1_TXD 0x0470: 0x0000005644000600 GPP_C14 UART1_RTS# 0x0478: 0x0000005744000502 GPP_C15 UART1_CTS# 0x0480: 0x0000305844000402 GPP_C16 I2C0_SDA 0x0488: 0x0000305944000602 GPP_C17 I2C0_SCL 0x0490: 0x0000305a44000402 GPP_C18 I2C1_SDA 0x0498: 0x0000305b44000602 GPP_C19 I2C1_SCL 0x04a0: 0x0000005c44000502 GPP_C20 UART2_RXD 0x04a8: 0x0000005d44000600 GPP_C21 UART2_TXD 0x04b0: 0x0000005e44000600 GPP_C22 UART2_RTS# 0x04b8: 0x0000005f44000502 GPP_C23 UART2_CTS# ------- GPIO Group GPP_D ------- 0x04c0: 0x0000006044000600 GPP_D0 n/a 0x04c8: 0x0000006144000600 GPP_D1 n/a 0x04d0: 0x0000006244000500 GPP_D2 n/a 0x04d8: 0x0000006344000600 GPP_D3 n/a 0x04e0: 0x0000306444000402 GPP_D4 ISH_I2C2_SDA 0x04e8: 0x0000006544000602 GPP_D5 I2S_SFRM 0x04f0: 0x0000006644000600 GPP_D6 I2S_TXD 0x04f8: 0x0000006744000502 GPP_D7 I2S_RXD 0x0500: 0x0000006844000602 GPP_D8 I2S_SCLK 0x0508: 0x0000006944000300 GPP_D9 GPIO 0x0510: 0x0000006a44000201 GPP_D10 GPIO 0x0518: 0x0000006b44000300 GPP_D11 GPIO 0x0520: 0x0000006c44000300 GPP_D12 GPIO 0x0528: 0x0200006d44000502 GPP_D13 ISH_UART0_RXD 0x0530: 0x0200006e44000600 GPP_D14 ISH_UART0_TXD 0x0538: 0x0000006f44000600 GPP_D15 ISH_UART0_RTS# 0x0540: 0x0200007044000502 GPP_D16 ISH_UART0_CTS# 0x0548: 0x0000007144000600 GPP_D17 DMIC_CLK1 0x0550: 0x0000107244000400 GPP_D18 DMIC_DATA1 0x0558: 0x0000007344000600 GPP_D19 DMIC_CLK0 0x0560: 0x0000107444000400 GPP_D20 DMIC_DATA0 0x0568: 0x0000007544000400 GPP_D21 n/a 0x0570: 0x0000007644000400 GPP_D22 n/a 0x0578: 0x0000307744000602 GPP_D23 ISH_I2C2_SCL ------- GPIO Group GPP_E ------- 0x0580: 0x0000001844000502 GPP_E0 SATAXPCIE0 0x0588: 0x0000001944000f00 GPP_E1 n/a 0x0590: 0x0000001a44000f00 GPP_E2 n/a 0x0598: 0x0000001b44000502 GPP_E3 CPU_GP0 0x05a0: 0x0000001c04000600 GPP_E4 SATA_DEVSLP0 0x05a8: 0x0000001d44000300 GPP_E5 GPIO 0x05b0: 0x0000001e80880102 GPP_E6 GPIO 0x05b8: 0x0000001f44000300 GPP_E7 GPIO 0x05c0: 0x0000002044000600 GPP_E8 SATA_LED# 0x05c8: 0x0000302144000503 GPP_E9 USB_OC0# 0x05d0: 0x0000302244000503 GPP_E10 USB_OC1# 0x05d8: 0x0000302344000503 GPP_E11 USB_OC2# 0x05e0: 0x0000302444000503 GPP_E12 USB_OC3# ------- GPIO Group GPP_F ------- 0x05e8: 0x0000002544000502 GPP_F0 SATAXPCIE3 0x05f0: 0x0000002644000502 GPP_F1 SATAXPCIE4 0x05f8: 0x0000002744000200 GPP_F2 GPIO 0x0600: 0x0000002844000201 GPP_F3 GPIO 0x0608: 0x0000002944000200 GPP_F4 GPIO 0x0610: 0x0000002a44100102 GPP_F5 GPIO 0x0618: 0x0000002b04000600 GPP_F6 SATA_DEVSLP4 0x0620: 0x0000002c44000200 GPP_F7 GPIO 0x0628: 0x0000002d44000102 GPP_F8 GPIO 0x0630: 0x0000002e84000102 GPP_F9 GPIO 0x0638: 0x0000002f44000300 GPP_F10 GPIO 0x0640: 0x0000003044000102 GPP_F11 GPIO 0x0648: 0x0000003184800102 GPP_F12 GPIO 0x0650: 0x0000003244000102 GPP_F13 GPIO 0x0658: 0x0000003344000102 GPP_F14 GPIO 0x0660: 0x0000303444000502 GPP_F15 USB_OC4# 0x0668: 0x0000303544000502 GPP_F16 USB_OC5# 0x0670: 0x0000003644000201 GPP_F17 GPIO 0x0678: 0x0000003744000201 GPP_F18 GPIO 0x0680: 0x0000003844000600 GPP_F19 eDP_VDDEN 0x0688: 0x0000003944000600 GPP_F20 eDP_BKLTEN 0x0690: 0x0000003a44000600 GPP_F21 eDP_BKLTCTL 0x0698: 0x0000003b84000201 GPP_F22 GPIO 0x06a0: 0x0000003c44000300 GPP_F23 GPIO ------- GPIO Group GPP_G ------- 0x06a8: 0x0000103d44800100 GPP_G0 GPIO 0x06b0: 0x0000003e44000201 GPP_G1 GPIO 0x06b8: 0x0000003f44000702 GPP_G2 FAN_TACH_2 0x06c0: 0x0000004080880100 GPP_G3 GPIO 0x06c8: 0x0000004144000200 GPP_G4 GPIO 0x06d0: 0x0000004244000200 GPP_G5 GPIO 0x06d8: 0x0000004344000201 GPP_G6 GPIO 0x06e0: 0x0000004444000102 GPP_G7 GPIO 0x06e8: 0x0000004544000201 GPP_G8 GPIO 0x06f0: 0x0000004644000201 GPP_G9 GPIO 0x06f8: 0x0000004744000200 GPP_G10 GPIO 0x0700: 0x0000004844000201 GPP_G11 GPIO 0x0708: 0x0000104984800100 GPP_G12 GPIO 0x0710: 0x0000004a44000201 GPP_G13 GPIO 0x0718: 0x0000004b44000300 GPP_G14 GPIO 0x0720: 0x0000004c44000201 GPP_G15 GPIO 0x0728: 0x0000104d84000200 GPP_G16 GPIO 0x0730: 0x0000004e44000201 GPP_G17 GPIO 0x0738: 0x0000004f84800102 GPP_G18 GPIO 0x0740: 0x0000005044000300 GPP_G19 GPIO 0x0748: 0x0000005144000201 GPP_G20 GPIO 0x0750: 0x0000105244000100 GPP_G21 GPIO 0x0758: 0x0000005384000201 GPP_G22 GPIO 0x0760: 0x0000005444000201 GPP_G23 GPIO ------- GPIO Group GPP_H ------- 0x0768: 0x0000005584000702 GPP_H0 SRCCLKREQ6# 0x0770: 0x0000005644000702 GPP_H1 SRCCLKREQ7# 0x0778: 0x0000005784000500 GPP_H2 SRCCLKREQ8# 0x0780: 0x0000005844000700 GPP_H3 SRCCLKREQ9# 0x0788: 0x0000005944000200 GPP_H4 GPIO 0x0790: 0x0000005a84000700 GPP_H5 SRCCLKREQ11# 0x0798: 0x0000005b44000201 GPP_H6 GPIO 0x07a0: 0x0000005c44000201 GPP_H7 GPIO 0x07a8: 0x0000005d44000201 GPP_H8 GPIO 0x07b0: 0x0000005e44000201 GPP_H9 GPIO 0x07b8: 0x0000005f44000201 GPP_H10 GPIO 0x07c0: 0x0000006044000201 GPP_H11 GPIO 0x07c8: 0x0000006144000200 GPP_H12 GPIO 0x07d0: 0x0000006244000102 GPP_H13 GPIO 0x07d8: 0x0000006344000102 GPP_H14 GPIO 0x07e0: 0x0000006444000102 GPP_H15 GPIO 0x07e8: 0x0000006544000201 GPP_H16 GPIO 0x07f0: 0x0000006644000201 GPP_H17 GPIO 0x07f8: 0x0000006744000201 GPP_H18 GPIO 0x0800: 0x0000306844000402 GPP_H19 ISH_I2C0_SDA 0x0808: 0x0000306944000602 GPP_H20 ISH_I2C0_SCL 0x0810: 0x0000306a44000402 GPP_H21 ISH_I2C1_SDA 0x0818: 0x0000306b44000602 GPP_H22 ISH_I2C1_SCL 0x0820: 0x0000006c44000200 GPP_H23 GPIO ------- GPIO Community 2 ------- PCR Port ID: 0xad0000 -------- GPIO Group GPD -------- 0x0400: 0x0000001844000502 GPD0 BATLOW# 0x0408: 0x0000001944000502 GPD1 ACPRESENT 0x0410: 0x00003c1a04000602 GPD2 LAN_WAKE# 0x0418: 0x0000001b44000502 GPD3 PWRBTN# 0x0420: 0x0000001c44000600 GPD4 SLP_S3# 0x0428: 0x0000001d44000600 GPD5 SLP_S4# 0x0430: 0x0000001e44000600 GPD6 SLP_A# 0x0438: 0x0000001f44000201 GPD7 GPIO 0x0440: 0x0000002044000600 GPD8 SUSCLK 0x0448: 0x0000002144000600 GPD9 SLP_WLAN# 0x0450: 0x0000002244000600 GPD10 SLP_S5# 0x0458: 0x0000002344000600 GPD11 LANPHYPC ------- GPIO Community 3 ------- PCR Port ID: 0xac0000 ------- GPIO Group GPP_I ------- 0x0400: 0x0000006d44000500 GPP_I0 DDPB_HPD0 0x0408: 0x0000006e44000500 GPP_I1 DDPC_HPD1 0x0410: 0x0000106f44000500 GPP_I2 DDPD_HPD2 0x0418: 0x0000107044000500 GPP_I3 DDPE_HPD3 0x0420: 0x0000007144000502 GPP_I4 EDP_HPD 0x0428: 0x0000007244000602 GPP_I5 DDPB_CTRLCLK 0x0430: 0x0000007344000402 GPP_I6 DDPB_CTRLDATA 0x0438: 0x0000007444000600 GPP_I7 DDPC_CTRLCLK 0x0440: 0x0000007544000400 GPP_I8 DDPC_CTRLDATA 0x0448: 0x0000007644000600 GPP_I9 DDPD_CTRLCLK 0x0450: 0x0000007744000400 GPP_I10 DDPD_CTRLDATA

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coreboot leadership meeting minutes for May 8 & May 22
by Martin Roth 24 May '19

24 May '19

coreboot leadership meeting notes are now public: https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK… Anyone interested in joining the leadership meetings in the future can check the calendar on the coreboot website for call-in information. ------------------------------------------------------------ 22 May 2019 Attendees: PatrickG, Werner, Jay Talbott, Martin, Matt DeVillier, Felix Held, Stefan, Kerry Brown, Ron, Philipp, Dhendricks Topics: * Results of polls (See https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/OWHS…) * Implement this after the 4.10 release. * Copyrights * Winner in poll: Create an authors file and remove all existing copyright lines * Discuss with SFC - need to figure out if there are any issues with removing copyright lines. * Characters per line * Winner in poll: 96 character lines. * Will reformat in conjunction with the clang-format * Update the contributor guidelines now, but the tree will lag behind for a while longer * Reformatting with clang-format * Winner in poll: Submitters should run clang-format before submitting a patch and it should be rejected in gerrit if it’s not formatted properly with an error telling them how to format it. * Will reformat the tree on a directory-by-directory basis and enforcement will start as directories are reformatted * Need to finalize clang-format options before we start * src/vendorcode will not be reformatted * Number of people voting varied by question 59/68/61 * coreboot contributor expectations * This will be a guideline for now - No significant penalties at this point. * Code should be maintained as long as a chip/platform is being sold? * Stefan feels that we shouldn’t have different guidelines for individuals and companies. * David feels like rejecting patches is going to stifle progress. * We will discuss this further on the mailing list. * If we make guidelines, the community will likely take these as rules and reject patches if they aren’t followed. * No decision made for now, review again next week. * Shall we add a CREDITS file a la Linux for people who contributed but are no longer active? * How is this different than the authors file? * Credits is for people who are no longer involved in the project. This is for people who authored code that is no longer in the master branch. * Can we make this part of the AUTHORS file? Or does it need to be its own thing? * Decision: Put the credits list in the Authors file. * Can we adopt on principle removing all cpp guards on protos? * Add cleanup task - remove guards specifically around prototypes? * Having the prototypes outside of guards turns a compile time error into a linker error. * We should be more strict about how we define our blocks’ APIs. We should make better definitions about what each block exports. Document these better, and maybe be more strict about what code consumes which function. * Keep header file guards * No decision made for now * Release - still plan releasing on May 28th. * Need to update release notes. Pad at https://piratenpad.de/p/coreboot4.10-release-checklist * Issue tracker: * Philipp: Can we replace redmine? * Stephan: Not with bugzilla. We've already tried bugzilla and trac. * Monorail? Only runs on app engine. * Some people are not sure how to address issues on current bugtracker as there’s no gerrit integration. * There is a Gerrit redmine plugin, which might help * Use github as our bugtracker? * This would probably encourage other github use like merge-requests, which we don’t want. * “its-redmine” (or other plug-in) for gerrit-redmine integration? https://github.com/cyrilix/its-redmine ------------------------------------------------------------ 8 May 2019 Attendees: PatrickG, Martin, Matt Devo, Felix Held, Stefan, Marc Jones, Philipp, PatrickR, David Hendricks Topics: * People are trying to subscribe to the coreboot security mailing list. Who should be on that list (and what criteria decide this)? * We don’t want this to be widely available to the public in case a significant security issue is announced. We want to make sure we can fix it before it’s announced to the public. * There’s currently nothing on the list, maybe because out code is great, and maybe because the list isn’t widely known. * Who should have access? * Currently Stefan & Patrick are the only 2 on the list * Martin: people who can merge code to coreboot? * Should we turn this into an alias instead of a mailing list? * AI:Patrick Add the security list to the website and announce on the mailing list. * Decision: Keep as a list so that there’s an archive * Decision: Keep the Stefan & Patrick as the only people on the list for now * Decision: Bring this up again once there is activity on security@ and we know better what to do. * Community votes * Decision: The poll will be set up to start on Tuesday (May 14), running until the next leadership meeting on May 22nd. * 4.10 process (pgeorgi hasn’t announced anything yet) * AI:Patrick will announce today * GSoC * 4 students have been accepted * All have arrived on the mailing list or IRC * Finding a leadership group replacement for Marc * David Hendricks is the only one who responded to the self nomination. * Werner supports David to replace Marc (as claimed by Martin) * Stefan supports David * Marc also supports David * Decision: David Hendricks is voted in to replace Marc * David: “Thank you” * AI: Martin will notify the SFC (Done) * Martin to push picasso documentation to coreboot * Writing now, Need to get permission from AMD before publishing. * OSF Hackathon (June, Bochum) * Lunch will be served there, dinner is Hunt-Your-Own-Food * OSFC * We have some sponsors, but are still getting more * Ron needs photos from people “looking younger than they look today” for his anniversary talk * FSP 1.0 migration * Intel doesn’t seem to want to invest any resources in an update * Who is the owner for these at Intel? Is there a contact at this point? * Dhendricks might be able to work to get these updated to FSP 2.0 * AI: Patrick will look into the reasons for the migration (mailing list etc) and potentially write up a doc * Issue tracker * Over 200 users have applied but haven’t been authorized (never logged in). * Set up automatic notifications on IRC & current mailing list (& Set up new Mailing list if the bugs become too noisy) * AI: Patrick will look for plugins to get this set up.

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Re: How to add NUVOTON NCT6776F support with serial port logic enabled ???
by Дмитрий Понаморев 24 May '19

24 May '19

The controversial decision but the console output is not connected directly to the processor but to the superio Nuvoton. I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC control register). This register includes LPC_CLKOUT1. As far as I understood, the nuvoton uses this signal. LPC Clock Enabling > The LPC clock signal, LPC_CLKOUT1, is enabled or disabled by the software > through the > 32-bit LPCC register at offset 84h in the configuration space at bus 0, > device 31 > (decimal), function 0. > The LPC clock signal, LPC_CLKOUT0, is always enabled. It also has an > enable/disable > bit in the 32-bit LPCC register at offset 84h, but the bit is read-only > and always set to > enable LPC_CLKOUT0. > I did not see any signals on the oscilloscope. I tried to enable it by adding a function to the coreboot-4.9/src/southbridge/intel/fsp_rangeley/lpc.c file: /* Tutn on LPC_CLK1 for nuvoton IBASE = 0x50 ILB_LPCC = 0x84 (LPC_CLCOUT[0:1]) */ static void soc_enable_lpc_clk1(struct device *dev) { u32 reg32 = 0; u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); reg32 = read32(ilb_base + ILB_LPCC); write32(ilb_base + ILB_LPCC, (reg32 | 0x3)); } Clock signals LPC_CLKOUT1 appeared, but it did not help. Super io does not appear in Linux. What else you need to configure in LPC controller and(or) in Nuvotone so that the device can be seen in Linux? What utility can I get it with? > You can also compare the register banks of PCI 0:1f.0. > сб, 18 мая 2019 г. в 14:36, Shreesh Chhabbi <schhabbi(a)ircona.com>: > Hi, > > Is the serial port where you are trying to capture logs, coming out of > Nuvoton controller or the Atom Processor? > If serial port is coming out of Nuvoton: > Usually the controller connected on LPC to the main processor is accessed > via IO ports. Controller needs to have code change to support this. If you > have Intel CRB's reference code for main processor and controller, you > could look for supported commands to EC. I have encountered post code print > on the seven segment displays via EC from main processor. But serial > console is always directly from main processor. > If serial port is coming out of main processor: > The UART controller is seen as a PCI device to the CPU. You need to > enumerate this and initialize and use it for dumping bytes onto serial > console (available in Intel CRB reference code usually). > > Thanks, > Shreesh Chhabbi > Sr. Software Engineer > Ircona (www.ircona.com) > > -----Original Message----- > From: dponamorev(a)gmail.com <dponamorev(a)gmail.com> > Sent: Friday 17 May 2019 16:02 > To: coreboot(a)coreboot.org > Subject: [coreboot] How to add NUVOTON NCT6776F support with serial port > logic enabled ??? > > There is a Lanner FW-7573 platform based on the Intel Rangeley Atom C2000 > series processor. > To work with the Serial port in this platform, the NUVOTON NCT6776F chip > is connected via the LPC bus to the processor. > I just can’t get Serial port working for debuging. I take as a basis intel > littleplains board. I tried to add NCT6776F support following the example > of other boards - without success. There is no output to the console, and > in Linux, the superiotool program does not see the NCT6776F. > > On the official version of the BIOS I loaded linux OS and took a dump. > (superiotool r => Found Nuvoton NCT6776F/D (C) (id=0xc333) at 0x4e) ) > > How to add NUVOTON NCT6776F support with serial port logic enabled ??? > > in devicetree.cb I add: > > device pci 1f.0 on # LPC bridge > chip superio/nuvoton/nct6776 > device pnp 4e.0 off end # > Floppy > device pnp 4e.1 off end # > Parallel port > device pnp 4e.2 on # > COM1 > io 0x60 = 0x3f8 > irq 0x70 = 4 > end > device pnp 4e.3 off end # > COM2, IR > device pnp 4e.5 off end # > Keyboard > device pnp 4e.6 off end # > CIR > device pnp 4e.7 off end # > GPIO6 > device pnp 4e.107 off end # > GPIO7 > device pnp 4e.207 off end # > GPIO8 > device pnp 4e.307 off end # > GPIO9 > device pnp 4e.8 off end # > WDT > device pnp 4e.108 off end # > GPIO0 > device pnp 4e.208 off end # > GPIOA > device pnp 4e.308 off end # > GPIOBASE > device pnp 4e.109 off end # > GPIO1 > device pnp 4e.209 off end # > GPIO2 > device pnp 4e.309 off end # > GPIO3 > device pnp 4e.409 off end # > GPIO4 > device pnp 4e.509 off end # > GPIO5 > device pnp 4e.609 off end # > GPIO6 > device pnp 4e.709 off end # > GPIO7 > device pnp 4e.a on end # > ACPI > device pnp 4e.b off end # > HWM, front pannel LED > device pnp 4e.d off end # > VID > device pnp 4e.e off end # > CIR WAKE-UP > device pnp 4e.f off end # > GPIO > device pnp 4e.14 off end # > SVID > device pnp 4e.16 off end # > Deep sleep > device pnp 4e.17 off end # > GPIOA > end > end # LPC bridge > > In superio.asl i add: > > #undef SUPERIO_DEV > #undef SUPERIO_PNP_BASE > > #define SUPERIO_DEV SIO0 > #define SUPERIO_PNP_BASE 0x4e > #define NCT6776_SHOW_PP > #define NCT6776_SHOW_SP1 > #define NCT6776_SHOW_KBC > #define NCT6776_SHOW_HWM > #define NCT6776_SHOW_GPIO > > #include <superio/nuvoton/nct6776/acpi/superio.asl> > > in romstage.c add function mainboard_config_superio: > > void mainboard_config_superio(void) > { > /* Enable UART */ > nuvoton_pnp_enter_conf_state(GLOBAL_DEV); > > /* Select SIO pin states. */ As in Dump........ > pnp_write_config(GLOBAL_DEV, 0x13, 0xff); > pnp_write_config(GLOBAL_DEV, 0x14, 0xff); > pnp_write_config(GLOBAL_DEV, 0x1b, 0x53); > pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); > pnp_write_config(GLOBAL_DEV, 0x24, 0x24); > pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); > pnp_write_config(GLOBAL_DEV, 0x2b, 0x03); > pnp_write_config(GLOBAL_DEV, 0x2a, 0x00); > pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); > > /* Power RAM in S3. */ > //pnp_set_logical_device(ACPI_DEV); > //pnp_write_config(ACPI_DEV, 0xe4, 0x10); > > pnp_set_logical_device(SERIAL_DEV); > > nuvoton_pnp_exit_conf_state(GLOBAL_DEV); > > nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org To unsubscribe send an > email to coreboot-leave(a)coreboot.org >

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Re: How to add NUVOTON NCT6776F support with serial port logic enabled ???
by Ranga Rao 24 May '19

24 May '19

Hi Dmitry, you can define the settings for unavailable clock synthesizer An example of UART clock setting defined in coreboot\src\drivers\uart\Kconfig what are the configuration options to be set for IDT clock 9VRS4420DKLFT? Do you have datasheet for 9VRS4420DKLFT Is this the one? https://ua.infinite-electronic.com/datasheet/63-9VRS4339BKLF.pdf Regards Ranga From: Дмитрий Понаморев <dponamorev(a)gmail.com<mailto:dponamorev@gmail.com>> Sent: Friday 24 May 2019 15:23 To: Kyösti Mälkki <kyosti.malkki(a)gmail.com<mailto:kyosti.malkki@gmail.com>> Cc: Shreesh Chhabbi <schhabbi(a)ircona.com<mailto:schhabbi@ircona.com>>; coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Subject: [coreboot] Re: How to add NUVOTON NCT6776F support with serial port logic enabled ??? Thank for help! The LPC_CLKOUT1 clock signal appeared but there is no nuvoton chip detected in linux. I could not turn off the SOC UART yet. With my changes, the system does not start well (stops at post code 0x46, 0x47). /*Disabled SOC UART1 & UART2*/ u32 reg32; reg32 = pci_read_config32(SOC_LPC_DEV /*(0,1f,0)*/, UART_CONT /*0x80*/); reg32 = reg32 & (~0x3); pci_write_config32(SOC_LPC_DEV, UART_CONT, reg32); And the most important thing is that the Nuvoton System Clock (48 MHz for the baud generator of the UARTs) is missing. IDT clock synthesizer (9VRS4420DKLFT) is responsible for the formation of this clock. This clock synthesizer provides reference clocks for I/O interfaces, SATA, USB, Gbe and PCI Express. At the initial moment of time, the clock synthesizer is initialized via the SMB bus (I can see it with an oscilloscope). But no 48 MHz clock for Nuvoton. Nuvoton System Clock, use the USB_48M_2X contact of 9VRS4420DKLFT, which is normally not used. How can I change the IDT clock synthesizer (9VRS4420DKLFT) settings in coreboot? Rather, where can I make changes in coreboot to properly configure IDT clock synthesizer (9VRS4420DKLFT)? Best Regards, Dmitry Ponamorev ср, 22 мая 2019 г. в 21:46, Kyösti Mälkki <kyosti.malkki(a)gmail.com<mailto:kyosti.malkki@gmail.com>>: On Wed, May 22, 2019 at 6:14 PM Дмитрий Понаморев <dponamorev(a)gmail.com<mailto:dponamorev@gmail.com>> wrote: > > The controversial decision but the console output is not connected directly to the processor but to the superio Nuvoton. > I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. > In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC control register). > This register includes LPC_CLKOUT1. As far as I understood, the nuvoton uses this signal. > Okay then. The paragraphs of datasheet you should be interested are: 24.2.4 about the LPC routing rules. It says anything not positively decoded by SOC integrated peripherals will be routed to LPC. 20.2 and 20.3 to disable the SoC's integrated UART devices. When enabled, they would positively decode 0x3f8 and 0x2f8 (bases) and prevent those from being routed to LPC controller. If you previously did not have LPC_CLK running for the Nuvoton part in your coreboot build, it explains why util/superiotool did not detect Nuvoton. If you did not do so already, run that tool again. Hopefully you see something on 0x4e now. SuperIOs typically have another clock input pin (either 24 MHz or 48 MHz) for the baud generator of the UARTs. If you get that Nuvoton detected, and disable SoC UARTs, and still have no serial output, I would trace the source for that clock next. Regards, Kyösti

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 24 May '19

24 May '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 12 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1401467: Null pointer dereferences (FORWARD_NULL) ________________________________________________________________________________________________________ *** CID 1401467: Null pointer dereferences (FORWARD_NULL) /src/drivers/intel/fsp1_1/car.c: 176 in romstage_c_entry() 170 } else { 171 /* This leaks a mapping which this code assumes is benign as 172 * the flash is memory mapped CPU's address space. */ 173 fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); 174 } 175 >>> CID 1401467: Null pointer dereferences (FORWARD_NULL) >>> Passing null pointer "fih" to "cache_as_ram_stage_main", which dereferences it. 176 cache_as_ram_stage_main(fih); 177 178 /* we don't return here */ 179 platform_enter_postcar(); 180 } 181 ** CID 1353342: (OVERRUN) ________________________________________________________________________________________________________ *** CID 1353342: (OVERRUN) /3rdparty/chromeec/common/pwm.c: 120 in cc_pwm_duty() 114 char *e; 115 char *raw; 116 117 if (argc < 2) { 118 ccprintf("PWM channels:\n"); 119 for (ch = 0; ch < PWM_CH_COUNT; ch++) >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "print_channel". 120 print_channel(ch, max_duty); 121 return EC_SUCCESS; 122 } 123 124 ch = strtoi(argv[1], &e, 0); 125 if (*e || ch < 0 || ch >= PWM_CH_COUNT) /3rdparty/chromeec/common/pwm.c: 148 in cc_pwm_duty() 142 return EC_ERROR_PARAM2; 143 } else if (value < 0) { 144 /* Negative = disable */ 145 pwm_enable(ch, 0); 146 } else { 147 ccprintf("Setting channel %d to %d\n", ch, value); >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "pwm_enable". 148 pwm_enable(ch, 1); 149 (max_duty == 100) ? pwm_set_duty(ch, value) : 150 pwm_set_raw_duty(ch, value); 151 } 152 } 153 /3rdparty/chromeec/common/pwm.c: 149 in cc_pwm_duty() 143 } else if (value < 0) { 144 /* Negative = disable */ 145 pwm_enable(ch, 0); 146 } else { 147 ccprintf("Setting channel %d to %d\n", ch, value); 148 pwm_enable(ch, 1); >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "pwm_set_raw_duty". 149 (max_duty == 100) ? pwm_set_duty(ch, value) : 150 pwm_set_raw_duty(ch, value); 151 } 152 } 153 154 print_channel(ch, max_duty); /3rdparty/chromeec/common/pwm.c: 154 in cc_pwm_duty() 148 pwm_enable(ch, 1); 149 (max_duty == 100) ? pwm_set_duty(ch, value) : 150 pwm_set_raw_duty(ch, value); 151 } 152 } 153 >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "print_channel". 154 print_channel(ch, max_duty); 155 156 return EC_SUCCESS; 157 } 158 DECLARE_CONSOLE_COMMAND(pwmduty, cc_pwm_duty, 159 "[channel [<percent> | -1=disable] | [raw <value>]]", ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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coreboot May 2019