coreboot May 2019

coreboot@coreboot.org

49 participants
56 discussions

Re: Lenovo G505S : USB issues at Qubes OS
by Mike Banon 14 May '19

14 May '19

Hi there Rogier, Why no tint? ;-) tint patch adds a checksum verification for the archive that will be downloaded later from Free Software Foundation during the compilation, so no security risk there. Perhaps the only downside of this tint tetris is that currently it's not compressed while being added to CBFS, so occupies about 90KB if I remember correctly, while that could be much less. Although there is a lot of free space at CBFS (>3 MB out of 4MB) while simply building a coreboot, if you'd like to add a lot of floppy-based OS later - even as few as 90KB might be an issue. It's strange that you got a variable degree of this USB issue at different laptops, it should've been the same regardless of your dGPU type. Seems to be a Qubes-only problem, a bit random, and might be possible to fix if you'd read a note here - http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#TODO_list . Here's a copy-paste : " 2) Both XHCI options in Coreboot menu should be disabled (unless you'd like to add the XHCI firmware) or the left side ports won't work at all. These options are already disabled by default and all the ports are functioning as USB 2.0. awokd tells: "You may have to use irqpoll in sys-usb kernel options with Qubes OS. USB interrupts don't seem to be routing correctly in Coreboot, and the only way to use them in Qubes is with irqpoll in the kernel options." " Perhaps awokd knows more about this issue, you could try to e-mail him directly. P.S. Hope you don't mind that I CC a coreboot mailing list, this troubleshooting knowledge may be useful to someone else so should be public On Tue, May 14, 2019 at 7:48 AM Rogier en Ingrid <rogieringrid(a)gmail.com> wrote: > > I got a few issues - mainly with Qubes 4.0.1. Not included the tint patch, also changed the .config to not include tint. For the rest, included all your nice patches. > > After installing Qubes 4.0.1, initialization of the OS, i noticed some errors when starting (will include them later today in 2nd mail) and mainly some weird USB port behavior: the laptop with dgpu R5-M230: none of the USB ports work when running Qubes (though all work at boot). the laptop with dgpu HD-8570M: usb 2.0 port does not work, both usb 3 on the left work. > Only again when running Qubes, not when booting a live Ubuntu for example. >

2 1

Coreboot hangs with post code 0x75. How to describe the PCIe Switch (Asmedia ASM1182e) and devices connected after it for devicetree.cb?
by dponamorev＠gmail.com 13 May '19

13 May '19

I'm trying to develop a coreboot+seabios for motherboard MB-7573 by LANNER, CPU Intel(R) Atom(TM) CPU C2758. PCI root port 4 configured as x4. PCIe Switch (Asmedia ASM1182e) connected to root port 4. Two more devices are connected to ASM1182e - Xillinx network device and RDC C6139(PCI bridge & VGA). How to describe the PCIe Switch (Asmedia ASM1182e) and devices connected after it for devicetree.cb? Link to Asmedia ASM1182e: http://www.asmedia.com.tw/eng/e_show_products.php?cate_index=168&item=134 My version of devicetree.cb not work and coreboot hangs on post code 0x75 (POST_BS_DEV_INIT): device domain 0 on device pci 00.0 on end # host bridge device pci 1.0 on end # PCIe Port #1 x4 device pci 2.0 on end # PCIe Port #2 x4 device pci 3.0 on end # PCIe Port #3 x4 device pci 4.0 on subsystemid 1b21 1182 device pci 0.0 on subsystemid 1b21 1182 device pci 03.0 on subsystemid 10ee 2012 end subsystemid 1b21 1182 device pci 07.0 on subsystemid 17f3 1035 device pci 0.0 on subsystemid 17f3 2200 end end end end # PCIe Port #4 x4 Hangs on init_link function (POST_BS_DEV_INIT=0x75). coreboot/src/device/device.c static void init_link(struct bus *link) { struct device *dev; struct bus *c_link; for (dev = link->children; dev; dev = dev->sibling) { post_code(POST_BS_DEV_INIT); post_log_path(dev); init_dev(dev); } for (dev = link->children; dev; dev = dev->sibling) { for (c_link = dev->link_list; c_link; c_link = c_link->next) init_link(c_link); } } More visually device tree so: +-04.0-[04-08]----00.0-[05-08]--+-03.0-[06]----00.0 10ee:2012 | \-07.0-[07-08]----00.0-[08]----00.0 RDC Semiconductor, Inc. Device 2200 Full lspci output: [root@localhost ~]# lspci 00:00.0 Host bridge: Intel Corporation Atom processor C2000 SoC Transaction Router (rev 02) 00:01.0 PCI bridge: Intel Corporation Atom processor C2000 PCIe Root Port 1 (rev 02) 00:02.0 PCI bridge: Intel Corporation Atom processor C2000 PCIe Root Port 2 (rev 02) 00:03.0 PCI bridge: Intel Corporation Atom processor C2000 PCIe Root Port 3 (rev 02) 00:04.0 PCI bridge: Intel Corporation Atom processor C2000 PCIe Root Port 4 (rev 02) 00:0b.0 Co-processor: Intel Corporation Atom processor C2000 QAT (rev 02) 00:0e.0 Host bridge: Intel Corporation Atom processor C2000 RAS (rev 02) 00:0f.0 IOMMU: Intel Corporation Atom processor C2000 RCEC (rev 02) 00:13.0 System peripheral: Intel Corporation Atom processor C2000 SMBus 2.0 (rev 02) 00:14.0 Ethernet controller: Intel Corporation Ethernet Connection I354 (rev 03) 00:14.1 Ethernet controller: Intel Corporation Ethernet Connection I354 (rev 03) 00:14.2 Ethernet controller: Intel Corporation Ethernet Connection I354 (rev 03) 00:14.3 Ethernet controller: Intel Corporation Ethernet Connection I354 (rev 03) 00:16.0 USB controller: Intel Corporation Atom processor C2000 USB Enhanced Host Controller (rev 02) 00:17.0 SATA controller: Intel Corporation Atom processor C2000 AHCI SATA2 Controller (rev 02) 00:18.0 SATA controller: Intel Corporation Atom processor C2000 AHCI SATA3 Controller (rev 02) 00:1f.0 ISA bridge: Intel Corporation Atom processor C2000 PCU (rev 02) 00:1f.3 SMBus: Intel Corporation Atom processor C2000 PCU SMBus (rev 02) 01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03) 02:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03) 04:00.0 PCI bridge: ASMedia Technology Inc. Device 1182 05:03.0 PCI bridge: ASMedia Technology Inc. Device 1182 05:07.0 PCI bridge: ASMedia Technology Inc. Device 1182 06:00.0 Network controller: Xilinx Corporation Device 2012 (rev 0a) 07:00.0 PCI bridge: RDC Semiconductor, Inc. Device 1035 (rev 02) 08:00.0 VGA compatible controller: RDC Semiconductor, Inc. Device 2200 [root@localhost ~]# lspci -ntvvv -[0000:00]-+-00.0 8086:1f08 +-01.0-[01]----00.0 8086:1533 +-02.0-[02]----00.0 8086:1533 +-03.0-[03]---- | +-04.0-[04-08]----00.0-[05-08]--+-03.0-[06]----00.0 10ee:2012 | \-07.0-[07-08]----00.0-[08]----00.0 17f3:2200 +-0b.0 8086:1f18 +-0e.0 8086:1f14 +-0f.0 8086:1f16 +-13.0 8086:1f15 +-14.0 8086:1f41 +-14.1 8086:1f41 +-14.2 8086:1f41 +-14.3 8086:1f41 +-16.0 8086:1f2c +-17.0 8086:1f22 +-18.0 8086:1f32 +-1f.0 8086:1f38 \-1f.3 8086:1f3c Fedora boot log: [ 1.579482] PCI host bridge to bus 0000:00 [ 1.583065] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] [ 1.590063] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 1.597062] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] [ 1.604062] pci_bus 0000:00: root bus resource [mem 0x80000000-0xdfffffff window] [ 1.612063] pci_bus 0000:00: root bus resource [mem 0x280000000-0xfffffffff window] [ 1.619063] pci_bus 0000:00: root bus resource [bus 00-ff] [ 1.625070] pci 0000:00:00.0: [8086:1f08] type 00 class 0x060000 [ 1.625214] pci 0000:00:01.0: [8086:1f10] type 01 class 0x060400 [ 1.625239] pci 0000:00:01.0: reg 0x10: [mem 0xdfc00000-0xdfc1ffff 64bit] [ 1.625254] pci 0000:00:01.0: enabling Extended Tags [ 1.630099] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold [ 1.630242] pci 0000:00:02.0: [8086:1f11] type 01 class 0x060400 [ 1.630266] pci 0000:00:02.0: reg 0x10: [mem 0xdfbe0000-0xdfbfffff 64bit] [ 1.630281] pci 0000:00:02.0: enabling Extended Tags [ 1.635099] pci 0000:00:02.0: PME# supported from D0 D3hot D3cold [ 1.635236] pci 0000:00:03.0: [8086:1f12] type 01 class 0x060400 [ 1.635260] pci 0000:00:03.0: reg 0x10: [mem 0xdfbc0000-0xdfbdffff 64bit] [ 1.635276] pci 0000:00:03.0: enabling Extended Tags [ 1.640100] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold [ 1.640237] pci 0000:00:04.0: [8086:1f13] type 01 class 0x060400 [ 1.640261] pci 0000:00:04.0: reg 0x10: [mem 0xdfba0000-0xdfbbffff 64bit] [ 1.640276] pci 0000:00:04.0: enabling Extended Tags [ 1.646098] pci 0000:00:04.0: PME# supported from D0 D3hot D3cold [ 1.646244] pci 0000:00:0b.0: [8086:1f18] type 00 class 0x0b4000 [ 1.646277] pci 0000:00:0b.0: reg 0x18: [mem 0xdfb80000-0xdfb9ffff 64bit] [ 1.646289] pci 0000:00:0b.0: reg 0x20: [mem 0xdfc30000-0xdfc33fff 64bit] [ 1.646459] pci 0000:00:0e.0: [8086:1f14] type 00 class 0x060000 [ 1.646610] pci 0000:00:0f.0: [8086:1f16] type 00 class 0x080600 [ 1.646667] pci 0000:00:0f.0: PME# supported from D0 D3hot D3cold [ 1.646803] pci 0000:00:13.0: [8086:1f15] type 00 class 0x088000 [ 1.646827] pci 0000:00:13.0: reg 0x10: [mem 0xdfc38000-0xdfc383ff 64bit] [ 1.647029] pci 0000:00:14.0: [8086:1f41] type 00 class 0x020000 [ 1.647051] pci 0000:00:14.0: reg 0x10: [mem 0xdfb60000-0xdfb7ffff 64bit] [ 1.647057] pci 0000:00:14.0: reg 0x18: [io 0xe0c0-0xe0df] [ 1.647077] pci 0000:00:14.0: reg 0x20: [mem 0xdfc2c000-0xdfc2ffff 64bit] [ 1.647130] pci 0000:00:14.0: PME# supported from D0 D3hot D3cold [ 1.647266] pci 0000:00:14.1: [8086:1f41] type 00 class 0x020000 [ 1.647288] pci 0000:00:14.1: reg 0x10: [mem 0xdfb40000-0xdfb5ffff 64bit] [ 1.647296] pci 0000:00:14.1: reg 0x18: [io 0xe0a0-0xe0bf] [ 1.647313] pci 0000:00:14.1: reg 0x20: [mem 0xdfc28000-0xdfc2bfff 64bit] [ 1.647365] pci 0000:00:14.1: PME# supported from D0 D3hot D3cold [ 1.647505] pci 0000:00:14.2: [8086:1f41] type 00 class 0x020000 [ 1.647528] pci 0000:00:14.2: reg 0x10: [mem 0xdfb20000-0xdfb3ffff 64bit] [ 1.647536] pci 0000:00:14.2: reg 0x18: [io 0xe080-0xe09f] [ 1.647552] pci 0000:00:14.2: reg 0x20: [mem 0xdfc24000-0xdfc27fff 64bit] [ 1.647604] pci 0000:00:14.2: PME# supported from D0 D3hot D3cold [ 1.647739] pci 0000:00:14.3: [8086:1f41] type 00 class 0x020000 [ 1.647762] pci 0000:00:14.3: reg 0x10: [mem 0xdfb00000-0xdfb1ffff 64bit] [ 1.647770] pci 0000:00:14.3: reg 0x18: [io 0xe060-0xe07f] [ 1.647786] pci 0000:00:14.3: reg 0x20: [mem 0xdfc20000-0xdfc23fff 64bit] [ 1.647838] pci 0000:00:14.3: PME# supported from D0 D3hot D3cold [ 1.647980] pci 0000:00:16.0: [8086:1f2c] type 00 class 0x0c0320 [ 1.648008] pci 0000:00:16.0: reg 0x10: [mem 0xdfc37000-0xdfc373ff] [ 1.648115] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold [ 1.648243] pci 0000:00:17.0: [8086:1f22] type 00 class 0x010601 [ 1.648262] pci 0000:00:17.0: reg 0x10: [io 0xe150-0xe157] [ 1.648270] pci 0000:00:17.0: reg 0x14: [io 0xe140-0xe143] [ 1.648278] pci 0000:00:17.0: reg 0x18: [io 0xe130-0xe137] [ 1.648286] pci 0000:00:17.0: reg 0x1c: [io 0xe120-0xe123] [ 1.648294] pci 0000:00:17.0: reg 0x20: [io 0xe040-0xe05f] [ 1.648302] pci 0000:00:17.0: reg 0x24: [mem 0xdfc36000-0xdfc367ff] [ 1.648342] pci 0000:00:17.0: PME# supported from D3hot [ 1.648466] pci 0000:00:18.0: [8086:1f32] type 00 class 0x010601 [ 1.648485] pci 0000:00:18.0: reg 0x10: [io 0xe110-0xe117] [ 1.648493] pci 0000:00:18.0: reg 0x14: [io 0xe100-0xe103] [ 1.648501] pci 0000:00:18.0: reg 0x18: [io 0xe0f0-0xe0f7] [ 1.648509] pci 0000:00:18.0: reg 0x1c: [io 0xe0e0-0xe0e3] [ 1.648516] pci 0000:00:18.0: reg 0x20: [io 0xe020-0xe03f] [ 1.648524] pci 0000:00:18.0: reg 0x24: [mem 0xdfc35000-0xdfc357ff] [ 1.648565] pci 0000:00:18.0: PME# supported from D3hot [ 1.648696] pci 0000:00:1f.0: [8086:1f38] type 00 class 0x060100 [ 1.648878] pci 0000:00:1f.3: [8086:1f3c] type 00 class 0x0c0500 [ 1.648897] pci 0000:00:1f.3: reg 0x10: [mem 0xdfc34000-0xdfc3401f] [ 1.648928] pci 0000:00:1f.3: reg 0x20: [io 0xe000-0xe01f] [ 1.649153] pci 0000:01:00.0: [8086:1533] type 00 class 0x020000 [ 1.649190] pci 0000:01:00.0: reg 0x10: [mem 0xdf900000-0xdf9fffff] [ 1.649228] pci 0000:01:00.0: reg 0x1c: [mem 0xdfa00000-0xdfa03fff] [ 1.649267] pci 0000:01:00.0: reg 0x30: [mem 0xdf800000-0xdf8fffff pref] [ 1.649365] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold [ 1.649507] pci 0000:00:01.0: PCI bridge to [bus 01] [ 1.654067] pci 0000:00:01.0: bridge window [mem 0xdf800000-0xdfafffff] [ 1.654160] pci 0000:02:00.0: [8086:1533] type 00 class 0x020000 [ 1.654197] pci 0000:02:00.0: reg 0x10: [mem 0xdf600000-0xdf6fffff] [ 1.654235] pci 0000:02:00.0: reg 0x1c: [mem 0xdf700000-0xdf703fff] [ 1.654274] pci 0000:02:00.0: reg 0x30: [mem 0xdf500000-0xdf5fffff pref] [ 1.654371] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold [ 1.654512] pci 0000:00:02.0: PCI bridge to [bus 02] [ 1.659066] pci 0000:00:02.0: bridge window [mem 0xdf500000-0xdf7fffff] [ 1.659136] pci 0000:00:03.0: PCI bridge to [bus 03] [ 1.664146] pci 0000:04:00.0: [1b21:1182] type 01 class 0x060400 [ 1.664200] pci 0000:04:00.0: enabling Extended Tags [ 1.670124] pci 0000:04:00.0: PME# supported from D0 D3hot D3cold [ 1.670249] pci 0000:00:04.0: PCI bridge to [bus 04-08] [ 1.675064] pci 0000:00:04.0: bridge window [io 0xd000-0xdfff] [ 1.675068] pci 0000:00:04.0: bridge window [mem 0xdf000000-0xdf4fffff] [ 1.675144] pci 0000:05:03.0: [1b21:1182] type 01 class 0x060400 [ 1.675198] pci 0000:05:03.0: enabling Extended Tags [ 1.680124] pci 0000:05:03.0: PME# supported from D0 D3hot D3cold [ 1.680226] pci 0000:05:07.0: [1b21:1182] type 01 class 0x060400 [ 1.680280] pci 0000:05:07.0: enabling Extended Tags [ 1.685123] pci 0000:05:07.0: PME# supported from D0 D3hot D3cold [ 1.685238] pci 0000:04:00.0: PCI bridge to [bus 05-08] [ 1.691068] pci 0000:04:00.0: bridge window [io 0xd000-0xdfff] [ 1.691073] pci 0000:04:00.0: bridge window [mem 0xdf000000-0xdf4fffff] [ 1.691131] pci 0000:05:03.0: PCI bridge to [bus 06] [ 1.696148] pci 0000:07:00.0: [17f3:1035] type 01 class 0x060400 [ 1.696316] pci 0000:07:00.0: PME# supported from D0 D3hot D3cold [ 1.696418] pci 0000:07:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' [ 1.706074] pci 0000:05:07.0: PCI bridge to [bus 07-08] [ 1.711071] pci 0000:05:07.0: bridge window [io 0xd000-0xdfff] [ 1.711076] pci 0000:05:07.0: bridge window [mem 0xdf000000-0xdf4fffff] [ 1.711145] pci_bus 0000:08: extended config space not accessible [ 1.717098] pci 0000:08:00.0: [17f3:2200] type 00 class 0x030000 [ 1.717131] pci 0000:08:00.0: reg 0x10: [mem 0xdf000000-0xdf3fffff] [ 1.717149] pci 0000:08:00.0: reg 0x14: [mem 0xdf400000-0xdf41ffff] [ 1.717167] pci 0000:08:00.0: reg 0x18: [io 0xd000-0xd07f] [ 1.717230] pci 0000:08:00.0: reg 0x30: [mem 0xdf420000-0xdf42ffff pref] [ 1.717288] pci 0000:08:00.0: supports D1 D2 [ 1.717415] pci 0000:07:00.0: PCI bridge to [bus 08] [ 1.723067] pci 0000:07:00.0: bridge window [io 0xd000-0xdfff] [ 1.723074] pci 0000:07:00.0: bridge window [mem 0xdf000000-0xdf4fffff] [ 1.723080] pci 0000:07:00.0: bridge window [mem 0x00000000-0x000fffff pref] [ 1.723321] ACPI: PCI Interrupt Link [LNKA] (IRQs 6 7 10 *11 12 15) [ 1.729169] ACPI: PCI Interrupt Link [LNKB] (IRQs 6 7 *10 11 12 15) [ 1.736169] ACPI: PCI Interrupt Link [LNKC] (IRQs 6 *7 10 11 12 15) [ 1.742168] ACPI: PCI Interrupt Link [LNKD] (IRQs 6 7 10 11 12 *15) [ 1.748168] ACPI: PCI Interrupt Link [LNKE] (IRQs 6 7 10 11 12 *15) [ 1.755169] ACPI: PCI Interrupt Link [LNKF] (IRQs 6 7 *10 11 12 15) [ 1.761167] ACPI: PCI Interrupt Link [LNKG] (IRQs 6 7 10 *11 12 15) [ 1.767169] ACPI: PCI Interrupt Link [LNKH] (IRQs 6 *7 10 11 12 15) [ 1.775172] pci 0000:08:00.0: vgaarb: setting as boot VGA device [ 1.776057] pci 0000:08:00.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none [ 1.790065] pci 0000:08:00.0: vgaarb: bridge control possible

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[libgfxinit] unable to power up display
by madeeha＠gmail.com 10 May '19

10 May '19

Hi Libgfxinit folks, I am using Libgfxinit built for Skylake platform to enable early graphics from within a baremetal application. The platform connects to an LCD via HDMI. Enabling debug log in Libgfxinit, I get the following from which it seems that the initialization completed successfully but the LCD remains powered off (orange light). Is there anything outside of this mode set sequence that I need to do to enable the display? [106.904524] HW.GFX.GMA.Initialize [106.907477] HW.GFX.GMA.Panel.Setup_PP_Sequencer [106.911825] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS [106.919119] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS [106.926500] HW.GFX.GMA.Registers.Read: 0x0004af00 <- 0x000c7210:PCH_PP_DIVISOR [106.933613] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS [106.939872] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS [106.947159] HW.GFX.GMA.Registers.Write: 0x08340001 -> 0x000c7208:PCH_PP_ON_DELAYS [106.954454] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS [106.960798] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS [106.968173] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS [106.975554] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR [106.981639] HW.GFX.GMA.Registers.Read: 0x0004af00 <- 0x000c7210:PCH_PP_DIVISOR [106.988754] HW.GFX.GMA.Registers.Write: 0x0004af07 -> 0x000c7210:PCH_PP_DIVISOR [106.995874] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL [107.002307] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL [107.009420] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL [107.016542] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A [107.021925] HW.GFX.GMA.Registers.Read: 0x00000081 <- 0x00064000:DDI_BUF_CTL_A [107.028959] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [107.034870] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL [107.041810] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL [107.048757] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [107.053973] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP [107.060828] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [107.066738] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL [107.073678] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL [107.080626] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [107.085842] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP [107.092696] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [107.098606] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL [107.105547] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL [107.112495] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [107.117710] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP [107.124563] HW.GFX.GMA.Registers.Unset_Mask: 0x03130303 !S SHOTPLUG_CTL [107.130995] HW.GFX.GMA.Registers.Read: 0x10001010 <- 0x000c4030:SHOTPLUG_CTL [107.137936] HW.GFX.GMA.Registers.Write: 0x10001010 -> 0x000c4030:SHOTPLUG_CTL [107.144883] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e00:DDI_BUF_TRANS_A_S0T1 [107.152525] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2 [107.160166] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1 [107.167808] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2 [107.175450] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1 [107.183090] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e14:DDI_BUF_TRANS_A_S2T2 [107.190733] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1 [107.198373] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2 [107.206015] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e20:DDI_BUF_TRANS_A_S4T1 [107.213657] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e24:DDI_BUF_TRANS_A_S4T2 [107.221299] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1 [107.228940] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2 [107.236582] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1 [107.244222] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2 [107.251864] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1 [107.259505] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2 [107.267146] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1 [107.274788] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2 [107.282431] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1 [107.290072] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2 [107.297714] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e60:DDI_BUF_TRANS_B_S0T1 [107.305355] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2 [107.312996] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1 [107.320637] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2 [107.328280] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1 [107.335920] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e74:DDI_BUF_TRANS_B_S2T2 [107.343562] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1 [107.351204] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2 [107.358845] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e80:DDI_BUF_TRANS_B_S4T1 [107.366487] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e84:DDI_BUF_TRANS_B_S4T2 [107.374129] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1 [107.381770] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2 [107.389410] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1 [107.397054] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2 [107.404694] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1 [107.412336] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2 [107.419978] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1 [107.427618] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2 [107.435260] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1 [107.442902] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2 [107.450542] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1 [107.458184] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2 [107.465827] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1 [107.473467] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2 [107.481109] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1 [107.488750] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2 [107.496393] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1 [107.504034] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2 [107.511676] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1 [107.519316] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2 [107.526957] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1 [107.534599] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2 [107.542242] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1 [107.549883] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2 [107.557525] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1 [107.565165] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064efc:DDI_BUF_TRANS_C_S7T2 [107.572807] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1 [107.580448] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2 [107.588089] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1 [107.595731] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2 [107.603372] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f20:DDI_BUF_TRANS_D_S0T1 [107.611014] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064f24:DDI_BUF_TRANS_D_S0T2 [107.618655] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f28:DDI_BUF_TRANS_D_S1T1 [107.626297] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f2c:DDI_BUF_TRANS_D_S1T2 [107.633939] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064f30:DDI_BUF_TRANS_D_S2T1 [107.641580] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f34:DDI_BUF_TRANS_D_S2T2 [107.649222] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064f38:DDI_BUF_TRANS_D_S3T1 [107.656863] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f3c:DDI_BUF_TRANS_D_S3T2 [107.664505] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f40:DDI_BUF_TRANS_D_S4T1 [107.672146] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f44:DDI_BUF_TRANS_D_S4T2 [107.679787] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f48:DDI_BUF_TRANS_D_S5T1 [107.687429] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f4c:DDI_BUF_TRANS_D_S5T2 [107.695070] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064f50:DDI_BUF_TRANS_D_S6T1 [107.702713] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f54:DDI_BUF_TRANS_D_S6T2 [107.710355] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f58:DDI_BUF_TRANS_D_S7T1 [107.717995] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064f5c:DDI_BUF_TRANS_D_S7T2 [107.725636] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f60:DDI_BUF_TRANS_D_S8T1 [107.733278] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f64:DDI_BUF_TRANS_D_S8T2 [107.740919] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f68:DDI_BUF_TRANS_D_S9T1 [107.748562] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f6c:DDI_BUF_TRANS_D_S9T2 [107.756203] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f80:DDI_BUF_TRANS_E_S0T1 [107.763844] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064f84:DDI_BUF_TRANS_E_S0T2 [107.771486] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f88:DDI_BUF_TRANS_E_S1T1 [107.779127] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f8c:DDI_BUF_TRANS_E_S1T2 [107.786769] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064f90:DDI_BUF_TRANS_E_S2T1 [107.794410] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f94:DDI_BUF_TRANS_E_S2T2 [107.802052] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064f98:DDI_BUF_TRANS_E_S3T1 [107.809692] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f9c:DDI_BUF_TRANS_E_S3T2 [107.817335] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064fa0:DDI_BUF_TRANS_E_S4T1 [107.824977] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064fa4:DDI_BUF_TRANS_E_S4T2 [107.832618] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064fa8:DDI_BUF_TRANS_E_S5T1 [107.840260] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064fac:DDI_BUF_TRANS_E_S5T2 [107.847901] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064fb0:DDI_BUF_TRANS_E_S6T1 [107.855542] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064fb4:DDI_BUF_TRANS_E_S6T2 [107.863183] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064fb8:DDI_BUF_TRANS_E_S7T1 [107.870825] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064fbc:DDI_BUF_TRANS_E_S7T2 [107.878466] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064fc0:DDI_BUF_TRANS_E_S8T1 [107.886108] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064fc4:DDI_BUF_TRANS_E_S8T2 [107.893749] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064fc8:DDI_BUF_TRANS_E_S9T1 [107.901392] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064fcc:DDI_BUF_TRANS_E_S9T2 [107.909033] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0 [107.915633] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0 [107.923274] HW.GFX.GMA.Registers.Write: 0x00124900 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0 [107.930915] HW.GFX.GMA.Power_And_Clocks_Haswell.PSR_Off [107.935952] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_EDP [107.941162] HW.GFX.GMA.Registers.Read: 0x00100001 <- 0x0006f800:SRD_CTL_EDP [107.948021] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_A [107.953058] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00060800:SRD_CTL_A [107.959745] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_B [107.964781] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00061800:SRD_CTL_B [107.971468] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_C [107.976504] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00062800:SRD_CTL_C [107.983190] HW.GFX.GMA.Panel.Backlight_Off [107.987097] HW.GFX.GMA.Registers.Unset_Mask: 0x00000004 !S PCH_PP_CONTROL [107.993703] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000c7204:PCH_PP_CONTROL [108.000818] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL [108.007937] HW.GFX.GMA.Panel.Off [108.010978] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL [108.016455] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000c7204:PCH_PP_CONTROL [108.023569] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL [108.030174] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000c7204:PCH_PP_CONTROL [108.037288] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL [108.044408] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS [108.052577] HW.GFX.GMA.Pipe_Setup.All_Off [108.056493] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL [108.062644] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL [108.069590] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL [108.076537] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [108.083225] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000700a0:CUR_FBC_CTL_A [108.090257] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPACNTR [108.096250] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070280:SPACNTR [108.102762] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070280:SPACNTR [108.109274] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007017c:CUR_BUF_CFG_A [108.116307] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070140:CUR_WM_A_0 [108.123081] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070144:CUR_WM_A_1 [108.129854] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070148:CUR_WM_A_2 [108.136629] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007014c:CUR_WM_A_3 [108.143401] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070150:CUR_WM_A_4 [108.150174] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070154:CUR_WM_A_5 [108.156948] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070158:CUR_WM_A_6 [108.163721] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007015c:CUR_WM_A_7 [108.170493] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007027c:PLANE_BUF_CFG_1_A [108.177875] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070240:PLANE_WM_1_A_0 [108.184994] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070244:PLANE_WM_1_A_1 [108.192114] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070248:PLANE_WM_1_A_2 [108.199236] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007024c:PLANE_WM_1_A_3 [108.206356] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070250:PLANE_WM_1_A_4 [108.213478] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070254:PLANE_WM_1_A_5 [108.220597] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070258:PLANE_WM_1_A_6 [108.227718] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007025c:PLANE_WM_1_A_7 [108.234837] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045270:WM_LINETIME_A [108.241872] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPACNTR [108.247951] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070180:DSPACNTR [108.254549] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070180:DSPACNTR [108.261150] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF [108.267749] HW.GFX.GMA.Registers.Read: 0x00030000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.275478] HW.GFX.GMA.Registers.Is_Set_Mask: PIPE_EDP_CONF [108.280860] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0007f008:PIPE_EDP_CONF [108.287894] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x0007f008:PIPE_EDP_CONF [108.296057] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.303786] HW.GFX.GMA.Registers.Is_Set_Mask: PIPEACONF [108.308822] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070008:PIPEACONF [108.315508] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00070008:PIPEACONF [108.323323] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00060400:PIPEA_DDI_FUNC_CTL [108.330792] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A [108.337131] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A [108.343990] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A [108.350850] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A [108.357884] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A [108.364222] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A [108.371082] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A [108.377943] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A [108.384976] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046140:TRANSA_CLK_SEL [108.392097] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071080:CUR_CTL_B [108.398783] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000710a0:CUR_FBC_CTL_B [108.405817] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPBCNTR [108.411808] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071280:SPBCNTR [108.418321] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071280:SPBCNTR [108.424833] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007117c:CUR_BUF_CFG_B [108.431867] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071140:CUR_WM_B_0 [108.438640] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071144:CUR_WM_B_1 [108.445414] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071148:CUR_WM_B_2 [108.452187] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007114c:CUR_WM_B_3 [108.458959] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071150:CUR_WM_B_4 [108.465733] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071154:CUR_WM_B_5 [108.472507] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071158:CUR_WM_B_6 [108.479278] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007115c:CUR_WM_B_7 [108.486052] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007127c:PLANE_BUF_CFG_1_B [108.493433] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071240:PLANE_WM_1_B_0 [108.500553] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071244:PLANE_WM_1_B_1 [108.507674] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071248:PLANE_WM_1_B_2 [108.514795] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007124c:PLANE_WM_1_B_3 [108.521915] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071250:PLANE_WM_1_B_4 [108.529035] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071254:PLANE_WM_1_B_5 [108.536156] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071258:PLANE_WM_1_B_6 [108.543276] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007125c:PLANE_WM_1_B_7 [108.550397] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045274:WM_LINETIME_B [108.557432] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPBCNTR [108.563509] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071180:DSPBCNTR [108.570109] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071180:DSPBCNTR [108.576708] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007119c:DSPBSURF [108.583309] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.591037] HW.GFX.GMA.Registers.Is_Set_Mask: PIPEBCONF [108.596073] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071008:PIPEBCONF [108.602759] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00071008:PIPEBCONF [108.610574] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00061400:PIPEB_DDI_FUNC_CTL [108.618041] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_B [108.624381] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068980:PS_CTRL_1_B [108.631241] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068980:PS_CTRL_1_B [108.638101] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068974:PS_WIN_SZ_1_B [108.645135] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_B [108.651473] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068a80:PS_CTRL_2_B [108.658334] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068a80:PS_CTRL_2_B [108.665193] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068a74:PS_WIN_SZ_2_B [108.672227] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046144:TRANSB_CLK_SEL [108.679348] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072080:CUR_CTL_C [108.686034] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000720a0:CUR_FBC_CTL_C [108.693067] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPCCNTR [108.699059] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072280:SPCCNTR [108.705572] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072280:SPCCNTR [108.712083] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007217c:CUR_BUF_CFG_C [108.719117] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072140:CUR_WM_C_0 [108.725891] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072144:CUR_WM_C_1 [108.732663] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072148:CUR_WM_C_2 [108.739438] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007214c:CUR_WM_C_3 [108.746210] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072150:CUR_WM_C_4 [108.752984] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072154:CUR_WM_C_5 [108.759757] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072158:CUR_WM_C_6 [108.766530] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007215c:CUR_WM_C_7 [108.773302] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007227c:PLANE_BUF_CFG_1_C [108.780685] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072240:PLANE_WM_1_C_0 [108.787804] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072244:PLANE_WM_1_C_1 [108.794924] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072248:PLANE_WM_1_C_2 [108.802045] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007224c:PLANE_WM_1_C_3 [108.809167] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072250:PLANE_WM_1_C_4 [108.816286] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072254:PLANE_WM_1_C_5 [108.823407] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072258:PLANE_WM_1_C_6 [108.830528] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007225c:PLANE_WM_1_C_7 [108.837647] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045278:WM_LINETIME_C [108.844681] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPCCNTR [108.850759] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072180:DSPCCNTR [108.857359] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072180:DSPCCNTR [108.863958] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007219c:DSPCSURF [108.870559] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.878288] HW.GFX.GMA.Registers.Is_Set_Mask: PIPECCONF [108.883323] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072008:PIPECCONF [108.890010] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00072008:PIPECCONF [108.897825] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00062400:PIPEC_DDI_FUNC_CTL [108.905292] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_C [108.911631] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00069180:PS_CTRL_1_C [108.918492] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00069180:PS_CTRL_1_C [108.925351] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00069174:PS_WIN_SZ_1_C [108.932385] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046148:TRANSC_CLK_SEL [108.939505] HW.GFX.GMA.Connectors.DDI.Off [108.943327] HW.GFX.GMA.Connectors.DDI.Digital_Off [108.947842] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A [108.953225] HW.GFX.GMA.Registers.Read: 0x00000081 <- 0x00064000:DDI_BUF_CTL_A [108.960260] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_A [108.966598] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064040:DP_TP_CTL_A [108.973457] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064040:DP_TP_CTL_A [108.980319] HW.GFX.GMA.Registers.Set_Mask: 0x00008000 .S DPLL_CTRL2 [108.986396] HW.GFX.GMA.Registers.Read: 0x00a10018 <- 0x0006c05c:DPLL_CTRL2 [108.993169] HW.GFX.GMA.Registers.Write: 0x00a18018 -> 0x0006c05c:DPLL_CTRL2 [108.999943] HW.GFX.GMA.Connectors.DDI.Off [109.003763] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.008279] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_B [109.013663] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064100:DDI_BUF_CTL_B [109.020696] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_B [109.027036] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064140:DP_TP_CTL_B [109.033894] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064140:DP_TP_CTL_B [109.040754] HW.GFX.GMA.Registers.Set_Mask: 0x00010000 .S DPLL_CTRL2 [109.046834] HW.GFX.GMA.Registers.Read: 0x00a18018 <- 0x0006c05c:DPLL_CTRL2 [109.053608] HW.GFX.GMA.Registers.Write: 0x00a18018 -> 0x0006c05c:DPLL_CTRL2 [109.060380] HW.GFX.GMA.Connectors.DDI.Off [109.064200] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.068716] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_C [109.074099] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064200:DDI_BUF_CTL_C [109.081134] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_C [109.087472] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064240:DP_TP_CTL_C [109.094333] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064240:DP_TP_CTL_C [109.101192] HW.GFX.GMA.Registers.Set_Mask: 0x00020000 .S DPLL_CTRL2 [109.107271] HW.GFX.GMA.Registers.Read: 0x00a18018 <- 0x0006c05c:DPLL_CTRL2 [109.114045] HW.GFX.GMA.Registers.Write: 0x00a38018 -> 0x0006c05c:DPLL_CTRL2 [109.120816] HW.GFX.GMA.Connectors.DDI.Off [109.124639] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.129154] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_D [109.134537] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064300:DDI_BUF_CTL_D [109.141570] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_D [109.147911] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064340:DP_TP_CTL_D [109.154770] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064340:DP_TP_CTL_D [109.161630] HW.GFX.GMA.Registers.Set_Mask: 0x00040000 .S DPLL_CTRL2 [109.167708] HW.GFX.GMA.Registers.Read: 0x00a38018 <- 0x0006c05c:DPLL_CTRL2 [109.174481] HW.GFX.GMA.Registers.Write: 0x00a78018 -> 0x0006c05c:DPLL_CTRL2 [109.181255] HW.GFX.GMA.Connectors.DDI.Off [109.185075] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.189590] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_E [109.194975] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064400:DDI_BUF_CTL_E [109.202008] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_E [109.208346] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064440:DP_TP_CTL_E [109.215206] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064440:DP_TP_CTL_E [109.222066] HW.GFX.GMA.Registers.Set_Mask: 0x00080000 .S DPLL_CTRL2 [109.228145] HW.GFX.GMA.Registers.Read: 0x00a78018 <- 0x0006c05c:DPLL_CTRL2 [109.234919] HW.GFX.GMA.Registers.Write: 0x00af8018 -> 0x0006c05c:DPLL_CTRL2 [109.241691] HW.GFX.GMA.PLLs.All_Off [109.244992] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S LCPLL2_CTL [109.251244] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00046014:LCPLL2_CTL [109.258016] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046014:LCPLL2_CTL [109.264791] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S WRPLL_CTL_2 [109.271129] HW.GFX.GMA.Registers.Read: 0x00202418 <- 0x00046060:WRPLL_CTL_2 [109.277988] HW.GFX.GMA.Registers.Write: 0x00202418 -> 0x00046060:WRPLL_CTL_2 [109.284848] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S WRPLL_CTL_1 [109.291187] HW.GFX.GMA.Registers.Read: 0x00202418 <- 0x00046040:WRPLL_CTL_1 [109.298049] HW.GFX.GMA.Registers.Write: 0x00202418 -> 0x00046040:WRPLL_CTL_1 [109.304908] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off [109.310031] PD is 3 [109.311942] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.319323] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.326876] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.334259] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.341725] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.348759] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.355793] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off [109.360917] PD is 4 [109.362826] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.370208] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.377763] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.385143] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.392611] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.399646] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.406679] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off [109.411802] PD is 5 [109.413713] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.421094] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.428648] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.436029] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.443497] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.450530] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.457564] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off [109.462687] PD is 6 [109.464598] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.471978] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.479534] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.486914] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.494381] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.501416] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.508449] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off [109.513573] PD is 2 [109.515484] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.522864] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.530418] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.537801] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.545268] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.552301] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.559335] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DBUF_CTL [109.565413] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL [109.572012] HW.GFX.GMA.Registers.Write: 0x0000000a -> 0x00045008:DBUF_CTL [109.578612] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00045008:DBUF_CTL [109.586340] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S LCPLL1_CTL [109.592592] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL [109.599366] HW.GFX.GMA.Registers.Write: 0x40000000 -> 0x00046010:LCPLL1_CTL [109.606140] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL [109.614041] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off [109.619165] PD is 2 [109.621076] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.628457] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.636011] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.643392] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.650859] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.657894] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.664926] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404: [109.673611] HW.GFX.GMA.Registers.Unset_Mask: 0x00000002 !S PWR_WELL_CTL_BIOS [109.680470] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.687851] HW.GFX.GMA.Registers.Write: 0x30000001 -> 0x00045400:PWR_WELL_CTL_BIOS [109.695232] HW.GFX.GMA.Registers.Unset_Mask: 0x00000002 !S PWR_WELL_CTL_DRIVER [109.702266] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.709821] HW.GFX.GMA.Registers.Write: 0x30000003 -> 0x00045404:PWR_WELL_CTL_DRIVER [109.717376] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off [109.722499] PD is 2 [109.724410] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.731790] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.739344] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.746726] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.754194] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.761228] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.768260] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404: [109.776944] HW.GFX.GMA.Registers.Unset_Mask: 0x20000000 !S PWR_WELL_CTL_BIOS [109.783804] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.791184] HW.GFX.GMA.Registers.Write: 0x10000001 -> 0x00045400:PWR_WELL_CTL_BIOS [109.798566] HW.GFX.GMA.Registers.Unset_Mask: 0x20000000 !S PWR_WELL_CTL_DRIVER [109.805600] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.813155] HW.GFX.GMA.Registers.Write: 0x10000003 -> 0x00045404:PWR_WELL_CTL_DRIVER [109.820713] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT [109.827135] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT [109.834255] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT [109.841376] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS [109.849364] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [109.854401] PD is 2 [109.856311] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.863692] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.871248] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.878629] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.886097] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.893131] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.900163] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_BIOS [109.906849] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.914230] HW.GFX.GMA.Registers.Write: 0x30000001 -> 0x00045400:PWR_WELL_CTL_BIOS [109.921610] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045400:PWR_WELL_CTL_BIOS [109.930122] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS [109.938110] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [109.943146] PD is 2 [109.945057] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.952439] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.959994] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.967375] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.974841] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.981876] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.988908] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_BIOS [109.995596] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [110.002977] HW.GFX.GMA.Registers.Write: 0x30000003 -> 0x00045400:PWR_WELL_CTL_BIOS [110.010357] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045400:PWR_WELL_CTL_BIOS [110.018867] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL [110.025552] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1 [110.031283] HW.GFX.GMA.Registers.Read: 0x00000845 <- 0x0006c058:DPLL_CTRL1 [110.038057] HW.GFX.GMA.Registers.Write: 0x00000847 -> 0x0006c058:DPLL_CTRL1 [110.044830] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL [110.050909] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00046010:LCPLL1_CTL [110.057682] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046010:LCPLL1_CTL [110.064455] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL [110.072357] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write [110.078175] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.086076] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA [110.093285] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 [110.100665] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX [110.107439] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.115342] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA [110.122547] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write [110.128365] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.136268] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA [110.143475] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 [110.150856] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX [110.157629] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.165532] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL [110.171436] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL [110.178035] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL [110.184634] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL [110.192363] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ [110.198535] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ [110.205735] HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ [110.212949] HW.GFX.GMA.Display_Probing.Read_EDID [110.217372] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [110.222408] PD is 2 [110.224319] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.231699] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.239253] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.246636] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.254104] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.261137] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.268170] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00045404: [110.276854] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_BIOS [110.283540] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.290920] HW.GFX.GMA.Registers.Write: 0xb0000003 -> 0x00045400:PWR_WELL_CTL_BIOS [110.298302] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045400:PWR_WELL_CTL_BIOS [110.306811] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [110.314802] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [110.321661] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.329215] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.336769] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [110.345453] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [110.353444] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [110.358478] PD is 5 [110.360389] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.367771] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.375325] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.382705] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.390174] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.397207] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.404242] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404: [110.412924] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_BIOS [110.419611] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.426991] HW.GFX.GMA.Registers.Write: 0xf0000023 -> 0x00045400:PWR_WELL_CTL_BIOS [110.434374] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045400:PWR_WELL_CTL_BIOS [110.442882] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER [110.449744] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.457298] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.464851] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404: [110.473535] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [110.478919] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B [110.485952] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [110.493247] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [110.499238] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B [110.506271] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [110.513305] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [110.521470] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.528503] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [110.533886] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.540919] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [110.548213] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [110.554206] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.561238] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [110.568273] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [110.576436] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.583469] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [110.588852] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.595886] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [110.603180] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [110.609172] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.616205] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [110.623240] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [110.631403] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.638436] HW.GFX.GMA.Display_Probing.Read_EDID [110.642864] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [110.647900] PD is 2 [110.649810] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045400:PWR_WELL_CTL_BIOS [110.657192] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.664747] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.672128] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.679595] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.686629] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.693662] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [110.700522] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.708077] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.715631] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [110.724316] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [110.732305] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [110.737341] PD is 4 [110.739251] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045400:PWR_WELL_CTL_BIOS [110.746633] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.754186] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.761567] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.769036] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.776069] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.783103] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404: [110.791785] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_BIOS [110.798472] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045400:PWR_WELL_CTL_BIOS [110.805854] HW.GFX.GMA.Registers.Write: 0xf00000b3 -> 0x00045400:PWR_WELL_CTL_BIOS [110.813235] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045400:PWR_WELL_CTL_BIOS [110.821744] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER [110.828605] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.836158] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.843713] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404: [110.852398] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C [110.857781] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C [110.864814] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 [110.872108] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C [110.878100] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C [110.885134] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C [110.892168] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C [110.900331] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.907363] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C [110.912747] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.919781] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 [110.927075] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C [110.933067] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.940101] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C [110.947134] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C [110.955297] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.962331] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C [110.967715] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.974748] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 [110.982042] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C [110.988033] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.995068] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C [111.002101] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C [111.010264] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [111.017297] HW.GFX.GMA.Display_Probing.Read_EDID [111.021726] HW.GFX.GMA.I2C.I2C_Read [111.025026] HW.GFX.GMA.I2C.Init_GMBUS [111.028499] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D [111.035192] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [111.042567] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D [111.049946] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 [111.057863] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 [111.064622] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0 [111.071395] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 [111.078169] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 [111.084941] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 [111.091714] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.099630] HW.GFX.GMA.Registers.Read: 0x00008a08 <- 0x000c5108:PCH_GMBUS2 [111.106397] HW.GFX.GMA.Registers.Read: 0xffffff00 <- 0x000c510c:PCH_GMBUS3 [111.113163] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.121080] HW.GFX.GMA.Registers.Read: 0x00008a0c <- 0x000c5108:PCH_GMBUS2 [111.127844] HW.GFX.GMA.Registers.Read: 0x00ffffff <- 0x000c510c:PCH_GMBUS3 [111.134611] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.142527] HW.GFX.GMA.Registers.Read: 0x00008a10 <- 0x000c5108:PCH_GMBUS2 [111.149292] HW.GFX.GMA.Registers.Read: 0x4042ac10 <- 0x000c510c:PCH_GMBUS3 [111.156059] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.163976] HW.GFX.GMA.Registers.Read: 0x00008a14 <- 0x000c5108:PCH_GMBUS2 [111.170741] HW.GFX.GMA.Registers.Read: 0x3138364c <- 0x000c510c:PCH_GMBUS3 [111.177508] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.185423] HW.GFX.GMA.Registers.Read: 0x00008a18 <- 0x000c5108:PCH_GMBUS2 [111.192189] HW.GFX.GMA.Registers.Read: 0x03011322 <- 0x000c510c:PCH_GMBUS3 [111.198956] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.206872] HW.GFX.GMA.Registers.Read: 0x00008a1c <- 0x000c5108:PCH_GMBUS2 [111.213638] HW.GFX.GMA.Registers.Read: 0x781b2b80 <- 0x000c510c:PCH_GMBUS3 [111.220404] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.228321] HW.GFX.GMA.Registers.Read: 0x00008a20 <- 0x000c5108:PCH_GMBUS2 [111.235086] HW.GFX.GMA.Registers.Read: 0xa705b72e <- 0x000c510c:PCH_GMBUS3 [111.241853] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.249769] HW.GFX.GMA.Registers.Read: 0x00008a24 <- 0x000c5108:PCH_GMBUS2 [111.256535] HW.GFX.GMA.Registers.Read: 0x26ad3854 <- 0x000c510c:PCH_GMBUS3 [111.263301] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.271218] HW.GFX.GMA.Registers.Read: 0x00008a28 <- 0x000c5108:PCH_GMBUS2 [111.277983] HW.GFX.GMA.Registers.Read: 0xbf54500e <- 0x000c510c:PCH_GMBUS3 [111.284749] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.292665] HW.GFX.GMA.Registers.Read: 0x00008a2c <- 0x000c5108:PCH_GMBUS2 [111.299431] HW.GFX.GMA.Registers.Read: 0x4f7180ef <- 0x000c510c:PCH_GMBUS3 [111.306197] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.314114] HW.GFX.GMA.Registers.Read: 0x00008a30 <- 0x000c5108:PCH_GMBUS2 [111.320880] HW.GFX.GMA.Registers.Read: 0x00b38081 <- 0x000c510c:PCH_GMBUS3 [111.327647] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.335561] HW.GFX.GMA.Registers.Read: 0x00008a34 <- 0x000c5108:PCH_GMBUS2 [111.342327] HW.GFX.GMA.Registers.Read: 0xc0810095 <- 0x000c510c:PCH_GMBUS3 [111.349095] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.357009] HW.GFX.GMA.Registers.Read: 0x00008a38 <- 0x000c5108:PCH_GMBUS2 [111.363775] HW.GFX.GMA.Registers.Read: 0x01010081 <- 0x000c510c:PCH_GMBUS3 [111.370542] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.378458] HW.GFX.GMA.Registers.Read: 0x00008a3c <- 0x000c5108:PCH_GMBUS2 [111.385224] HW.GFX.GMA.Registers.Read: 0x39210101 <- 0x000c510c:PCH_GMBUS3 [111.391991] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.399906] HW.GFX.GMA.Registers.Read: 0x00008a40 <- 0x000c5108:PCH_GMBUS2 [111.406672] HW.GFX.GMA.Registers.Read: 0x1a623090 <- 0x000c510c:PCH_GMBUS3 [111.413439] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.421354] HW.GFX.GMA.Registers.Read: 0x00008a44 <- 0x000c5108:PCH_GMBUS2 [111.428120] HW.GFX.GMA.Registers.Read: 0xb0684027 <- 0x000c510c:PCH_GMBUS3 [111.434888] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.442804] HW.GFX.GMA.Registers.Read: 0x00008a48 <- 0x000c5108:PCH_GMBUS2 [111.449568] HW.GFX.GMA.Registers.Read: 0x0fb10036 <- 0x000c510c:PCH_GMBUS3 [111.456335] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.464251] HW.GFX.GMA.Registers.Read: 0x00008a4c <- 0x000c5108:PCH_GMBUS2 [111.471018] HW.GFX.GMA.Registers.Read: 0x1c000011 <- 0x000c510c:PCH_GMBUS3 [111.477784] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.485700] HW.GFX.GMA.Registers.Read: 0x00008a50 <- 0x000c5108:PCH_GMBUS2 [111.492464] HW.GFX.GMA.Registers.Read: 0xff000000 <- 0x000c510c:PCH_GMBUS3 [111.499233] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.507148] HW.GFX.GMA.Registers.Read: 0x00008a54 <- 0x000c5108:PCH_GMBUS2 [111.513913] HW.GFX.GMA.Registers.Read: 0x35344700 <- 0x000c510c:PCH_GMBUS3 [111.520680] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.528596] HW.GFX.GMA.Registers.Read: 0x00008a58 <- 0x000c5108:PCH_GMBUS2 [111.535362] HW.GFX.GMA.Registers.Read: 0x38394833 <- 0x000c510c:PCH_GMBUS3 [111.542130] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.550045] HW.GFX.GMA.Registers.Read: 0x00008a5c <- 0x000c5108:PCH_GMBUS2 [111.556809] HW.GFX.GMA.Registers.Read: 0x3638314b <- 0x000c510c:PCH_GMBUS3 [111.563577] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.571493] HW.GFX.GMA.Registers.Read: 0x00008a60 <- 0x000c5108:PCH_GMBUS2 [111.578257] HW.GFX.GMA.Registers.Read: 0x00000a4c <- 0x000c510c:PCH_GMBUS3 [111.585025] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.592941] HW.GFX.GMA.Registers.Read: 0x00008a64 <- 0x000c5108:PCH_GMBUS2 [111.599707] HW.GFX.GMA.Registers.Read: 0x4400fc00 <- 0x000c510c:PCH_GMBUS3 [111.606475] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.614389] HW.GFX.GMA.Registers.Read: 0x00008a68 <- 0x000c5108:PCH_GMBUS2 [111.621154] HW.GFX.GMA.Registers.Read: 0x204c4c45 <- 0x000c510c:PCH_GMBUS3 [111.627921] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.635839] HW.GFX.GMA.Registers.Read: 0x00008a6c <- 0x000c5108:PCH_GMBUS2 [111.642603] HW.GFX.GMA.Registers.Read: 0x39303032 <- 0x000c510c:PCH_GMBUS3 [111.649369] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.657285] HW.GFX.GMA.Registers.Read: 0x00008a70 <- 0x000c5108:PCH_GMBUS2 [111.664052] HW.GFX.GMA.Registers.Read: 0x20200a57 <- 0x000c510c:PCH_GMBUS3 [111.670818] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.678734] HW.GFX.GMA.Registers.Read: 0x00008a74 <- 0x000c5108:PCH_GMBUS2 [111.685501] HW.GFX.GMA.Registers.Read: 0xfd000000 <- 0x000c510c:PCH_GMBUS3 [111.692267] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.700183] HW.GFX.GMA.Registers.Read: 0x00008a78 <- 0x000c5108:PCH_GMBUS2 [111.706949] HW.GFX.GMA.Registers.Read: 0x1e4b3800 <- 0x000c510c:PCH_GMBUS3 [111.713715] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.721631] HW.GFX.GMA.Registers.Read: 0x00008a7c <- 0x000c5108:PCH_GMBUS2 [111.728395] HW.GFX.GMA.Registers.Read: 0x0a001053 <- 0x000c510c:PCH_GMBUS3 [111.735163] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.743079] HW.GFX.GMA.Registers.Read: 0x0000ca00 <- 0x000c5108:PCH_GMBUS2 [111.749844] HW.GFX.GMA.Registers.Read: 0x20202020 <- 0x000c510c:PCH_GMBUS3 [111.756611] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.764527] HW.GFX.GMA.Registers.Read: 0x0000ca00 <- 0x000c5108:PCH_GMBUS2 [111.771293] HW.GFX.GMA.Registers.Read: 0x40002020 <- 0x000c510c:PCH_GMBUS3 [111.778060] HW.GFX.GMA.Registers.Wait: 0x00004000 <- 0x00004000 & 0x000c5108:PCH_GMBUS2 [111.785968] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1 [111.792735] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 [111.800644] HW.GFX.GMA.I2C.Release_GMBUS [111.804371] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 [111.811143] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 [111.817916] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D [111.824783] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [111.832158] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D [111.839539] EDID+0x0000: 00 ff ff ff ff ff ff 00 10 ac 42 40 4c 36 38 31 [111.846312] EDID+0x0010: 22 13 01 03 80 2b 1b 78 2e b7 05 a7 54 38 ad 26 [111.853084] EDID+0x0020: 0e 50 54 bf ef 80 71 4f 81 80 b3 00 95 00 81 c0 [111.859859] EDID+0x0030: 81 00 01 01 01 01 21 39 90 30 62 1a 27 40 68 b0 [111.866632] EDID+0x0040: 36 00 b1 0f 11 00 00 1c 00 00 00 ff 00 47 34 35 [111.873406] EDID+0x0050: 33 48 39 38 4b 31 38 36 4c 0a 00 00 00 fc 00 44 [111.880179] EDID+0x0060: 45 4c 4c 20 32 30 30 39 57 0a 20 20 00 00 00 fd [111.886950] EDID+0x0070: 00 38 4b 1e 53 10 00 0a 20 20 20 20 20 20 00 40 [111.893724] HW.GFX.GMA.Display_Probing.Read_EDID [111.898153] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [111.903189] PD is 2 [111.905100] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [111.912481] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [111.920035] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [111.927416] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [111.934885] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [111.941918] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [111.948951] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [111.955812] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [111.963366] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [111.970921] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [111.979604] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [111.987593] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [111.992630] PD is 5 [111.994541] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [112.001922] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [112.009475] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [112.016856] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [112.024325] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [112.031358] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [112.038392] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER [112.045252] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [112.052806] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [112.060362] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404: [112.069044] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [112.074429] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.081461] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [112.088757] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [112.094747] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.101780] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [112.108816] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [112.116977] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.124010] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [112.129395] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.136429] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [112.143723] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [112.149713] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.156748] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [112.163781] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [112.171944] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.178978] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [112.184361] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.191396] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [112.198690] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [112.204681] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.211714] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [112.218748] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [112.226912] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.233945] HW.GFX.GMA.Display_Probing.Read_EDID [112.238374] HW.GFX.GMA.I2C.I2C_Read [112.241673] HW.GFX.GMA.I2C.Init_GMBUS [112.245146] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D [112.251838] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [112.259213] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D [112.266594] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 [112.274511] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 [112.281270] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0 [112.288042] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 [112.294816] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 [112.301589] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 [112.308363] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [112.316278] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 [112.323037] HW.GFX.GMA.I2C.Release_GMBUS [112.326771] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 [112.333545] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 [112.340317] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D [112.347184] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [112.354558] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D [112.362113] CONFIG => [112.364198] (Primary => [112.366803] (Port => HDMI1 , [112.370102] Framebuffer => [112.373140] (Width => 1680, [112.376788] Height => 1050, [112.380436] Start_X => 0, [112.383821] Start_Y => 0, [112.387209] Stride => 1680, [112.390856] V_Stride => 1050, [112.394502] Tiling => Linear , [112.398409] Rotation => No_Rotation, [112.402664] Offset => 0x00000000, [112.406574] BPC => 8), [112.409785] Mode => [112.412217] (Dotclock => 146250000, [112.417079] H_Visible => 1680, [112.421509] H_Sync_Begin => 1784, [112.425937] H_Sync_End => 1960, [112.430365] H_Total => 2240, [112.434793] V_Visible => 1050, [112.439223] V_Sync_Begin => 1053, [112.443651] V_Sync_End => 1059, [112.448080] V_Total => 1089, [112.452509] H_Sync_Active_High => False, [112.457023] V_Sync_Active_High => True, [112.461452] BPC => 5)), [112.465795] Secondary => [112.468400] (Port => Disabled, [112.471700] Framebuffer => [112.474739] (Width => 1, [112.478124] Height => 1, [112.481511] Start_X => 0, [112.484897] Start_Y => 0, [112.488285] Stride => 1, [112.491672] V_Stride => 1, [112.495058] Tiling => Linear , [112.498965] Rotation => No_Rotation, [112.503220] Offset => 0x00000000, [112.507128] BPC => 8), [112.510341] Mode => [112.512773] (Dotclock => 19200000, [112.517549] H_Visible => 1, [112.521715] H_Sync_Begin => 1, [112.525885] H_Sync_End => 1, [112.530052] H_Total => 1, [112.534220] V_Visible => 1, [112.538388] V_Sync_Begin => 1, [112.542556] V_Sync_End => 1, [112.546724] V_Total => 1, [112.550892] H_Sync_Active_High => False, [112.555408] V_Sync_Active_High => False, [112.559923] BPC => 5)), [112.564266] Tertiary => [112.566869] (Port => Disabled, [112.570170] Framebuffer => [112.573209] (Width => 1, [112.576595] Height => 1, [112.579982] Start_X => 0, [112.583369] Start_Y => 0, [112.586755] Stride => 1, [112.590141] V_Stride => 1, [112.593529] Tiling => Linear , [112.597437] Rotation => No_Rotation, [112.601691] Offset => 0x00000000, [112.605600] BPC => 8), [112.608811] Mode => [112.611244] (Dotclock => 19200000, [112.616019] H_Visible => 1, [112.620186] H_Sync_Begin => 1, [112.624354] H_Sync_End => 1, [112.628522] H_Total => 1, [112.632691] V_Visible => 1, [112.636860] V_Sync_Begin => 1, [112.641028] V_Sync_End => 1, [112.645196] V_Total => 1, [112.649365] H_Sync_Active_High => False, [112.653879] V_Sync_Active_High => False, [112.658395] BPC => 5))); [113.471029] Success [113.473113] Update_Power [113.475456] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [113.480494] PD is 2 [113.482403] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [113.489785] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.497339] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [113.504721] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [113.512188] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [113.519221] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [113.526255] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [113.533116] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.540671] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [113.548226] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [113.556908] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [113.564898] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On [113.569933] PD is 5 [113.571844] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [113.579225] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.586779] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [113.594161] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [113.601629] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [113.608663] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [113.615696] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER [113.622556] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.630111] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [113.637664] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404: [113.646522] Trying to enable port HDMI1 [113.650604] Enable_Output [113.653035] Success - Fill_Port_Config [113.656595] Success - Validate_Config [113.660069] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting [113.665538] HW.GFX.GMA.PLLs.Alloc [113.668666] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1 [113.674395] HW.GFX.GMA.Registers.Read: 0x00000847 <- 0x0006c058:DPLL_CTRL1 [113.681169] HW.GFX.GMA.Registers.Write: 0x00000847 -> 0x0006c058:DPLL_CTRL1 [113.687942] HW.GFX.GMA.Registers.Write: 0x80a0016d -> 0x0006c040:DPLL1_CFGR1 [113.694803] HW.GFX.GMA.Registers.Write: 0x000003a5 -> 0x0006c044:DPLL1_CFGR2 [113.701662] HW.GFX.GMA.Registers.Read: 0x00000847 <- 0x0006c058:DPLL_CTRL1 [113.708436] HW.GFX.GMA.Registers.Read: 0x80a0016d <- 0x0006c040:DPLL1_CFGR1 [113.715295] HW.GFX.GMA.Registers.Read: 0x000003a5 <- 0x0006c044:DPLL1_CFGR2 [113.722156] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL [113.728930] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS [113.736918] Success - PLLs Alloc [113.739963] HW.GFX.GMA.Connectors.Pre_On [113.743691] HW.GFX.GMA.Connectors.DDI.Pre_On [113.747773] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2 [113.753503] HW.GFX.GMA.Registers.Read: 0x00af8018 <- 0x0006c05c:DPLL_CTRL2 [113.760277] HW.GFX.GMA.Registers.Write: 0x00ae8018 -> 0x0006c05c:DPLL_CTRL2 [113.767050] Success - Connectors Pre_On [113.770697] HW.GFX.GMA.Pipe_Setup.On [113.774083] HW.GFX.GMA.Transcoder.Setup [113.777731] HW.GFX.GMA.Registers.Write: 0x40000000 -> 0x00046140:TRANSA_CLK_SEL [113.784851] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x00060000:HTOTAL_A [113.791449] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x00060004:HBLANK_A [113.798049] HW.GFX.GMA.Registers.Write: 0x07a706f7 -> 0x00060008:HSYNC_A [113.804562] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x0006000c:VTOTAL_A [113.811162] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x00060010:VBLANK_A [113.817761] HW.GFX.GMA.Registers.Write: 0x0422041c -> 0x00060014:VSYNC_A [113.824274] HW.GFX.GMA.Pipe_Setup.Setup_FB [113.828182] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [113.834869] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [113.841553] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A [113.848327] HW.GFX.GMA.Pipe_Setup.Setup_Display [113.852668] HW.GFX.GMA.Registers.Write: 0x009f0008 -> 0x0007027c:PLANE_BUF_CFG_1_A [113.860051] HW.GFX.GMA.Registers.Write: 0x80008098 -> 0x00070240:PLANE_WM_1_A_0 [113.867170] HW.GFX.GMA.Registers.Write: 0x00070000 -> 0x0007017c:CUR_BUF_CFG_A [113.874205] HW.GFX.GMA.Registers.Write: 0x80008008 -> 0x00070140:CUR_WM_A_0 [113.880977] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane [113.885665] HW.GFX.GMA.Registers.Write: 0x84002000 -> 0x00070180:DSPACNTR [113.892265] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF [113.899125] HW.GFX.GMA.Registers.Write: 0x0419068f -> 0x00070190:PLANE_SIZE_1_A [113.906246] HW.GFX.GMA.Registers.Write: 0x00000069 -> 0x00070188:DSPASTRIDE [113.913019] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007018c:PLANE_POS_1_A [113.920053] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF [113.926652] HW.GFX.GMA.Registers.Write: 0x068f0419 -> 0x0006001c:PIPEASRC [113.933252] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070030:PIPEAMISC [113.939938] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A [113.946278] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A [113.953137] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A [113.959996] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A [113.967031] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A [113.973370] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A [113.980231] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A [113.987091] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A [113.994123] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [114.000809] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [114.007495] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A [114.014268] HW.GFX.GMA.Registers.Write: 0x91020000 -> 0x00060400:PIPEA_DDI_FUNC_CTL [114.021738] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00070008:PIPEACONF [114.028423] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00070008:PIPEACONF [114.035109] HW.GFX.GMA.Connectors.Post_On [114.038931] HW.GFX.GMA.Connectors.DDI.Post_On [114.043099] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_B [114.049091] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064100:DDI_BUF_CTL_B [114.056124] HW.GFX.GMA.Registers.Write: 0x80000080 -> 0x00064100:DDI_BUF_CTL_B [114.063758] Enabled port HDMI1

3 3

p8h61-m_pro PS/2
by Simon Newton 10 May '19

10 May '19

Been playing with this board and have ran into a weird problem. I cant get a PS2 keyboard to work with this motherboard under coreboot. Ive used direct PS2 keyboard connections, Ive used PS2 splitters and PS2 KVMs and none work. PS2 init as an option is present and selected in the coreboot config (CONFIG_DRIVERS_PS2_KEYBOARD=y) Im using current master of coreboot, and have tried the keyboard via the PS2 port in multiple permutations of direct connect, with splitter and also via KVM. None of which work. Ive tried with different payloads including coreinfo and seabios, none of which work. This is proving to be a challenge as im trying to make this board the first port of a desktop board to heads firmware. Its worked well so far, the only sticking point is the PS2 keyboard functionality. USB keyboard is not really an option when using heads+qubes. I cant find any refernece to ps2 or 8042 in the serial console, until the SeaBIOS payload takes over. That displays the following; Found 1 ltp ports Found 1 serial ports Got ps2 nak (status=51) Does anyone have any thoughts or pointers? Cheers

2 4

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 10 May '19

10 May '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 7 new defect(s) introduced to coreboot found with Coverity Scan. 5 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 7 of 7 defect(s) ** CID 1401344: (OVERRUN) ________________________________________________________________________________________________________ *** CID 1401344: (OVERRUN) /src/mainboard/intel/kunimitsu/romstage.c: 34 in mainboard_memory_init_params() 28 29 void mainboard_memory_init_params(struct romstage_params *params, 30 MEMORY_INIT_UPD *memory_params) 31 { 32 spd_memory_init_params(memory_params); 33 mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); >>> CID 1401344: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15. 34 mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); 35 mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); 36 mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); 37 memory_params->MemorySpdDataLen = SPD_LEN; 38 memory_params->DqPinsInterleaved = FALSE; /src/mainboard/intel/saddlebrook/romstage.c: 67 in mainboard_memory_init_params() 61 /* 62 * Configure the DQ/DQS settings if required. In general the settings 63 * should be set in the FSP flash image and should not need to be 64 * changed. 65 */ 66 mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); >>> CID 1401344: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15. 67 mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); 68 mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); 69 mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); 70 71 /* update spd length*/ 72 memory_params->MemorySpdDataLen = blk.len; 73 memory_params->DqPinsInterleaved = TRUE; ** CID 1401343: Memory - corruptions (OVERRUN) /src/mainboard/google/glados/variants/lars/variant.c: 63 in variant_memory_init_params() ________________________________________________________________________________________________________ *** CID 1401343: Memory - corruptions (OVERRUN) /src/mainboard/google/glados/variants/lars/variant.c: 63 in variant_memory_init_params() 57 /* Override Rcomp Target assignment for specific SKU(s) */ 58 if (spd_index == K4E6E304EB_MEM_ID) 59 targeted_rcomp = StrengthendRcompTarget; 60 61 memcpy(params->DqByteMapCh0, dq_map, 62 sizeof(params->DqByteMapCh0) * 2); >>> CID 1401343: Memory - corruptions (OVERRUN) >>> Overrunning array "params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 63 memcpy(params->DqsMapCpu2DramCh0, dqs_map, 64 sizeof(params->DqsMapCpu2DramCh0) * 2); 65 memcpy(params->RcompResistor, RcompResistor, 66 sizeof(params->RcompResistor)); 67 memcpy(params->RcompTarget, targeted_rcomp, 68 sizeof(params->RcompTarget)); ** CID 1401342: (BUFFER_SIZE) /src/mainboard/google/glados/variants/caroline/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/caroline/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/glados/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/glados/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/chell/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/chell/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/cave/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/cave/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/lars/variant.c: 61 in variant_memory_init_params() /src/mainboard/google/glados/variants/lars/variant.c: 63 in variant_memory_init_params() /src/mainboard/google/glados/variants/asuka/variant.c: 42 in variant_memory_init_params() /src/mainboard/google/glados/variants/asuka/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/sentry/variant.c: 54 in variant_memory_init_params() /src/mainboard/google/glados/variants/sentry/variant.c: 56 in variant_memory_init_params() ________________________________________________________________________________________________________ *** CID 1401342: (BUFFER_SIZE) /src/mainboard/google/glados/variants/caroline/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "memory_params->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/caroline/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "memory_params->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/glados/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "memory_params->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/glados/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "memory_params->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/chell/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "memory_params->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/chell/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "memory_params->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/cave/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "memory_params->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/cave/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "memory_params->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/lars/variant.c: 61 in variant_memory_init_params() 55 const u16 *targeted_rcomp = RcompTarget; 56 57 /* Override Rcomp Target assignment for specific SKU(s) */ 58 if (spd_index == K4E6E304EB_MEM_ID) 59 targeted_rcomp = StrengthendRcompTarget; 60 >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "params->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 61 memcpy(params->DqByteMapCh0, dq_map, 62 sizeof(params->DqByteMapCh0) * 2); 63 memcpy(params->DqsMapCpu2DramCh0, dqs_map, 64 sizeof(params->DqsMapCpu2DramCh0) * 2); 65 memcpy(params->RcompResistor, RcompResistor, 66 sizeof(params->RcompResistor)); /src/mainboard/google/glados/variants/lars/variant.c: 63 in variant_memory_init_params() 57 /* Override Rcomp Target assignment for specific SKU(s) */ 58 if (spd_index == K4E6E304EB_MEM_ID) 59 targeted_rcomp = StrengthendRcompTarget; 60 61 memcpy(params->DqByteMapCh0, dq_map, 62 sizeof(params->DqByteMapCh0) * 2); >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "params->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 63 memcpy(params->DqsMapCpu2DramCh0, dqs_map, 64 sizeof(params->DqsMapCpu2DramCh0) * 2); 65 memcpy(params->RcompResistor, RcompResistor, 66 sizeof(params->RcompResistor)); 67 memcpy(params->RcompTarget, targeted_rcomp, 68 sizeof(params->RcompTarget)); /src/mainboard/google/glados/variants/asuka/variant.c: 42 in variant_memory_init_params() 36 /* Rcomp resistor */ 37 const u16 RcompResistor[3] = { 200, 81, 162 }; 38 39 /* Rcomp target */ 40 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 41 >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "memory_params->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 42 memcpy(memory_params->DqByteMapCh0, dq_map, 43 sizeof(memory_params->DqByteMapCh0) * 2); 44 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 45 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 46 memcpy(memory_params->RcompResistor, RcompResistor, 47 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/asuka/variant.c: 44 in variant_memory_init_params() 38 39 /* Rcomp target */ 40 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 41 42 memcpy(memory_params->DqByteMapCh0, dq_map, 43 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "memory_params->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 44 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 45 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 46 memcpy(memory_params->RcompResistor, RcompResistor, 47 sizeof(memory_params->RcompResistor)); 48 memcpy(memory_params->RcompTarget, RcompTarget, 49 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/sentry/variant.c: 54 in variant_memory_init_params() 48 const u16 *targeted_rcomp = RcompTarget; 49 50 /* Override Rcomp Target assignment for specific SKU(s) */ 51 if (spd_index == K4E6E304EE_MEM_ID) 52 targeted_rcomp = StrengthendRcompTarget; 53 >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 12 byte destination string "memory_params->DqByteMapCh0" by writing the maximum 24 bytes from "dq_map". 54 memcpy(memory_params->DqByteMapCh0, dq_map, 55 sizeof(memory_params->DqByteMapCh0) * 2); 56 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 57 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 58 memcpy(memory_params->RcompResistor, RcompResistor, 59 sizeof(memory_params->RcompResistor)); 60 memcpy(memory_params->RcompTarget, targeted_rcomp, 61 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/sentry/variant.c: 56 in variant_memory_init_params() 50 /* Override Rcomp Target assignment for specific SKU(s) */ 51 if (spd_index == K4E6E304EE_MEM_ID) 52 targeted_rcomp = StrengthendRcompTarget; 53 54 memcpy(memory_params->DqByteMapCh0, dq_map, 55 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401342: (BUFFER_SIZE) >>> You might overrun the 8 byte destination string "memory_params->DqsMapCpu2DramCh0" by writing the maximum 16 bytes from "dqs_map". 56 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 57 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 58 memcpy(memory_params->RcompResistor, RcompResistor, 59 sizeof(memory_params->RcompResistor)); 60 memcpy(memory_params->RcompTarget, targeted_rcomp, 61 sizeof(memory_params->RcompTarget)); ** CID 1401341: (OVERRUN) ________________________________________________________________________________________________________ *** CID 1401341: (OVERRUN) /src/mainboard/intel/kunimitsu/romstage.c: 33 in mainboard_memory_init_params() 27 } 28 29 void mainboard_memory_init_params(struct romstage_params *params, 30 MEMORY_INIT_UPD *memory_params) 31 { 32 spd_memory_init_params(memory_params); >>> CID 1401341: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23. 33 mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); 34 mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); 35 mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); 36 mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); 37 memory_params->MemorySpdDataLen = SPD_LEN; 38 memory_params->DqPinsInterleaved = FALSE; /src/mainboard/intel/saddlebrook/romstage.c: 66 in mainboard_memory_init_params() 60 61 /* 62 * Configure the DQ/DQS settings if required. In general the settings 63 * should be set in the FSP flash image and should not need to be 64 * changed. 65 */ >>> CID 1401341: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23. 66 mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); 67 mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); 68 mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); 69 mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); 70 71 /* update spd length*/ 72 memory_params->MemorySpdDataLen = blk.len; 73 memory_params->DqPinsInterleaved = TRUE; ** CID 1401340: Memory - corruptions (OVERRUN) /src/mainboard/google/glados/variants/lars/variant.c: 61 in variant_memory_init_params() ________________________________________________________________________________________________________ *** CID 1401340: Memory - corruptions (OVERRUN) /src/mainboard/google/glados/variants/lars/variant.c: 61 in variant_memory_init_params() 55 const u16 *targeted_rcomp = RcompTarget; 56 57 /* Override Rcomp Target assignment for specific SKU(s) */ 58 if (spd_index == K4E6E304EB_MEM_ID) 59 targeted_rcomp = StrengthendRcompTarget; 60 >>> CID 1401340: Memory - corruptions (OVERRUN) >>> Overrunning array "params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 61 memcpy(params->DqByteMapCh0, dq_map, 62 sizeof(params->DqByteMapCh0) * 2); 63 memcpy(params->DqsMapCpu2DramCh0, dqs_map, 64 sizeof(params->DqsMapCpu2DramCh0) * 2); 65 memcpy(params->RcompResistor, RcompResistor, 66 sizeof(params->RcompResistor)); ** CID 1401339: (OVERRUN) /src/mainboard/google/glados/variants/caroline/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/glados/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/chell/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/cave/variant.c: 46 in variant_memory_init_params() /src/mainboard/google/glados/variants/asuka/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/sentry/variant.c: 56 in variant_memory_init_params() ________________________________________________________________________________________________________ *** CID 1401339: (OVERRUN) /src/mainboard/google/glados/variants/caroline/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401339: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/glados/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401339: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/chell/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401339: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/cave/variant.c: 46 in variant_memory_init_params() 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401339: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); 50 memcpy(memory_params->RcompTarget, RcompTarget, 51 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/asuka/variant.c: 44 in variant_memory_init_params() 38 39 /* Rcomp target */ 40 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 41 42 memcpy(memory_params->DqByteMapCh0, dq_map, 43 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401339: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 44 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 45 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 46 memcpy(memory_params->RcompResistor, RcompResistor, 47 sizeof(memory_params->RcompResistor)); 48 memcpy(memory_params->RcompTarget, RcompTarget, 49 sizeof(memory_params->RcompTarget)); /src/mainboard/google/glados/variants/sentry/variant.c: 56 in variant_memory_init_params() 50 /* Override Rcomp Target assignment for specific SKU(s) */ 51 if (spd_index == K4E6E304EE_MEM_ID) 52 targeted_rcomp = StrengthendRcompTarget; 53 54 memcpy(memory_params->DqByteMapCh0, dq_map, 55 sizeof(memory_params->DqByteMapCh0) * 2); >>> CID 1401339: (OVERRUN) >>> Overrunning array "memory_params->DqsMapCpu2DramCh0" of 8 bytes by passing it to a function which accesses it at byte offset 15 using argument "16UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 56 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 57 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 58 memcpy(memory_params->RcompResistor, RcompResistor, 59 sizeof(memory_params->RcompResistor)); 60 memcpy(memory_params->RcompTarget, targeted_rcomp, 61 sizeof(memory_params->RcompTarget)); ** CID 1401338: (OVERRUN) /src/mainboard/google/glados/variants/caroline/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/glados/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/chell/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/cave/variant.c: 44 in variant_memory_init_params() /src/mainboard/google/glados/variants/asuka/variant.c: 42 in variant_memory_init_params() /src/mainboard/google/glados/variants/sentry/variant.c: 54 in variant_memory_init_params() ________________________________________________________________________________________________________ *** CID 1401338: (OVERRUN) /src/mainboard/google/glados/variants/caroline/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401338: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/glados/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401338: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/chell/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401338: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/cave/variant.c: 44 in variant_memory_init_params() 38 /* Rcomp resistor */ 39 const u16 RcompResistor[3] = { 200, 81, 162 }; 40 41 /* Rcomp target */ 42 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 43 >>> CID 1401338: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 44 memcpy(memory_params->DqByteMapCh0, dq_map, 45 sizeof(memory_params->DqByteMapCh0) * 2); 46 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 47 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 48 memcpy(memory_params->RcompResistor, RcompResistor, 49 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/asuka/variant.c: 42 in variant_memory_init_params() 36 /* Rcomp resistor */ 37 const u16 RcompResistor[3] = { 200, 81, 162 }; 38 39 /* Rcomp target */ 40 const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; 41 >>> CID 1401338: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 42 memcpy(memory_params->DqByteMapCh0, dq_map, 43 sizeof(memory_params->DqByteMapCh0) * 2); 44 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 45 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 46 memcpy(memory_params->RcompResistor, RcompResistor, 47 sizeof(memory_params->RcompResistor)); /src/mainboard/google/glados/variants/sentry/variant.c: 54 in variant_memory_init_params() 48 const u16 *targeted_rcomp = RcompTarget; 49 50 /* Override Rcomp Target assignment for specific SKU(s) */ 51 if (spd_index == K4E6E304EE_MEM_ID) 52 targeted_rcomp = StrengthendRcompTarget; 53 >>> CID 1401338: (OVERRUN) >>> Overrunning array "memory_params->DqByteMapCh0" of 12 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 54 memcpy(memory_params->DqByteMapCh0, dq_map, 55 sizeof(memory_params->DqByteMapCh0) * 2); 56 memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, 57 sizeof(memory_params->DqsMapCpu2DramCh0) * 2); 58 memcpy(memory_params->RcompResistor, RcompResistor, 59 sizeof(memory_params->RcompResistor)); 60 memcpy(memory_params->RcompTarget, targeted_rcomp, 61 sizeof(memory_params->RcompTarget)); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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G505s: Discrepancies b/w harvested vgabios VS patches
by Matt B 10 May '19

10 May '19

Greetings, Because it's always good to check, I extracted the discrete GPU's vgabios rom from my G505s following method 3 ("Retrieval via Linux kernel") listed here: [1] I have no dGPU, and I assume that it was discovered that this produces a clean (correct) iGPU rom blob. Not that I wrote a '1' to the file first to enable reading, as noted here: [2] I compared the files using tkdiff in hexdump format. See attachments for the files. Comparing the file that I extracted and pci1002,990b.rom from [3] (obtained via "./atombios.sh") they are definitely very similar, but there are many spots with discrepancies. The diff output is at the end of this email. Along the way I had to take the file from the patch and turn it back into a binary and then hexdump it with the same options to make sure they had the same formatting. It was noted in [4] that there were some differences between the vgabios roms used for integrated GPUs in laptops with and without discrete ones, specifically with regard to supply voltage. Can anyone confirm that the version supplied via the patch is the one from laptops with a discrete GPU, and that what I have matches what would be expected for a dGPU-less laptop? Is there a hash of the rom itself somewhere to point to? Sincerely, -Matt Attachments: extracted_vgabios.rom => the rom I extracted myself extracted_vgabios.rom.txt => the result of "hexdump -C extracted_vgabios.rom" pci1002,990b.rom.txt => the rom from the patch (received along with 6663 and 6665) pci1002,990b.rom.txt.rom => the result of "cat pci1002,990b.rom.txt | xxd -r" pci1002,990b.rom.txt.rom.txt => the result of hexdumping pci1002,990b.rom.txt.rom as above Checksums: 0c0543a28677baa75c49616e5fe326a413f779e77764f8a6dd13c798d3b076ee extracted_vgabios.rom 0515b8cbf184fbfba13ae48d70b1c5ae05405dd709e0eef2291c6d8a4a587287 pci1002,6663.rom.txt 416c748e5ad538593003e47a484067d7cbb509ddff7de079f5603b6d135898bf pci1002,6665.rom.txt c35f469b56c41385b0196c0c9df6599ef9e81e32078da2dd3cf81760c9bd3365 pci1002,990b.rom.txt References: [1] https://coreboot.coreboot.narkive.com/zEkIcuSS/ultimate-vgabios-extraction-… [2] https://www.coreboot.org/VGA_support [3] http://dangerousprototypes.com/docs/Lenovo_G505S_hacking [4] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/GZNW… Diff results: $ diff extracted_vgabios.rom.txt pci1002,990b.rom.txt.rom.txt 3c3 < 00000020 4d 49 00 00 00 00 00 00 00 00 00 00 00 00 00 04 |MI..............| --- > 00000020 4d d3 00 00 00 00 00 00 00 00 00 00 00 00 00 04 |M...............| 27c27 < 000001a0 34 03 08 00 00 30 02 10 0b 99 b4 01 a4 a5 4a a6 |4....0........J.| --- > 000001a0 34 03 08 00 00 40 02 10 0b 99 b4 01 a4 a5 4a a6 |4....@ ........J.| 2735,2736c2735,2736 < 0000aae0 00 00 00 00 00 00 d1 00 01 03 12 1b 56 05 70 00 |............V.p.| < 0000aaf0 00 03 0e 00 20 00 20 00 02 00 04 00 59 01 c2 00 |.... . .....Y...| --- > 0000aae0 00 00 00 00 00 00 d1 00 01 03 41 1c 56 05 a0 00 |..........A.V...| > 0000aaf0 00 03 16 00 30 00 20 00 02 00 05 00 58 01 c2 00 |....0. .....X...| 2841c2841 < 0000b200 06 00 00 00 00 00 00 00 4c 00 4e 00 03 00 74 01 |........L.N...t.| --- > 0000b200 06 00 00 00 00 00 00 00 4a 00 4c 00 03 00 74 01 |........J.L...t.| 2848,2850c2848,2850 < 0000b290 00 00 72 00 32 89 00 00 01 00 4e 00 56 d0 00 00 |..r.2.....N.V...| < 0000b2a0 02 00 48 00 40 19 01 00 03 00 42 00 40 19 01 00 |..H.@.....B.@ ...| < 0000b2b0 03 00 42 00 8b 1e 00 00 70 11 01 00 00 00 00 00 |..B.....p.......| --- > 0000b290 00 00 70 00 32 89 00 00 01 00 4c 00 56 d0 00 00 |..p.2.....L.V...| > 0000b2a0 02 00 46 00 40 19 01 00 03 00 40 00 40 19 01 00 |..F.@ .....@.@...| > 0000b2b0 03 00 40 00 8b 1e 00 00 70 11 01 00 00 00 00 00 |..@.....p.......| 2855c2855 < 0000b300 80 38 01 00 80 38 01 00 14 82 00 00 50 00 76 00 |.8...8......P.v.| --- > 0000b300 80 38 01 00 80 38 01 00 14 82 00 00 4e 00 74 00 |.8...8......N.t.|

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security@ email address as a point of contact for coreboot security issues
by Patrick Georgi 08 May '19

08 May '19

Hi everybody, I think we never officially announced it: there's an email alias to post security issues to, at security(a)coreboot.org. Right now, it's maintained by Stefan and me, and when issues appear there we will share them with the affected maintainers for resolution. Technically it's a mailing list (that a few folks tried to subscribe to), but that's mostly for convenience: it's not meant to be open for all due to the sensitive nature of things discussed there. When dealing with an issue through that channel, we will make sure that there's disclosure afterwards - maybe delayed a bit to roll out fixes to users first, but otherwise as soon as possible. I won't commit to any timeline here simply because we lack experience with that (so far there hasn't been a report through that channel). I also created a change to the homepage at https://review.coreboot.org/c/homepage/+/32689 to make that point of contact more visible. Let's develop coreboot in a way that we won't need this alias very often :-) Regards, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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How to connect with my mentors for GSoC project
by Asami Doi 08 May '19

08 May '19

Hello, I will work on the project "Adding QEMU/AArch64 Support to Coreboot" as a GSoC student. I'm excited to work with you and my mentors, rrangel and Edward O'Callaghan. Thank you in advance. I have a question about how to work on the project. *Q. How can I communicate with my mentors?* Is it ok to communicate with mentors via this mailing list? Or, is it better to do it via video chat or direct email to avoid too many emails for other members? Thank you, Asami

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 07 May '19

07 May '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 6 new defect(s) introduced to coreboot found with Coverity Scan. 16 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 6 of 6 defect(s) ** CID 1401305: Memory - illegal accesses (BUFFER_SIZE_WARNING) /src/soc/qualcomm/common/qclib.c: 44 in qclib_add_if_table_entry() ________________________________________________________________________________________________________ *** CID 1401305: Memory - illegal accesses (BUFFER_SIZE_WARNING) /src/soc/qualcomm/common/qclib.c: 44 in qclib_add_if_table_entry() 38 void qclib_add_if_table_entry(const char *name, void *base, 39 uint32_t size, uint32_t attrs) 40 { 41 struct qclib_cb_if_table_entry *te = 42 &qclib_cb_if_table.te[qclib_cb_if_table.num_entries++]; 43 assert(qclib_cb_if_table.num_entries <= qclib_cb_if_table.max_entries); >>> CID 1401305: Memory - illegal accesses (BUFFER_SIZE_WARNING) >>> Calling strncpy with a maximum size argument of 24 bytes on destination array "te->name" of size 24 bytes might leave the destination string unterminated. 44 strncpy(te->name, name, sizeof(te->name)); 45 te->blob_address = (uintptr_t)base; 46 te->size = size; 47 te->blob_attributes = attrs; 48 } 49 ** CID 1401304: Control flow issues (NO_EFFECT) /3rdparty/vboot/firmware/2lib/2misc.c: 131 in vb2_init_context() ________________________________________________________________________________________________________ *** CID 1401304: Control flow issues (NO_EFFECT) /3rdparty/vboot/firmware/2lib/2misc.c: 131 in vb2_init_context() 125 * initialized. */ 126 if (ctx->workbuf_used) { 127 if (sd->magic != VB2_SHARED_DATA_MAGIC) 128 return VB2_ERROR_SHARED_DATA_MAGIC; 129 130 if (sd->struct_version_major != VB2_SHARED_DATA_VERSION_MAJOR || >>> CID 1401304: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "sd->struct_version_minor < 0". 131 sd->struct_version_minor < VB2_SHARED_DATA_VERSION_MINOR) 132 return VB2_ERROR_SHARED_DATA_VERSION; 133 134 return VB2_SUCCESS; 135 } 136 ** CID 1381814: (BUFFER_SIZE) /src/soc/intel/cannonlake/fsp_params.c: 281 in platform_fsp_silicon_init_params_cb() /src/soc/intel/cannonlake/fsp_params.c: 283 in platform_fsp_silicon_init_params_cb() ________________________________________________________________________________________________________ *** CID 1381814: (BUFFER_SIZE) /src/soc/intel/cannonlake/fsp_params.c: 281 in platform_fsp_silicon_init_params_cb() 275 #endif 276 /* PCI Express */ 277 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { 278 if (config->PcieClkSrcUsage[i] == 0) 279 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; 280 } >>> CID 1381814: (BUFFER_SIZE) >>> You might overrun the 16 byte destination string "params->PcieClkSrcUsage" by writing the maximum 24 bytes from "config->PcieClkSrcUsage". 281 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, 282 sizeof(config->PcieClkSrcUsage)); 283 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, 284 sizeof(config->PcieClkSrcClkReq)); 285 memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, 286 sizeof(config->PcieRpLtrEnable)); /src/soc/intel/cannonlake/fsp_params.c: 283 in platform_fsp_silicon_init_params_cb() 277 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { 278 if (config->PcieClkSrcUsage[i] == 0) 279 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; 280 } 281 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, 282 sizeof(config->PcieClkSrcUsage)); >>> CID 1381814: (BUFFER_SIZE) >>> You might overrun the 16 byte destination string "params->PcieClkSrcClkReq" by writing the maximum 24 bytes from "config->PcieClkSrcClkReq". 283 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, 284 sizeof(config->PcieClkSrcClkReq)); 285 memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, 286 sizeof(config->PcieRpLtrEnable)); 287 memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, 288 sizeof(config->PcieRpHotPlug)); ** CID 1381813: Memory - corruptions (OVERRUN) /src/soc/intel/cannonlake/fsp_params.c: 281 in platform_fsp_silicon_init_params_cb() ________________________________________________________________________________________________________ *** CID 1381813: Memory - corruptions (OVERRUN) /src/soc/intel/cannonlake/fsp_params.c: 281 in platform_fsp_silicon_init_params_cb() 275 #endif 276 /* PCI Express */ 277 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { 278 if (config->PcieClkSrcUsage[i] == 0) 279 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; 280 } >>> CID 1381813: Memory - corruptions (OVERRUN) >>> Overrunning array "params->PcieClkSrcUsage" of 16 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 281 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, 282 sizeof(config->PcieClkSrcUsage)); 283 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, 284 sizeof(config->PcieClkSrcClkReq)); 285 memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, 286 sizeof(config->PcieRpLtrEnable)); ** CID 1381812: Memory - corruptions (OVERRUN) /src/soc/intel/cannonlake/fsp_params.c: 283 in platform_fsp_silicon_init_params_cb() ________________________________________________________________________________________________________ *** CID 1381812: Memory - corruptions (OVERRUN) /src/soc/intel/cannonlake/fsp_params.c: 283 in platform_fsp_silicon_init_params_cb() 277 for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { 278 if (config->PcieClkSrcUsage[i] == 0) 279 config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; 280 } 281 memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, 282 sizeof(config->PcieClkSrcUsage)); >>> CID 1381812: Memory - corruptions (OVERRUN) >>> Overrunning array "params->PcieClkSrcClkReq" of 16 bytes by passing it to a function which accesses it at byte offset 23 using argument "24UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 283 memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, 284 sizeof(config->PcieClkSrcClkReq)); 285 memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, 286 sizeof(config->PcieRpLtrEnable)); 287 memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, 288 sizeof(config->PcieRpHotPlug)); ** CID 1353342: (OVERRUN) ________________________________________________________________________________________________________ *** CID 1353342: (OVERRUN) /3rdparty/chromeec/common/pwm.c: 120 in cc_pwm_duty() 114 char *e; 115 char *raw; 116 117 if (argc < 2) { 118 ccprintf("PWM channels:\n"); 119 for (ch = 0; ch < PWM_CH_COUNT; ch++) >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "print_channel". 120 print_channel(ch, max_duty); 121 return EC_SUCCESS; 122 } 123 124 ch = strtoi(argv[1], &e, 0); 125 if (*e || ch < 0 || ch >= PWM_CH_COUNT) /3rdparty/chromeec/common/pwm.c: 148 in cc_pwm_duty() 142 return EC_ERROR_PARAM2; 143 } else if (value < 0) { 144 /* Negative = disable */ 145 pwm_enable(ch, 0); 146 } else { 147 ccprintf("Setting channel %d to %d\n", ch, value); >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "pwm_enable". 148 pwm_enable(ch, 1); 149 (max_duty == 100) ? pwm_set_duty(ch, value) : 150 pwm_set_raw_duty(ch, value); 151 } 152 } 153 /3rdparty/chromeec/common/pwm.c: 149 in cc_pwm_duty() 143 } else if (value < 0) { 144 /* Negative = disable */ 145 pwm_enable(ch, 0); 146 } else { 147 ccprintf("Setting channel %d to %d\n", ch, value); 148 pwm_enable(ch, 1); >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "pwm_set_raw_duty". 149 (max_duty == 100) ? pwm_set_duty(ch, value) : 150 pwm_set_raw_duty(ch, value); 151 } 152 } 153 154 print_channel(ch, max_duty); /3rdparty/chromeec/common/pwm.c: 154 in cc_pwm_duty() 148 pwm_enable(ch, 1); 149 (max_duty == 100) ? pwm_set_duty(ch, value) : 150 pwm_set_raw_duty(ch, value); 151 } 152 } 153 >>> CID 1353342: (OVERRUN) >>> Overrunning callee's array of size 1 by passing argument "ch" (which evaluates to 2) in call to "print_channel". 154 print_channel(ch, max_duty); 155 156 return EC_SUCCESS; 157 } 158 DECLARE_CONSOLE_COMMAND(pwmduty, cc_pwm_duty, 159 "[channel [<percent> | -1=disable] | [raw <value>]]", ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Building Coreboot Image for Opencellular
by karthikm618＠gmail.com 07 May '19

07 May '19

Hello, I'm Karthik working on Opencellular (https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wi…). I'm trying to build coreboot image for Opencellular Board. Finally, succeeded in building the image but with a WARNING message ** WARNING ** coreboot will be built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. So my question is 1. Is it okay to flash the image with above WARNING message onto the board? Help me to find a way. Thank you, in advance.

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coreboot May 2019