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Hi @ all,
is there a Coroboot for the Lenovo T410 Laptop?
Greetings
Alex Veek
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All,
After reviewing some of the comments on the ASUS KGPE-D16 being
essentially too large of a system and too expensive for many people, and
the fact that modern, blob-free systems are not really available in the
mid-range arena, Raptor Engineering would like to offer to create a
native initalization blob-free port for the ASUS KCMA-D8, which is
essentially the KGPE-D16's ATX-compatible "little brother".
We would be asking $15,000 for the port, including upstreaming to the
master coreboot tree. We already have extensive experience with these
Family 10h/15h boards, and would be able to create a port of similar
quality to the existing KGPE-D16 source in terms of both code quality
and overall functionality.
If this is something you might be interested in please let me know. We
are able to accept multiple payments from various sources for the same
project (within limits), so if this is something your local Linux groups
or similar might be interested in we should be able to keep the cost on
any one individual or organization to a reasonable level.
Thank you for your consideration,
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
http://www.raptorengineeringinc.com
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Hi John,
> It sounds to me as though the PCI id's of the graphics card for the
> upgraded CPU may be different (I could be totally wrong about that, so I
> defer to others on the list if I'm barking up the wrong tree) and your
> coreboot image may need to be updated accordingly. Of course, it could
> also be the video BIOS that's the problem as you've suggested.
Thank you for the hint. I inspected that, but the PCI-IDs actually look the same:
00:01.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Trinity [Radeon HD 7480D] [1002:9993]
(A4-5300)
and
00:01.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Richland [Radeon HD 8670D] (prog-if 00 [VGA controller])
(A10-6700)
Looks like the VGA BIOS is really different:
# diff vgabios_a4-5300.bin vgabios_a10_6700.bin
Binary files vgabios_a4-5300.bin and vgabios_a10_6700.bin differ
Guess I will have to to "update" the VGA BIOS then.
Cheers, Daniel
>
> Hi Daniel,
>
>
> Kind Regards,
>
> John.
>
>
> On 28/06/16 09:24, Daniel Kulesz via coreboot wrote:
> > Hi folks,
> >
> > I upgraded the CPU in my F2A-85M from a A4-5300 (Trinity) to a A10-6700 (Richland). The board had Coreboot installed before with the VGA BIOS extracted from the A4-5300. However, I did not get any video output when trying to boot after the upgrade, so I replaced the flash chip with a backup with the vendor BIOS that works.
> >
> > Is it likely that the A10-6700 needs a different VGA BIOS or does this this rather look like a different issue? I don't want to experiment too much because the BIOS chips are hardware-wise pretty fragile (even when using the extractor tool).
> >
> > Cheers, Daniel
> >
The Linux 4.7 kernel payload crashes early in the boot process
with CoreBoot 4.4. I traced it to these instructions that are
finding a safe spot to decompress the rest of the kernel and
patched around it with a hard coded location:
diff -u --recursive /home/hudson/build/clean/linux-4.7/arch/x86/boot/compressed/head_64.S ./linux-4.7/arch/x86/boot/compressed/head_64.S
--- /home/hudson/build/clean/linux-4.7/arch/x86/boot/compressed/head_64.S 2016-07-24 15:23:50.000000000 -0400
+++ ./linux-4.7/arch/x86/boot/compressed/head_64.S 2016-08-05 12:07:11.399854225 -0400
@@ -340,9 +357,15 @@
1:
/* Target address to relocate to for decompression */
+#if 0
movl BP_init_size(%rsi), %ebx
subl $_end, %ebx
addq %rbp, %rbx
+#else
+ // coreboot does not populate the init_size boot param?
+ // fake it with a hard coded value
+ movl $0x97b000, %ebx
+#endif
/* Set up the stack */
leaq boot_stack_end(%rbx), %rsp
It seems that the Linux kernel bzImage is supposed to set this value,
rather than coreboot, so my comment is likely incorrect.
Dumping linux-4.7/arch/x86/boot/header.o, it looks like init_siez
is supposed to be 0xcf5000, so I wonder if %rsi is pointing to the
wrong location.
In 4.6.4 the computed address was hardcoded:
movl $LOAD_PHYSICAL_ADDR, %ebx
/* Target address to relocate to for decompression */
addl $z_extract_offset, %ebx
3e: bb 00 00 00 01 mov $0x1000000,%ebx
43: 81 c3 00 00 00 00 add $0x0,%ebx
--
Trammell
Hi,
FOSDEM 2017 deadlines are soon.
Do we want to have a full developer room, a talk or just a stand?
Unfortunately I won't be able to attend, so someone else will have to be
the formal contact for organizing our stand/devroom/talk. I will help
with submitting proposals if this is desired by the person organizing
our stand/devroom/...
Who is willing to take care of our FOSDEM 2017 presence?
https://fosdem.org/2017/news/2016-07-20-call-for-participation/
Deadlines:
Developer Rooms: 9 September
Main Track Talks: 10 October
Stands: 31 October
Lightning talks: 25 November
Regards,
Carl-Daniel
Hello,
I am building coreboot image for Apollo Lake.
My designed mainboard comes with DDR3L SODIMMs + PMIC.
To my knowledge,
RVP1 board is for DDR3L SODIMMs and discrete VRs.
RVP2 board is for LPDDR3 and PMIC.
If I selected under coreboot configuration:
Mainboard --> Mainboard vendor (Intel)
Mainboard model (Apollolake DDR3 RVP1)
How to modify VR type from Discrete to PMIC???
Kind regards,
Morris
Hello All,
I am currently trying to send POST codes from Coreboot (downloaded approximately a month ago) to a Beagle I2C/SPI reader, specifically via i2c. I don't know the register needed for i2c_writeb() so I figured I would use i2c_raw_write(). In general since I have been unable to locate anything explaining the difference between the two functions I would really appriciate it if someone could explain it or direct me to where I can find documentation. I am hoping that the explaination/resource will either tell me where / or direct me to how I can figure out where the i2c_raw_write will write to (if it will just write directly to the Beagle or somewhere else)? Or would it be better to send it to a register with i2c_writeb()? I am running Coreboot on an ASROCK Mainboard, model IMB-A180.
Thank you.
HN
Hello all,
I'm happy to *finally* have the information and registration page online:
https://coreboot.berlin/
Yes, it's very late, but I hope that we will still be a good number
of people meeting up next weekend.
Quick feedback helps me make sure that everyone will get food.
If you are interested in attending, but unable to register at the
Community Registration Fee cost then please get in touch with me,
so that we can try to work something out.
Thank you very much, and hope to see you in Berlin on the 7:th!
//Peter
Hi everyone
I have a question.
Sometime ago i bought a Mini Pcie post card to do some tests, and it works
really well, on a really old notebook.
Now I'm doing some research on a newer notebook, that doesn't have a Mini
Pcie connector.
The only available connector is a m.2 Key A.
So my question is.
What are the chances os my PCie post card work on the m.2 connector after
having an adapter like these:
[image: pasted1] [image: pasted2]
Does any one know if the m.2 connector has any direct connection to the LPC
lines, on the same way as the PCIe slots have ?
Thanks and Regards
Rafael R. Machado
