coreboot September 2016

coreboot@coreboot.org

51 participants
82 discussions

[RFC] Statement regarding AMD’s new architecture Zen
by Paul Menzel 11 Sep '16

11 Sep '16

Dear coreboot folks, AMD presented the new processor architecture *Zen* [1], which – from the published reports – looks quite promising to be competitive to Intel once again. No devices are sold yet, but I guess they are already worked on. (Hopefully, there will be also Google Chromebooks and Chromeboxes.) Should the coreboot community publish a statement, asking AMD to make it possible to fully initialize these devices with free software? Is there somebody good in English writing, and knowledgeable of the current state, able to draft something up? For example, will there still be a Platform Security Processor (PSP) [2], and SMU (System(?) Management Unit) [3]? What does the statement need to contain? 1. Request for free documentation for all parts (chipset (RAM) init, PSP, SMU, …) 2. User controllable signing keys 3. Reference to Intel’s involvement to coreboot Nice to have: 4. Code contributions from AMD What else is missing? (I am well aware, that such a statement has a small chance to change anything. But better try than not.) Thanks, Paul [1] https://en.wikipedia.org/wiki/Zen_%28microarchitecture%29 [2] https://www.coreboot.org/Binary_situation#recent_AMD

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 09 Sep '16

09 Sep '16

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1362592: Null pointer dereferences (NULL_RETURNS) ________________________________________________________________________________________________________ *** CID 1362592: Null pointer dereferences (NULL_RETURNS) /src/drivers/generic/max98357a/max98357a.c: 41 in max98357a_fill_ssdt() 35 struct acpi_dp *dp; 36 37 if (!dev->enabled || !config) 38 return; 39 40 /* Device */ >>> CID 1362592: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be null "acpi_device_scope(dev)" when calling "acpigen_write_scope". 41 acpigen_write_scope(acpi_device_scope(dev)); 42 acpigen_write_device(acpi_device_name(dev)); 43 acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); 44 acpigen_write_name_integer("_UID", 0); 45 acpigen_write_name_string("_DDN", dev->chip_ops->name); 46 acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] anyone use coreboot on Lenovo T520?
by Patrick Rudolph 08 Sep '16

08 Sep '16

On Wed, 7 Sep 2016 21:15:05 +0800 Iru Cai <mytbk920423(a)gmail.com> wrote: Hi Iru, I've got a T520 with soldered pin header as in the referenced wiki page, and I've got a T420 where I had to use 10cm long wires to place the pin header near the RAM slots to make it accessible through the bottom flap. I've got no problems using both devices. Can you give more information where the system hangs ? Does it hang in coreboot? Does it occur after hours running the system ? Regards, Patrick > Hi community, > > I've had this problem for a long time, but I don't feel like to ask it > until some one ask me about this problem. > > Lenovo T520 has a BIOS chip under the magnesium structure frame, and > it may have a WSON package, so I solder a pin connector at the `J100' > solder place. (https://www.coreboot.org/Board:lenovo/t520#Flashing) > However, I don't know whether it can cause problems. I flashed two > pieces of T520 mainboard (without nVIDIA GPU) before, and after it had > coreboot installed, the system could hang randomly, I don't know what > had happened. I hadn't tested it with the pin connector soldered and > factory firmwae. > > So I hope some one with this laptop can report some status in using. > > Regards, > Iru

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Welcome to the new coreboot.org!
by Stefan Reinauer 08 Sep '16

08 Sep '16

Hi! As some of you might already have noticed, our new web presence has gone live on https://www.coreboot.org/ today! I want to use this chance to send a big shout out to Philipp Deppenwiese and Martin Roth, and all the others that have been involved in making this moment happen, for their great work! With the new web page, our presence has not only arrived in the 21st century. We also have a better portal to catch the different groups interested in coreboot, in the future: End users, software developers and hardware manufacturers. There will be changes, modifications and optimizations in the next couple of days or weeks, but please feel free to send us feedback on coreboot's new look and content. Thanks, Stefan

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Re: [coreboot] anyone use coreboot on Lenovo T520?
by Patrick Rudolph 08 Sep '16

08 Sep '16

On Thu, 8 Sep 2016 19:25:15 +0800 Iru Cai <mytbk920423(a)gmail.com> wrote: > Hi Patrick, > > On Wed, Sep 07, 2016 at 05:36:45PM +0200, Patrick Rudolph wrote: > > On Wed, 7 Sep 2016 21:15:05 +0800 > > Iru Cai <mytbk920423(a)gmail.com> wrote: > > > > Hi Iru, > > I've got a T520 with soldered pin header as in the referenced wiki > > page, and I've got a T420 where I had to use 10cm long wires to > > place the pin header near the RAM slots to make it accessible > > through the bottom flap. > > I never solder pins on T420, and have no such problem. Maybe there's > something to do with my soldering skills. > > > I've got no problems using both devices. > > > > Can you give more information where the system hangs ? > > Does it hang in coreboot? Does it occur after hours running the > > system ? > > The machine boots fine to Linux, but it can freeze after some time, > and I can't predict when this will happen. You can try to limit DDR frequency using devicetree's max_mem_clock_mhz setting. Vendor BIOS uses 666 here. You can try to limit CPU pstate. It looks like the vendor BIOS doesn't expose the highest pstate at all. I haven't looked at this, but I guess it's to decrease power consumtion when running on battery. I've never had any problem using coreboot on my T420. You can find the commit here: https://www.coreboot.org/Supported_Motherboards#lenovo.2Ft420 > > > > > Regards, > > Patrick > > > > Regards, > Iru > > > > Hi community, > > > > > > I've had this problem for a long time, but I don't feel like to > > > ask it until some one ask me about this problem. > > > > > > Lenovo T520 has a BIOS chip under the magnesium structure frame, > > > and it may have a WSON package, so I solder a pin connector at > > > the `J100' solder place. > > > (https://www.coreboot.org/Board:lenovo/t520#Flashing) However, I > > > don't know whether it can cause problems. I flashed two pieces of > > > T520 mainboard (without nVIDIA GPU) before, and after it had > > > coreboot installed, the system could hang randomly, I don't know > > > what had happened. I hadn't tested it with the pin connector > > > soldered and factory firmwae. > > > > > > So I hope some one with this laptop can report some status in > > > using. > > > > > > Regards, > > > Iru > >

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Re: [coreboot] Welcome to the new coreboot.org!
by ron minnich 08 Sep '16

08 Sep '16

That is terrific! On Thu, Sep 8, 2016 at 9:15 AM Martin Roth <gaumless(a)gmail.com> wrote: > "Better" is having the website checked into git, so any of us can update > it! > > https://review.coreboot.org/#/q/project:homepage+status:open > https://review.coreboot.org/#/admin/projects/homepage > > > > > > > On Thu, Sep 8, 2016 at 8:12 AM, Zoran Stojsavljevic < > zoran.stojsavljevic(a)gmail.com> wrote: > >> There is always "better" per say, whatever does it mean!? ;-) >> >> Am I right (I am too old to play it on first, second... N-th quick >> pick move), don't I? ;-))) >> >> Zoran >> >> On 9/8/16, ron minnich <rminnich(a)gmail.com> wrote: >> > It's wonderful. >> > >> > For fun, I found this, which is *not* the first one, but close. >> > >> > >> https://web.archive.org/web/20000819124055/http://www.acl.lanl.gov/linuxbio… >> > >> > >> > On Wed, Sep 7, 2016 at 5:51 PM Stefan Reinauer >> > <stefan.reinauer(a)coreboot.org> >> > wrote: >> > >> >> Hi! >> >> >> >> As some of you might already have noticed, our new web presence >> >> has gone live on https://www.coreboot.org/ today! >> >> >> >> I want to use this chance to send a big shout out to Philipp >> Deppenwiese >> >> and Martin Roth, and all the others that have been involved in making >> >> this moment happen, for their great work! >> >> >> >> With the new web page, our presence has not only arrived in the 21st >> >> century. We also have a better portal to catch the different groups >> >> interested in coreboot, in the future: End users, software developers >> >> and hardware manufacturers. >> >> >> >> There will be changes, modifications and optimizations in the next >> >> couple of days or weeks, but please feel free to send us feedback on >> >> coreboot's new look and content. >> >> >> >> Thanks, >> >> Stefan >> >> >> >> -- >> >> coreboot mailing list: coreboot(a)coreboot.org >> >> https://www.coreboot.org/mailman/listinfo/coreboot >> >> >> > >> > >

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Re: [coreboot] Welcome to the new coreboot.org!
by Martin Roth 08 Sep '16

08 Sep '16

"Better" is having the website checked into git, so any of us can update it! https://review.coreboot.org/#/q/project:homepage+status:open https://review.coreboot.org/#/admin/projects/homepage On Thu, Sep 8, 2016 at 8:12 AM, Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > There is always "better" per say, whatever does it mean!? ;-) > > Am I right (I am too old to play it on first, second... N-th quick > pick move), don't I? ;-))) > > Zoran > > On 9/8/16, ron minnich <rminnich(a)gmail.com> wrote: > > It's wonderful. > > > > For fun, I found this, which is *not* the first one, but close. > > > > https://web.archive.org/web/20000819124055/http://www.acl. > lanl.gov/linuxbios/index.html > > > > > > On Wed, Sep 7, 2016 at 5:51 PM Stefan Reinauer > > <stefan.reinauer(a)coreboot.org> > > wrote: > > > >> Hi! > >> > >> As some of you might already have noticed, our new web presence > >> has gone live on https://www.coreboot.org/ today! > >> > >> I want to use this chance to send a big shout out to Philipp Deppenwiese > >> and Martin Roth, and all the others that have been involved in making > >> this moment happen, for their great work! > >> > >> With the new web page, our presence has not only arrived in the 21st > >> century. We also have a better portal to catch the different groups > >> interested in coreboot, in the future: End users, software developers > >> and hardware manufacturers. > >> > >> There will be changes, modifications and optimizations in the next > >> couple of days or weeks, but please feel free to send us feedback on > >> coreboot's new look and content. > >> > >> Thanks, > >> Stefan > >> > >> -- > >> coreboot mailing list: coreboot(a)coreboot.org > >> https://www.coreboot.org/mailman/listinfo/coreboot > >> > > >

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Re: [coreboot] Coreboot with ipxe for Pc Engines Alix2d13
by Reto Rayen 08 Sep '16

08 Sep '16

Hello guys Is any further Informationen needed? To solve this issue. Should i create a ticket for this? Kind regards Reto Rayen

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Re: [coreboot] Welcome to the new coreboot.org!
by Zoran Stojsavljevic 08 Sep '16

08 Sep '16

There is always "better" per say, whatever does it mean!? ;-) Am I right (I am too old to play it on first, second... N-th quick pick move), don't I? ;-))) Zoran On 9/8/16, ron minnich <rminnich(a)gmail.com> wrote: > It's wonderful. > > For fun, I found this, which is *not* the first one, but close. > > https://web.archive.org/web/20000819124055/http://www.acl.lanl.gov/linuxbio… > > > On Wed, Sep 7, 2016 at 5:51 PM Stefan Reinauer > <stefan.reinauer(a)coreboot.org> > wrote: > >> Hi! >> >> As some of you might already have noticed, our new web presence >> has gone live on https://www.coreboot.org/ today! >> >> I want to use this chance to send a big shout out to Philipp Deppenwiese >> and Martin Roth, and all the others that have been involved in making >> this moment happen, for their great work! >> >> With the new web page, our presence has not only arrived in the 21st >> century. We also have a better portal to catch the different groups >> interested in coreboot, in the future: End users, software developers >> and hardware manufacturers. >> >> There will be changes, modifications and optimizations in the next >> couple of days or weeks, but please feel free to send us feedback on >> coreboot's new look and content. >> >> Thanks, >> Stefan >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> >

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GNU Libreboot, version 20160907 released
by Leah Rowe 07 Sep '16

07 Sep '16

GNU Libreboot 20160907 This release adds one new mainboard to libreboot: * Intel D945GCLF desktop motherboard (thanks to Arthur Heymans) For existing boards, there are no new board specific changes. Get it from: https://libreboot.org/download/ Other bugfixes: * Various improvements to the documentation * re-added "unset superusers" to the grub.cfg, which was needed for some users depending on the distros that they used GNU Libreboot 20160902 This is a bugfix release, based on 20160818. It contains no new board changes. The previous 20160818 release had build errors in the _src archive, and the _util archive was only source code. Changes compared to 20160818: * Fixed bug where ./build module coreboot always returned non-zero status * Fixed missing symlink of crossgcc when building from _src (thanks Arthur Heymans) * Fixed building with the depthcharge payload (ASUS C201) * Proper ChangeLog now, instead of pasted git log * Util archive is now binaries again (source code is in the _src archive) * Documentation is now in HTML format GNU Libreboot 20160818 This is a brand GNU release. Libreboot joined the GNU project on 14 May 2016. This 18 August 2016 release is the first GNU release of libreboot. NEW BOARDS ADDED: * ASUS Chromebook C201 (ARM laptop) (thanks to Paul Kocialkowski) * Gigabyte GA-G41M-ES2L motherboard (desktop) (thanks to Damien Zammit) * Intel D510MO motherboard (desktop) (thanks to Damien Zammit) * ASUS KCMA-D8 motherboard (desktop) (thanks to Timothy Pearson) * ASUS KFSN4-DRE motherboard (server) (thanks to Timothy Pearson) * ASUS KGPE-D16 motherboard (server) (thanks to Timothy Pearson) For details development history on these boards, refer to the git log and documentation. For boards previously supported, many fixes from upstream have been merged. Other changes (compared to libreboot 20150518), for libreboot in general or for previously supported systems: (this is a summary. For more detailed change list, refer to the git log) 256MiB VRAM allocated on GM45 (X200, T400, T500, R400) instead of 32MiB. This is an improvement over both Lenovo BIOS and Libreboot 20150518, allowing video decoding at 1080p to be smoother. (thanks Arthur Heymans) To clarify, GM45 video performance in libreboot 20160818 is better than on the original BIOS and the previous libreboot release. 64MiB VRAM on i945 (X60, T60, MacBook2,1) now supported in coreboot-libre, and used by default (in the previous release, it was 8MiB allocated). Thanks to Arthur Heymans. Higher battery life on GM45 (X200, T400, T500, R400) due to higher cstates now being supported (thanks Arthur Heymans). C4 power states also supported. Higher battery life on i945 (X60, T60, MacBook2,1) due to better CPU C-state settings. (Deep C4, Dynamicl L2 shrinking, C2E). Text mode on GM45 (X200, T400, T500, R400) now works, making it possible to use MemTest86+ comfortably. (thanks to Nick High from coreboot) Dual channel LVDS displays on GM45 (T400, T500) are now automatically detected in coreboot-libre. (thanks Vladimir Serbinenko from coreboot) Partial fix in coreboot-libre for GRUB display on GM45, for dual channel LVDS higher resolution LCD panels (T400, T500). (thanks Arthur Heymans) Massively improved GRUB configuration, making it easier to boot more encrypted systems automatically, and generally a more useful menu for booting the system (thanks go to Klemens Nanni of the autoboot project). Libreboot now uses the grub.cfg provided by the installed GNU/Linux distribution automatically, if present, switching to that configuration. This is done across many partitions, where libreboot actively searches for a configuration file (also on LVM volumes and encrypted volumes). This should make libreboot more easy to use for non-technical users, without having to modify the GRUB configuration used in libreboot. Utilities archives is now source only. You will need to compile the packages in there (build scripts included, and a script for installing build dependencies in Trisquel 7). (binary utility archives are planned again in the next release, when the new build system is merged) SeaGRUB is now the default payload on all x86 boards. (SeaBIOS configured to load a compressed GRUB payload from CBFS immediately, without providing an interface in SeaBIOS. This way, GRUB is still used but now BIOS services are available, so you get the best of both worlds). Thanks go to Timothy Pearson of coreboot for this idea. crossgcc is now downloaded and built as a separate module to coreboot-libre, with a universal revision used to build all boards. Individual boards now have their own coreboot revision and patches, independently of each other board. This makes maintenance easier. Updated all utilities, and modules (coreboot, GRUB, etc) to newer versions, with various bugfixes and improvements upstream. RTC century byte issue now fixed on GM45 in coreboot-libre, so the date should now be correctly displayed when running the latest linux kernel, instead of seeing 1970-01-01 when you boot (thanks to Alexander Couzens from coreboot) Build system now uses multiple CPU cores when building, speeding up building for some people. Manually specifying how many cores are needed is also possible, for those using the build system in a chroot environment. (thanks go to Timothy Pearson from coreboot) In the build system (git repository), https:// is now used when cloning coreboot. http:// is used as a fallback for GRUB, if git:// fail s. New payload, the depthcharge bootloader (free bootloader maintained by Google) for use on the ASUS Chromebook C201. (thanks go to Paul Kocialkowski) Various fixes to the ich9gen utility (e.g. flash component density is now set correctly in the descriptor, gbe-less descriptors now supported) The official documentation included in the release in provided in texinfo format, instead of HTML; this was one of the requirements for joining GNU. (the other requirement is a new build system, to comply with GNU standards, e.g. Makefiles, and common Makefile entries present in all GNU software. As of Libreboot 20160818, this new build system is not yet merged, but will be in the release afterwards) ChangeLog and NEWS files are included in the release, to comply with GNU standards (they are dumps of the git-log output) -- Leah Rowe Libreboot developer Use free software. Free as in freedom. https://www.gnu.org/philosophy/free-sw.html Use a free operating system, GNU/Linux. https://www.gnu.org/ Use a free BIOS. https://libreboot.org/ Support freedom. Join the Free Software Foundation. https://fsf.org/ Minifree Ltd, trading as Ministry of Freedom | Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK | Web: http://minifree.org/

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coreboot September 2016