coreboot September 2016

coreboot@coreboot.org

51 participants
82 discussions

What problems are there with native RAM initialization on Intel Sandy Bridge?
by Paul Menzel 26 Sep '16

26 Sep '16

Dear Matt, You commented in [1], that there are problems with native RAM initialization on Intel Sandy Bridge. > using native raminit seems to be problematic on several > samsung/stumpy devices, hence the use of the MRC blob instead In #coreboot, I was asked which ones there are. Could you please report those here, or in the bug tracker [2]. Thanks, Paul [1] https://review.coreboot.org/16735/ [2] https://ticket.coreboot.org/

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Getting an WXGA+ LED MVA panel to work on T400: "G141C1-L01"
by Merlin Büge 26 Sep '16

26 Sep '16

Hello everyone! This is my first post to this mailing list :) I'm trying to get a specific panel working on my Thinkpad T400 which runs libreboot. It's an WXGA+ MVA panel (CMO G141C1-L01) and I have soldered an adapter cable for it. From what I have found, nobody succeeded on this mod yet - there are some attempts on 51nb.com, but only for the T410. I basically took some already existing adapter cable, and modified a few pins, so that it would match up exactly with the datasheets. I used the LG LP141WP2-TLB1 for reference. Some details about my adapter cable can be found here: http://forum.thinkpads.com/viewtopic.php?f=45&t=121151 In the first post there are also links to the datasheets of the two panels in question. Of course I thoroughly checked all my self-made connections and modifications, but only with some general purpose DMM for continuity. They all seem fine. So far backlight + PWM control works, but I have no image displayed, both in libreboot (with GRUB2 as payload) and Linux (up-to-date Arch Linux). I tried the panel both with the latest stock ROM (3.23/EC 1.06) and with the latest libreboot release, which is currently 2016090 (t400_8mb_usqwerty_vesafb.rom in my case). Since I have not much experience with such low-level hardware stuff, could someone maybe help me with this or direct me to some useful direction, how I can debug this? I already tried booting with i915.lvds_channel_mode=2 (since I was not able to figure out what mode was actually used, because this module parameter is normally set to "0", which means the channel mode is taken from BIOS). I attached the EDIDs of both panels, the coreboot log (cbmem -c) of both panels, and a kernel log of both panels. I also attached a kernel log of the MVA panel with drm debbuging enabled (drm.debug=0x1e log_buf_len=1M). Note that all of the logs were taken from the T400 with the latest libreboot release. It would be great if somebody could have a look at it. (I don't understand much of it.) Here is a picture of the adapter cable, so that you have an idea what it looks like: https://lut.im/funPftuHF0/3sndAspbdiwOpTN4.jpg I already put *a lot* of effort in this project, and I would be very happy if it succeeded at the end of the day. I would design some PCBs then, so that this would basically become a drop-in replacement. Background is: The T400 is a very desirable target for libreboot, since it's build on the latest Intel hardware currently supported in libreboot for laptops. And (not only in the libreboot community) it is sadly well known for its rather bad TN panels. Also, it would be something that I could give back to the libreboot community. Since I have not much experience with mailing lists, please correct my of any 'bad' behavior. Thank you for reading this, and for any advice in advance :) Regards, Merlin -- Merlin Büge <toni(a)bluenox07.de>

3 4

USB 2.0 test pattern support on Bayley Bay
by Mayuri Tendulkar 25 Sep '16

25 Sep '16

Hi Team We are trying to do the eye pattern test on USB2.0 on Bayley Bay board. But we are not able to see the test pattern support from BIOS side. Do we have any settings in coreboot to enable this? This works fine on any Linux laptop/desktop Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] Debugging MRC issues with FPS
by Zoran Stojsavljevic 25 Sep '16

25 Sep '16

Hello Adolfo (you are somehow known to me, isn't it that you are working for INTEL Inside support, or maybe not)!? What does it mean _cr in your email address (Costa Rica, isn't it)?! ;-) Let us ask this very relevant people in INTEL Inside, who MANDATORY should know info you are asking, since they are responsible, aren't they (INTEL insider is asking for FSP POST codes Coreboot outsiders, which will again ask much more relevant INTEL Insiders)??? IN -> OUT -> IN schema. Shouldn't it be: IN -> IN schema ONLY??? :-)) Verrückt (Deutsche Sprache)?! :LOL: _______ Hello Stephanie, You realize how this all strange is (the context)? *BTW, we, Coreboot members... We should once forever know these POST codes are (you hide inside FSPs - probably reminiscence of BIOS MRC post codes, or you tell us all?!)? Could you, please, make this as public info to INTEL Outside?* Divya, Could you, please, arrange what I am (in *RED*) asking for (INTEL Inside and INTEL Outside)? You do realize why I am asking this, correct???💡 (don't touch/blame Adolfo... You should ask many questions somewhere else... You know exactly where!) Thank you, Zoran Stojsavljevic, independent FREE contributor On Sun, Sep 25, 2016 at 5:55 PM, Adolfo Sanchez <adolfo_sm_cr(a)hotmail.com> wrote: > Hello > > > I would like to know the best way to get information about a Failure > related with Memory Initialization when using FPS. > > Specially when the FSPmemoryinit is being called but then the system > hangs. POST Code 0x50 > > What flags can be enable to get more information? > > > Best Regards, > > Adolfo Sanchez > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Debugging MRC issues with FPS
by Adolfo Sanchez 25 Sep '16

25 Sep '16

Hello I would like to know the best way to get information about a Failure related with Memory Initialization when using FPS. Specially when the FSPmemoryinit is being called but then the system hangs. POST Code 0x50 What flags can be enable to get more information? Best Regards, Adolfo Sanchez

1 0

Support for Gigabyte ga-ma78gm-us2h?
by Alberto Simón Francés 25 Sep '16

25 Sep '16

Hello, I've been trying to make this board boot and I haven't had much success. Sometimes I've been able to get it to POST, but it's not something that happens consistently. Since I can't find much info other than it being listed, I'm asking here to see if by any chance there's something that I'm missing, because I feel like I'm just trying random things to see what sticks. Thankfully the board has dual bios, so it's easy to go back if I mess something up. Please, help. Best regards, Albert

1 0

Does anyone know about SMSC KBC1126?
by Iru Cai 25 Sep '16

25 Sep '16

Hi, I'm trying to work with some HP machines. I disassembled these machines and saw they the EC chip SMSC KBC1126-NU. I read the backup firmware and can see strings like `8051 RESET`, and I found if I modify certain part of the firmware, the machine will fail to power with some LEDs blinking, so I know the EC firmware is in the BIOS chip, and it's an 8051 program. I searched about this chip, and some people say the EC chip also contains program. I can't find anything about this chip, and coreboot wiki has KBC1122 and I only found a 5-page product review on the Internet. I don't know if there's anyone know about this EC. I want to know about: - Where is the entry point of the EC firmware in the BIOS chip - How this EC chip does the power management and keyboard control Thanks, Iru

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FSF transgender discrimination anyone? GNU project refuses to let go of libreboot
by Leah Rowe 24 Sep '16

24 Sep '16

Hi, A week ago, libreboot left the GNU project because of transgender discrimination at the Free Software Foundation. GNU project has told me that they will not allow libreboot to leave GNU. This is quite possibly the biggest insult imaginable, considering what has happened. This attitude within the GNU project is disgusting. So the libreboot project hereby announces just how disgusting both the GNU project and FSF are: https://libreboot.org/gnu-insult/ -- Leah Rowe Libreboot developer Use free software. Free as in freedom. https://en.wikipedia.org/wiki/Free_software Use a free operating system, GNU/Linux. Use a free BIOS. https://libreboot.org/ Support computer user freedom. https://peers.community/ Minifree Ltd, trading as Ministry of Freedom | Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK | Web: http://minifree.org/

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SMI handler for fsp_broadwell_de
by Watzlavick, Robert L 23 Sep '16

23 Sep '16

I want to experiment with an SMI handler on the Camelback Mountain CRB (Xeon D-1500) but it appears that the fsp_broadwell_de changes removed SMM support. I'm browsing the coreboot-4.4 release. Was there a reason it was removed? It shows up in the soc/intel/Broadwell area so I suppose I could port over the original code. I didn't see that the D_LCK bit was set anywhere so does that mean I can potentially let SeaBIOS install an SMI handler? Or is it set in the FSP? I also noticed the mainline has some new code under coreboot/src/soc/intel/sch but I'm not sure which processors that is for. Thanks, -Bob

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Re: [coreboot] SMI handler for fsp_broadwell_de
by Watzlavick, Robert L 23 Sep '16

23 Sep '16

Thank you very much for the reply. I think you mean though that the FSP does NOT need to be touched - correct? -Bob ________________________________ From: Yang, York [york.yang(a)intel.com] Sent: Thursday, September 22, 2016 8:34 PM To: Watzlavick, Robert L (US); coreboot(a)coreboot.org Subject: EXTERNAL: Re: SMI handler for fsp_broadwell_de Fsp_broadwell_de do not implement the SMI support, but you may refer to soc/Broadwell as both are Intel architecture chipset. The SMI support can be done purely in coreboot, but need to touch FSP. / YoRK From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Watzlavick, Robert L Sent: Thursday, September 22, 2016 4:28 PM To: coreboot(a)coreboot.org Subject: [coreboot] SMI handler for fsp_broadwell_de I want to experiment with an SMI handler on the Camelback Mountain CRB (Xeon D-1500) but it appears that the fsp_broadwell_de changes removed SMM support. I’m browsing the coreboot-4.4 release. Was there a reason it was removed? It shows up in the soc/intel/Broadwell area so I suppose I could port over the original code. I didn’t see that the D_LCK bit was set anywhere so does that mean I can potentially let SeaBIOS install an SMI handler? Or is it set in the FSP? I also noticed the mainline has some new code under coreboot/src/soc/intel/sch but I’m not sure which processors that is for. Thanks, -Bob

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coreboot September 2016