coreboot February 2021

coreboot@coreboot.org

42 participants
34 discussions

Currently broken devicetrees (was Re: X200 dock has been broken since November 2019)

by Nico Huber

Hi all, that we had another case of a missing-device-below-chip in a devicetree made me write a patch for `sconfig` [1]. Now that it's checking for the issue, that uncovered a few (31) more cases [2] that need to be fixed before upstream can benefit from the patch. Please help to fix the devicetrees. Note, `sconfig` currently doesn't print the file name of override trees, e.g. when it says SCONFIG mainboard/.../devicetree.cb line 10: end: syntax error that might as well refer to line 10 in an override tree. Nico [1] https://review.coreboot.org/c/coreboot/+/51119 [2] https://qa.coreboot.org/job/coreboot-gerrit/164572/ Failing boards: board.AMD_BILBY board.AMD_CEREME board.AMD_MANDOLIN board.GETAC_P470 board.GOOGLE_BRYA0 board.GOOGLE_FALCO board.GOOGLE_PEPPY board.GOOGLE_WOLF board.KONTRON_BSL6 board.LENOVO_R500 board.LENOVO_T430S board.LENOVO_T431S board.LENOVO_T520 board.LENOVO_T530 board.LENOVO_W530 board.LENOVO_X1 board.LENOVO_X220 board.LENOVO_X220I board.LENOVO_X220_MRC_BIN board.LENOVO_X220_OPTION_TABLE_DEBUG_TPM_EXTENDED_CBFS board.LENOVO_X230 board.LENOVO_X230S board.LENOVO_X230T board.LENOVO_X301 board.LENOVO_X60 board.RODA_RK886EX board.SIEMENS_BOXER26

1 month, 1 week

A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

by dponamorev＠gmail.com

Hi! We developed our CRB motherboard on Intel Atom C3538 (4 core) Denverton_NS processor. Faced with the following problem. For part of processors with the same SKU and steping (Atom C3538), lapic #4 in devicetree.cb needed (95%), and for the other part lapic #0 (5%). Intel confirmed that it might be so and that's okay ... Part of devicetree.cb: device cpu_cluster 0 on device lapic 4 on end end If we do not specify lapic id correctly in devicetree.cb, freeBSD OS does not BOOT (Unix like). FreeBSD BOOT log (set lapic #4 in devicetree.cb but need lapic #0): Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 APIC: Found table at 0x7f769420 APIC: Using the MADT enumerator. MADT: Found CPU APIC ID 0 ACPI ID 0: enabled SMP: Added CPU 0 (AP) MADT: Found CPU APIC ID 4 ACPI ID 1: enabled SMP: Added CPU 4 (AP) MADT: Found CPU APIC ID 12 ACPI ID 2: enabled SMP: Added CPU 12 (AP) MADT: Found CPU APIC ID 16 ACPI ID 3: enabled SMP: Added CPU 16 (AP) MADT: Found CPU APIC ID 24 ACPI ID 4: enabled SMP: Added CPU 24 (AP) Copyright (c) 1992-2019 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 11.3-RELEASE #0 r349754: Fri Jul 5 04:45:24 UTC 2019 root@releng2.nyi.freebsd.org:/usr/obj/usr/src/sys/GENERIC amd64 FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0) Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 Table 'HPET' at 0x7f7694a0 ACPI: No SRAT table found PPIM 0: PA=0xa0000, VA=0xffffffff82410000, size=0x10000, mode=0 VT(vga): resolution 640x480 Preloaded elf kernel "/boot/kernel/kernel" at 0xffffffff8226d000. Calibrating TSC clock ... TSC clock: 2100071708 Hz CPU: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz (2100.07-MHz K8-class CPU) Origin="GenuineIntel" Id=0x506f1 Family=0x6 Model=0x5f Stepping=1 Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE> Features2=0x4ff8ebbf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,RDRAND> AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM> AMD Features2=0x101<LAHF,Prefetch> Structured Extended Features=0x2294e283<FSGSBASE,TSCADJ,SMEP,ERMS,NFPUSG,MPX,PQE,RDSEED,SMAP,CLFLUSHOPT,PROCTRACE,SHA> Structured Extended Features3=0xac000400<MD_CLEAR,IBPB,STIBP,ARCH_CAP,SSBD> XSAVE Features=0xf<XSAVEOPT,XSAVEC,XINUSE,XSAVES> IA32_ARCH_CAPS=0x69<RDCL_NO,SKIP_L1DFL_VME> VT-x: Basic Features=0xda0400<SMM,INS/OUTS,TRUE> Pin-Based Controls=0xff<ExtINT,NMI,VNMI,PreTmr,PostIntr> Primary Processor Controls=0xfff9fffe<INTWIN,TSCOff,HLT,INVLPG,MWAIT,RDPMC,RDTSC,CR3-LD,CR3-ST,CR8-LD,CR8-ST,TPR,NMIWIN,MOV-DR,IO,IOmap,MTF,MSRmap,MONITOR,PAUSE> Secondary Processor Controls=0x1d6fff<APIC,EPT,DT,RDTSCP,x2APIC,VPID,WBINVD,UG,APIC-reg,VID,PAUSE-loop,RDRAND,VMFUNC,VMCS,XSAVES> Exit Controls=0xda0400<PAT-LD,EFER-SV,PTMR-SV> Entry Controls=0xda0400 EPT Features=0x6334141<XO,PW4,UC,WB,2M,1G,INVEPT,AD,single,all> VPID Features=0xf01<INVVPID,individual,single,all,single-globals> TSC: P-state invariant, performance statistics DTLB: 4k pages, fully associative, 32 entries Data TLB: 4 KBytes pages, 4-way set associative, 512 entries Instruction TLB: 4 KByte pages, fully associative, 48 entries DTLB: 2M/4M Byte pages, 4-way associative, 32 entries L2 cache: 2048 kbytes, 16-way associative, 64 bytes/line real memory = 8589934592 (8192 MB) Physical memory chunk(s): 0x0000000000010000 - 0x000000000009bfff, 573440 bytes (140 pages) 0x0000000000100000 - 0x00000000001fffff, 1048576 bytes (256 pages) 0x0000000002400000 - 0x000000007f74ffff, 2100625408 bytes (512848 pages) 0x0000000100000000 - 0x000000027012efff, 6175256576 bytes (1507631 pages) avail memory = 8220336128 (7839 MB) Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 Table 'HPET' at 0x7f7694a0 ACPI: No DMAR table found Event timer "LAPIC" quality 600 ACPI APIC Table: <COREv4 COREBOOT> WARNING: L1 data cache covers less APIC IDs than a core 0 < 1 Package ID shift: 5 L2 cache ID shift: 2 L1 cache ID shift: 1 Core ID shift: 1 panic: AP #4 (PHY# 0) failed! cpuid = 0 KDB: stack backtrace: #0 0xffffffff80b4c4b7 at kdb_backtrace+0x67 #1 0xffffffff80b054ce at vpanic+0x17e #2 0xffffffff80b05343 at panic+0x43 #3 0xffffffff80f752a4 at native_start_all_aps+0x344 #4 0xffffffff80f74c4f at cpu_mp_start+0x2ef #5 0xffffffff80b5cb76 at mp_start+0xa6 #6 0xffffffff80aa0b48 at mi_startup+0x118 #7 0xffffffff8031202c at btext+0x2c Uptime: 1s Other Linux OS boot but show an incorrect number of cores (5 instead of 4) and offline processor cores appear (see log). Ubuntu 18.04 LTS (GNU/Linux 4.15.0-20-generic x86_64) # lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 5 On-line CPU(s) list: 0,2-4 Off-line CPU(s) list: 1 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 95 Model name: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz Stepping: 1 CPU MHz: 2097.502 CPU max MHz: 2100.0000 CPU min MHz: 800.0000 BogoMIPS: 4200.00 Virtualization: VT-x L1d cache: 24K L1i cache: 32K L2 cache: 2048K NUMA node0 CPU(s): 0,2-4 What can be done in this situation? How to make a universal version of devicetree.cb?

1 month, 3 weeks

TigerLake RVP TCSS init failure

by Michal Zygowski

Dear coreboot community, I have encountered problem with silicon init on Tiger Lake RVP platform. I managed to resolve previous issues with memory initialization and now hitting an error with TCSS init. The FSP asserts on IOM ready check, which is 0. The configuration has selected CONFIG_USE_INTEL_FSP_MP_INIT (without MP PPI service). When the CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI is selected, then the FSP-S returns smoothly (at least from one of the phases I guess) and resets after clearing MCEs in coreboot's CPU init: CPU: vendor Intel device 806c0 CPU: family 06, model 8c, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x00 done. Turbo is available but hidden Turbo is available and visible CPU #0 initialized Initializing CPU #2 Initializing CPU #6 Initializing CPU #7 CPU: vendor Intel device 806c0 CPU: family 06, model 8c, stepping 00 CPU: vendor Intel device 806c0 CPU: family 06, model 8c, stepping 00 Clearing out pending MCEs Cl (tutaj następuje reset) Any ideas what may cause these issues? When I clean this up, I will upstream the DDR4 variant of TGL UP3 RVP. -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com

1 month, 3 weeks

what are requirements for coreboot IOMMU support?

by ludphaeus

Hi I am trying to port a Haswell laptop and I would want it to have IOMMU support. My chipset supports VT-d but CPU does not. The official info from Intel says the PC needs chipset, CPU and BIOS to support VT-d to use IOMMU. I think this is not true because I saw some boards in board status have working IOMMU with no VT-d support in chipset but with coreboot advertising DMAR table to OS and CPU with VT-d support. Sapphire H61 is a example of this. But other H61 coreboot boards such as P8H61-M LX that have CPU without VT-d advertise no IOMMU capability. So what is really required for full IOMMU ? Do I have chance for full, working IOMMU on this laptop? Thanks, Lud

7 months, 3 weeks

Display Port Monitor turns off during Ubuntu OS boot

by Rao G

Hi Coreboot Team, There is an external Monitor which works on HDMI/DVI and also DP , In BIOS the display is good whereas in OS (Ubuntu 18.04) until the kernel is initialized and i915 Video driver is loaded display is perfect, looks like the i915 OS driver switches off the monitor and there is no signal Does ACPI GFX method have to return any External display specific data to the OS driver ? Tried to make changes to VBIOS but did not help, thought ASL code is missing under GFX0 From the OS following data can be read 1. External Monitor's EDID data can be read from I2C Bus 2. Even VBT data from ACPI NVS can be read Tried to dig into some of these files https://github.com/torvalds/linux/tree/master/drivers/gpu/drm/i915/display intel_dp.c, intel_acpi.c to understand what function is turning off DP link when i have the OS debug driver logs, can send it across Any clues will help, appreciate your time PS:The platform has Intel BayTrail SoC, ValleyView chipset and VBIOS. The bios do not use GOP driver which replaces VBIOS Thanks Rao

7 months, 3 weeks

Lenovo T410: Regression in coreboot 4.13?

by Daniel Kulesz

Hi folks, I spent a long time trying to get coreboot 4.13 to work on a Lenovo T410, trying various configuration options etc. but it never worked (fan, keyboard LED and thinklight went on, screen stayed dark). I tried even the most basic config, but no luck. I tried the same with coreboot 4.12 and this seems to work fine. Unfortunately, this is not my laptop and the owner needs his laptop back asap, so I don't have the time to further debug this issue. Yet, I wanted to report this regression as I I am wondering if anyone else is running 4.13 on a T410 with success? Cheers, Daniel

7 months, 3 weeks

Question regarding reflashing/updating

by Louis

Hello, Just wanted to say thank you for creating this firmware it is a great project and I hope I can contribute to it one day. I have an x230 preinstalled with Coreboot skulls, am I able to re-flash Coreboot skulls internally just through the OS or is there a way to verify that the firmware installed on the system hasn't been modified in any way, thank you. Kindest regards, Louis

7 months, 3 weeks

T440P porting and issues

by crabstorage＠getbackinthe.kitchen

I've been running coreboot on my T440P and trying to fix it up. I have already resolved some things here: https://github.com/Ph0rk0z/coreboot/pulls Will have to figure out how to contribute this back to coreboot after testing so it can pass code review. Other things remain, including: - software changing of keyboard backlight doesn't work on windows (but I fixed it on linux) - lenovo hotkey / mic mute services crash windows (bad pool_caller) - intel haswell -mini hd audio shows exclamation point, will not start. I've read others don't have DP audio working either. - there is an unknown ACPI\VEN_BOOT@DEV_0000 device - card reader doesn't work in windows/linux and crashes windows on warm boot - plug/unplug ac under bios and windows causes screen to go dark for a second - occasionally power button light turns off (fixed by suspend) - TLP stats for charge mAH are off by a factor of 10. - tianocore picks up the windows loader as a boot option but doesn't pick up arch linux, old bios enumerated both. - tianocore menus/graphics are only what looks like 640x480 and don't take up the screen I'd like to solve the card reader issue but not sure where to start. It appears correctly detected and matches everything on my x250. Any hints to what I should look at?

7 months, 3 weeks

X200 dock has been broken since November 2019

by Kevin Keijzer

I have a couple of X200's, all running coreboot 4.10. The dock works fine there. When I press the undock button (either on the side or with Fn+F9), the system undocks, and when I put the laptop back in the dock, the led goes red again, and the USB ports start working again. The same happens when the system is suspended and resumed. However, since coreboot 4.11, the re-docking part is completely broken. I can press the undock button(s), which work fine, but when I re-dock the laptop, the led remains green and USB does not work. Also, when I suspend and resume the laptop, the system undocks immediately after resuming from S3, even though no button was pressed and it's still physically docked. The only way to recover from this is by rebooting. In coreboot 4.13, this bug is still present. So I decided to bisect the issue, and I found the offending commit: 96ae7a3a2d38b96c1dfee57fda2c2eaab7e9e762 is the first bad commit commit 96ae7a3a2d38b96c1dfee57fda2c2eaab7e9e762 Author: Bill XIE <persmule(a)hardenedlinux.org> Date: Wed Oct 16 23:22:10 2019 +0800 mb/lenovo/x200: Add ThinkPad X301 as a variant It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. https://review.coreboot.org/c/coreboot/+/36093 Looking at the changes, this seems pretty plausible. I would like to get coreboot 4.14 running properly again with docked X200's, but I'm not sure (yet) what the exact cause of the breakage is. -- With kind regards, Kevin Keijzer

7 months, 3 weeks

New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1447050: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/haswell/northbridge.c: 301 in mc_add_dram_resources() ________________________________________________________________________________________________________ *** CID 1447050: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/haswell/northbridge.c: 301 in mc_add_dram_resources() 295 size_k = (0xa0000 >> 10) - base_k; 296 ram_resource(dev, index++, base_k, size_k); 297 298 /* 0xc0000 -> TSEG - DPR */ 299 base_k = 0xc0000 >> 10; 300 size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; >>> CID 1447050: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "dpr.size >> 10" is 0 regardless of the values of its operands. This occurs as the operand of assignment. 301 size_k -= dpr.size >> 10; 302 ram_resource(dev, index++, base_k, size_k); 303 304 /* TSEG - DPR -> BGSM */ 305 resource = new_resource(dev, index++); 306 resource->base = mc_values[TSEG_REG] - dpr.size; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

7 months, 3 weeks

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coreboot February 2021