coreboot February 2021

coreboot@coreboot.org

42 participants
35 discussions

Coreboot and Tianocore
by techmindams04＠gmail.com 06 Feb '21

06 Feb '21

Hi, I have generated a payload from edk2 2017. When i booting with payload i got struck after the below message. The keyboard is not detecting so i can't press any key. Mouse got powered up. Even i exchanged the usb ports but still keyboard not detecting. I am using coreboot and edk2 payload. I am using Coffeelake processor. If i use the uefi payload binary from Intel. Everything is working and able to select device in the boot manager and load OS. LastBlock : 4FFFFF [0m[37m[40m F2 or Down to enter Boot Manager Menu. ENTER to boot directly. [Bds]OsIndication: 0000000000000000 [Bds]=============Begin Load Options Dumping ...============= Driver Options: SysPrep Options: Boot Options: Boot0000: UiApp 0x0109 Boot0001: UEFI SM659GXC CDZ A0519022617060000001 0x0001 Boot0002: UEFI Shell 0x0001 PlatformRecovery Options: PlatformRecovery0000: Default PlatformRecovery 0x0001 [Bds]=============End Load Options Dumping============= [Bds]BdsWait ...Zzzzzzzzzzzz... [Bds]BdsWait(3)..Zzzz...

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 05 Feb '21

05 Feb '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 3 new defect(s) introduced to coreboot found with Coverity Scan. 2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 1445995: Code maintainability issues (UNUSED_VALUE) /src/arch/x86/acpi_bert_storage.c: 534 in bert_new_event() ________________________________________________________________________________________________________ *** CID 1445995: Code maintainability issues (UNUSED_VALUE) /src/arch/x86/acpi_bert_storage.c: 534 in bert_new_event() 528 if (!status) 529 return NULL; 530 531 status->raw_data_length = sizeof(*status); 532 533 if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) >>> CID 1445995: Code maintainability issues (UNUSED_VALUE) >>> Assigning value from "bert_append_genproc(status)" to "r" here, but that stored value is overwritten before it can be used. 534 r = bert_append_genproc(status); 535 else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) 536 r = bert_append_ia32x64(status); 537 if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) 538 r = bert_append_fw_err(status); 539 /* else if other types not implemented */ ** CID 1445994: Integer handling issues (BAD_SHIFT) /src/soc/amd/common/block/acpi/pm_state.c: 21 in get_index_bit() ________________________________________________________________________________________________________ *** CID 1445994: Integer handling issues (BAD_SHIFT) /src/soc/amd/common/block/acpi/pm_state.c: 21 in get_index_bit() 15 uint32_t t; 16 17 if (limit > TOTAL_BITS(uint32_t)) 18 return -1; 19 20 /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ >>> CID 1445994: Integer handling issues (BAD_SHIFT) >>> In expression "1 << limit", left shifting by more than 31 bits has undefined behavior. The shift amount, "limit", is as much as 32. 21 t = (1 << limit) - 1; 22 if ((value & t) == 0) 23 return -1; 24 t = 1; 25 for (i = 0; i < limit; i++) { 26 if (value & t) ** CID 1445993: Code maintainability issues (UNUSED_VALUE) /src/arch/x86/acpi_bert_storage.c: 536 in bert_new_event() ________________________________________________________________________________________________________ *** CID 1445993: Code maintainability issues (UNUSED_VALUE) /src/arch/x86/acpi_bert_storage.c: 536 in bert_new_event() 530 531 status->raw_data_length = sizeof(*status); 532 533 if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) 534 r = bert_append_genproc(status); 535 else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID)) >>> CID 1445993: Code maintainability issues (UNUSED_VALUE) >>> Assigning value from "bert_append_ia32x64(status)" to "r" here, but that stored value is overwritten before it can be used. 536 r = bert_append_ia32x64(status); 537 if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) 538 r = bert_append_fw_err(status); 539 /* else if other types not implemented */ 540 else 541 r = NULL; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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[Events] Talk about coreboot on POWER + vBeer online party!
by Mike Banon 04 Feb '21

04 Feb '21

Dear friends, Next Thursday __4th Feb at 3PM GMT__ , 3mdeb invites you to talk about the POWER9 support in coreboot opensource BIOS - https://meet.google.com/xsy-ocfw-exm . You are going to learn: 1) great benefits a coreboot will deliver to POWER-based PCs; 2) our progress and interesting challenges we are facing; 3) unique features of Dasharo coreboot-based firmware. Also, soon we are having a vBeer online party! Will be happy to discuss the open/libre firmwares (coreboot, Dasharo, etc.), related hardwares and other nice embedded things you have in mind. Please visit http://live.evenea.com/3mdeb-vbeer at 18th Feb 3PM GMT to have some fun with us. -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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DP (Display Port) not enumerating in OS
by Rao G 03 Feb '21

03 Feb '21

Hello Coreboot Developers, Display port which comes along with Integrated LVDS, does not show up any OS graphics display text or screen after booting to OS, the DP port looks good during BIOS, at some point of time during OS booting display port turns off and no video on DP. Using ubuntu 18.04 Some ASL code for graphics is missing? HDMI, DVI & LVDS works well, no issue there Thanks for your time and any clues that would help to resolve this issue? Kind Regards Rao

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 02 Feb '21

02 Feb '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1445928: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/amd/picasso/data_fabric.c: 178 in data_fabric_set_indirect_address() ________________________________________________________________________________________________________ *** CID 1445928: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/amd/picasso/data_fabric.c: 178 in data_fabric_set_indirect_address() 172 { 173 uint32_t fabric_indirect_access_reg = DF_IND_CFG_INST_ACC_EN; 174 /* Register offset field [10:2] in this register corresponds to [10:2] of the 175 requested offset. */ 176 fabric_indirect_access_reg |= reg & DF_IND_CFG_ACC_REG_MASK; 177 fabric_indirect_access_reg |= >>> CID 1445928: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "(func << 11) & (28 /* 7 << 2 */)" is always 0 regardless of the values of its operands. This occurs as the bitwise operand of "|". 178 (func << DF_IND_CFG_ACC_FUN_SHIFT) & DF_IND_CFG_ACC_FUN_MASK; 179 fabric_indirect_access_reg |= instance_id << DF_IND_CFG_INST_ID_SHIFT; 180 pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, fabric_indirect_access_reg); 181 } 182 183 uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id) ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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coreboot February 2021