May 2025 - coreboot - mail.coreboot.org

[coreboot - Bug #592] (New) Lenovo M920q can't use DIMM2 RAM slot
by Coreboot Enjoyer June 10, 2025

June 10, 2025

Issue #592 has been reported by Coreboot Enjoyer. ---------------------------------------- Bug #592: Lenovo M920q can't use DIMM2 RAM slot https://ticket.coreboot.org/issues/592 * Author: Coreboot Enjoyer * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2025-04-15 * Affected versions: main * Related links: https://github.com/Thrilleratplay/coreboot-builder-scripts/issues/33 Also, it looks like a similar issue to https://ticket.coreboot.org/issues/462 * Affected hardware: Lenovo M920q ---------------------------------------- Building the current coreboot source, as well as commits 497298708c330deb479fbf3ee6a3acc8bff2a102, 640a41f3ee938b794b140218921e0fd63b1d9235 and 7945a31e9172ec2939cc1abc6036962a6efb601b, produces the firmware, that allows to initialize the motherboard if only DIMM1 RAM slot is filled. It fails to initialize, if DIMM1 RAM slot is empty and DIMM2 is filled, as well as if both DIMM1 and DIMM2 are filled. The issue is reproducible with different RAM sticks. I tried every possible combination with Kingston 32GB (2666MHz, CL 19-19-19-43) and Samsung 8GB (2400MHz, CL 17-17-17-39) -- the motherboard recognizes RAM sticks correctly, but still fails when the DIMM2 is filled with any RAM stick. I have also attached the build config file, which uses most of the default options. ---Files-------------------------------- m920q-dimm2-config.txt (27.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Coreboot Rabbit Logo
by Eneko X June 5, 2025

June 5, 2025

"### [Martin] We need a name for the coreboot rabbit logo * Currently, we typically refer to it as "the coreboot logo," and I think it would be great to assign it a unique name to make it stand out. Here are a few suggested names: Rabbot, Harry, Rabby, and Harry Hare." I Would Name it Peter Peter the Rabbit

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2025-05-28 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org May 29, 2025

May 29, 2025

# 2025-05-28 - coreboot Leadership Meeting ## Attendees Mina Asante, Jon Murphy, David Hendricks, Martin Roth, Werner Zeh, Julius Werner, Alicja Michalska, Matt DeVillier, Ziang Wang, Jay Talbott, Maximilian Brune. ## Open Action Items * 2025-05-28 * [Open] Martin: Create DevBD branch * 2025-05-14 * [Open] Martin: Review the list of people with +2 rights and update it before the next release. * 2024-11-27 * [Open] Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * [Open] Add clarification to docs, “do not use gerrit change-id or CB: format in reference to already-merged patches.” * 2024-10-16 * [Open] Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * [Open] Jon: Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * [Open] Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian(?) * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * [Open] Daniel: Look at how we want to localize (non-console) strings for coreboot. Long-term project. ## Minutes ### [Martin] We need a name for the coreboot rabbit logo * Currently, we typically refer to it as "the coreboot logo," and I think it would be great to assign it a unique name to make it stand out. Here are a few suggested names Rabbot, Harry, Rabby, Harry Hare. * Suggested names from the mailing list: Corebunny, Corry, Peter, The Rabbit of Corebannog, Peter Rabbit, Speedy The Rabbit, Speedy. * [David] Perplexity suggests "Blitz" which translates well between English and German. * Put up a poll - Should we name the coreboot rabbit, what’s a good name? ### [Martin] I’d like to propose setting up a dedicated google chat group for everyone attending the leadership meetings. This group would be used to share updates, important info, and reminders before and during the meetings. * [martin] Does this split the discussion even further? * We have discord, irc, slack, mailing list already. * Julius: Make this a general chat for coreboot? * Set up matrix with bridges to various services? Is there a bridge to google chat? * [Werner] Promote one of the existing channels to be the “official” channel. Educate people to report issues here. Which channel? Slack, discord, irc? * Let’s look at solutions to bridge the services and join the community again. ### [Ziang] Leadership meeting in Asia time * Greetings, everyone! not sure if it’s appropriate for me to show up here, but FWIW I’d like to run the Asia leadership meeting if it is still on track. We could gather companies in the APAC area and schedule a bi-weekly call. Project sync or upstream plan would have a right place to be carried out in this way. * This sounds great. What time? * Maybe afternoon in China so people in India can attend? * Probably want to do the meeting in English? * 7:00-7:30AM GMT+2 can work for Werner (Germany) * 2pm China time. * Need to formalize way to set up branches and repos * Create DevBD branch [martin] ### [Max] GCC 15 is still causing issues. As more distributions are now moving to GCC 15, this is getting to be an increasingly annoying problem. * In order to build the toolchain again: (https://review.coreboot.org/c/coreboot/+/87650) * In order to build coreboot again: (https://review.coreboot.org/c/coreboot/+/87656) * compiling clang is still a problem * Can we make a macro to handle the differences between gcc 14 & 15 * Can’t build clang when gcc15 is the system toolchain * Need to figure out how to use other toolchains to build clang. * Publish a document on how to use older system toolchains to build the coreboot toolchain. ### Information * The mailing list software has been upgraded and we've got a new set of build servers to lower the cost. * The next release is scheduled for just over 3 weeks - June 20th. # Next Leadership Meeting * June 11, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice Decisions shown here are not necessarily final and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda, and show up if possible to discuss it. Of course, items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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[coreboot - Bug #596] (New) Allocate resources from top down AND extend PCIe resource window above 4G together breaks libgfxinit bootscreen
by Walter Sonius May 28, 2025

May 28, 2025

Issue #596 has been reported by Walter Sonius. ---------------------------------------- Bug #596: Allocate resources from top down AND extend PCIe resource window above 4G together breaks libgfxinit bootscreen https://ticket.coreboot.org/issues/596 * Author: Walter Sonius * Status: New * Priority: Normal * Target version: none * Start date: 2025-05-19 * Affected versions: 25.03 ---------------------------------------- When enabling both `Allocate resources from top down` [enabled by default and fixed recently](https://review.coreboot.org/c/coreboot/+/87504) and `Extend resource window for PCIe devices above 4G` libgfxinit will break during bootscreen and other PCIe issues like failing wifi drivers may occur. Tested coreboot-25.03-519-ga2010cf5eeea (a2010cf5eeea6ad4a154cfb13760092f0865af3f) with Dell_Optiplex_5040_sff (i3-6100) and earlier Coreboot 25.03-467-gf0ad05b57ebe with Lenovo [x201](https://ticket.coreboot.org/issues/548#note-10) with MrChromeBox EDK2 2502. Can/should these 2 options be used together, if I understand correctly when using a modern efi GOP dGPU together with resizeable-bar all 3 options(+Support PCIe Resizable BARs) need to be enabled? Only using `Allocate resources from top down` or `Extend resource window for PCIe devices above 4G` does not lead up to this issue. ---Files-------------------------------- cb-log-dell-5040-sff-notd-a4b-ok-bootscreen.txt (41 KB) cb-log-dell-5040-sff-td-noa4b-ok-bootscreen.txt (41 KB) cb-log-dell-5040-sff-td-a4b-no-bootscreen.txt (40.5 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org May 26, 2025

May 26, 2025

Dear coreboot Community, Please be reminded that we have an upcoming leadership meeting scheduled for Wednesday, May 28, 2025. [1] Kindly take a moment to update the agenda with matters you wish to see addressed during the meeting. [2] Thank you. ## Agenda ### [Martin] We need a name for the coreboot rabbit logo * Currently, we typically refer to it as "the coreboot logo," and I think it would be great to assign it a unique name to make it stand out. Here are a few suggested names: Rabbot, Harry, Rabby, and Harry Hare. ### [Martin] I’d like to propose setting up a dedicated google chat group for everyone attending the leadership meetings. This group would be used to share updates, important info, and reminders before and during the meetings. ### Info: The mailing list software has been upgraded, and we've got a new set of build servers to lower the cost. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org May 23, 2025

May 23, 2025

Dear coreboot Community, Kindly note that our next leadership meeting is scheduled for Wednesday, May 28, 2025. [1] Please take a moment to update the agenda with matters you wish to see addressed during the meeting. [2] Thank you. Best regards, Mina Asante. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Support #597] (New) success mb/dell: OptiPlex 5040 SFF works with adjusted Optiplex 3050 Micro code port
by Walter Sonius May 20, 2025

May 20, 2025

Issue #597 has been reported by Walter Sonius. ---------------------------------------- Support #597: success mb/dell: OptiPlex 5040 SFF works with adjusted Optiplex 3050 Micro code port https://ticket.coreboot.org/issues/597 * Author: Walter Sonius * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2025-05-19 * Affected versions: 25.03 ---------------------------------------- Not sure to put this under support or refactoring, since adding this code to upstream coreboot using gerrit may look straight forward and easy to have a nice working optiplex_5040 port. My concern is however that the original `dell/optiplex_3050` code might need to be refactored into a variant first before this code will be accepted and that refactoring may be to much for me as a newbie. But it works... it works really well indeed. By mostly reusing `dell/optiplex_3050` port code which takes care of handling some variants 'SFF/MICRO' hinted by 'ramstage.c' for its own 3050 series itself, I just reused all of the code which I mostly don't understand and therefor may be wrong to put that as NEW board into the code tree. Although I have 'autoport logs' made for my 'optiplex_5040_sff' I don't know how to translate/apply correct that to my model(if needed). But since you have to start somewhere, and autoport only made logs I therefor just want to share this code and progress. Specs: Dell Optiplex 5040 SFF Motherboard: DP/N 0T7D40, CN-0T7D40-72200, 588-00HF-A00 OEM BIOS version: 1.22.0 03/16/2022 Reg Model: D11S Reg Type: D11S001 Service tag: HPR6C92 CPU: i3-6100 This Optiplex 5040 SFF motherboard looks very similar to the 3050 SFF(shares the same OEM BIOS as the 3050 micro) except for the following visual differences: 4 DDR3L slots vs 2 DDR4 slots (DDR4-sodimm on the micro) 1 PCIe 4x length (open) black slot vs 1x length (closed), micro none 3 SATA connectors vs 2 SATA (black missing), micro one 4 USB3 back ports vs 2 USB3 2 DisplayPorts vs 1 DisplayPort 1 serial vs 0 serial port 1 VGA(using motherboard header) vs 0 VGA 2 PS2 vs 0 PS2 ports Q170 chipset vs B250 chipset First the initial deguard requirement was the same for my optiplex_5040 sff as for the optiplex_3050 micro, as well as flashing or recovery. A minor edit to the [deguard code](https://ticket.coreboot.org/issues/588) is necessary to complete the deguard instruction. With the following crucial edits to the 'optiplex_3050' port its 'Kconfig', 'romstage.c' and minor edits to the existing 'devicetree.cb' almost everything started working: First hang on RAM issue ["[EMERG] FspMemoryInit error, status=0x80000007"](https://ticket.coreboot.org/issues/594) was fixed by adjusting 'Kconfig' `config DIMM_SPD_SIZE` from `default 512 # DDR4` to `256 # DDR3` and editing 'romstage.c' with additional addresses and changing `CaVrefConfig 2` to `0` made all 4 DIMM slots work: ``` > struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53 } }; mem_cfg->DqPinsInterleaved = 1; > mem_cfg->CaVrefConfig = 0; mem_cfg->MemorySpdDataLen = blk.len; > mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; > mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; > mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; > mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; ``` By some additional edits to 'devicetree.cb' all PCIe slots(16x,4x,M2-ssd), all USB2&3 ports, all SATA ports and both PS2 ports started to function. Only the USB OC values have my concern, don't know what they stand for. ``` > # SLOT2 x16 > device ref peg0 on > register "Peg0MaxLinkWidth" = "Peg0_x16" > > # Configure PCIe clockgen in PCH > register "PcieRpClkReqSupport[0]" = "1" > register "PcieRpClkReqNumber[0]" = "0" > register "PcieRpClkSrcNumber[0]" = "0" > end > --- > device ref south_xhci on > register "usb2_ports" = "{ > [0] = USB2_PORT_MID(OC0), // Front panel (blue) > [1] = USB2_PORT_MID(OC0), // Front panel (blue) > [2] = USB2_PORT_MID(OC3), // Back panel (blue) > [3] = USB2_PORT_MID(OC2), // Back panel (blue) > [4] = USB2_PORT_MID(OC1), // Back panel (blue) > [5] = USB2_PORT_MID(OC1), // Back panel rightup (black) > [6] = USB2_PORT_MID(OC1), // Back panel (blue) > [7] = USB2_PORT_MID(OC1), // Back panel rightlow (black) > [8] = USB2_PORT_MID(OC_SKIP), // Front Panel rightlow (black) > [9] = USB2_PORT_MID(OC_SKIP), // Front Panel rightup (black) > > }" > register "usb3_ports" = "{ > [0] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) > [1] = USB3_PORT_DEFAULT(OC0), // Front panel (blue) > [2] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) > [3] = USB3_PORT_DEFAULT(OC2), // Back panel (blue) > [4] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) > [5] = USB3_PORT_DEFAULT(OC1), // Back panel (blue) > }" > end --- > register "SataPortsEnable[1]" = "1" > register "SataPortsEnable[2]" = "1" --- < device ref pcie_rp21 on < register "PcieRpClkReqSupport[20]" = "1" < register "PcieRpClkReqNumber[20]" = "3" < register "PcieRpAdvancedErrorReporting[20]" = "1" < register "PcieRpLtrEnable[20]" = "true" < register "PcieRpClkSrcNumber[20]" = "3" < register "PcieRpHotPlug[20]" = "1" < end < < # Realtek LAN < device ref pcie_rp5 on < register "PcieRpClkReqSupport[4]" = "0" < register "PcieRpHotPlug[4]" = "0" < end < < # M.2 WiFi < device ref pcie_rp8 on < register "PcieRpClkReqSupport[7]" = "0" < register "PcieRpHotPlug[7]" = "1" --- > # SLOT3_M.2 > device ref pcie_rp17 on > register "PcieRpClkReqSupport[16]" = "1" > register "PcieRpClkReqNumber[16]" = "3" > register "PcieRpAdvancedErrorReporting[16]" = "1" > register "PcieRpLtrEnable[16]" = "true" > register "PcieRpClkSrcNumber[16]" = "3" > register "PcieRpHotPlug[16]" = "1" > end > > # SLOT1 x4 > device ref pcie_rp9 on > register "PcieRpClkReqSupport[8]" = "0" > register "PcieRpHotPlug[8]" = "1" > end --- > device pnp 2e.1 on # 8042 > io 0x60 = 0x60 > irq 0x0f = 0 > irq 0x70 = 1 > irq 0x72 = 12 > end --- > chip drivers/pc80/tpm > device pnp 0c31.0 on end > end --- > device ref gbe on end ``` Also TPM2 and onboard ethernet came alive with final edits to 'Kconfig': ``` > select MAINBOARD_HAS_TPM2 > select MEMORY_MAPPED_TPM > select MAINBOARD_USES_IFD_GBE_REGION ``` All audio ports including chassis speaker(soundcard) work using unchanged optiplex_3050 code, however autoport logs ran on OEM show different codec(chipset) and parameters for the 5040_sff compared to 3050 micro this may need to be alterned for correctness? Video output was unreliable until I replaced 'data.vbt' with the one extracted from original Dell Optiplex 5040 SFF 1.22 OEM bios (debugfs) and altered 'gma-mainboard.ads' to have HDMI and 2 DisplayPorts working perfectly. Only the VGA port, which is shown as 3rd DisplayPort (xrandr) uses the original motherboard breakout to the chassis VGA won't work at all (port not detected no BOOT nor OS). ``` ports : constant Port_List := (HDMI1, -- External HDMI DP2, -- External DP (bottom) DP1, -- External DP (top) DP3, -- External VGA (opt. breakout cable) others => Disabled); ``` Tested this on coreboot-25.03-519-ga2010cf5eeea both SeaBIOS 1.16.3 and EDK2 MrChromeBox 2502 payloads booting KDE NEON Linux 6.11 fine. Besides the "VGA port" only "Wake for LAN" isn't working for me yet every other port/connection/slot does work even combined iGPU and dGPU, leds, and CPU Fan speed also varies boot/restart. My concern is with the USB OC values, allot of GPIO values copied from the 3050 port and not correct to autoport and other stuff I might overlook. Feel free to check the added drop in optiplex_5040_sff.zip file with mostly a copy of 3050 micro port code to build a functional optiplex_5040_sff target or spin a variant into gerrit which I can assist and confirm testing. ---Files-------------------------------- autoport-corebooted-dell_optiplex_5040_sff.zip (208 KB) autoport-OEM122-dell_optiplex_5040_sff-deguard.zip (419 KB) optiplex_5040_sff.zip (14 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2025_05_21 coreboot Review Session
by mina＠coreboot.org May 19, 2025

May 19, 2025

Hello coreboot, Please be reminded that our upcoming group review session is scheduled for Wednesday, May 21, 2025. https://meet.google.com/kpu-yozw-gtt Check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html Here is the link to the list of patches to be reviewed this week: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…) Add any specific patches you'd like the group to review to the top of the sheet. As an hour is not sufficient to address all patches on the list, reviewing patches in advance is greatly appreciated. Thank you. Best regards, Mina.

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Adding Support to Dell Latitude 5420
by Eneko X May 18, 2025

May 18, 2025

Can you add support for Dell Latitude 5420 please, I still haven't dumped the laptop bios but i can still do it in the future

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[coreboot - Support #594] (New) "[EMERG] FspMemoryInit error, status=0x80000007" on Dell Optiplex 5040 SFF (0T7D40) using optiplex_3050 port code
by Walter Sonius May 17, 2025

May 17, 2025

Issue #594 has been reported by Walter Sonius. ---------------------------------------- Support #594: "[EMERG] FspMemoryInit error, status=0x80000007" on Dell Optiplex 5040 SFF (0T7D40) using optiplex_3050 port code https://ticket.coreboot.org/issues/594 * Author: Walter Sonius * Status: New * Priority: Normal * Target version: none * Start date: 2025-04-28 * Affected versions: 25.03 * Affected hardware: Dell Optiplex 5040 SFF ---------------------------------------- To further test the "deguard", just tried to flash this unsupported `optiplex_3050` code on the Dell Optiplex 5040 SFF and results in this error. **[EMERG] FspMemoryInit error, status=0x80000007** The Dell Optiplex 3050 micro shares the same OEM BIOS file as the Optiplex 3050 SFF. Since the later board looks very similar tot the Optiplex 5040 SFF except for these obvious differences: 2 DDR4 (DDR4-sodimm on the micro) slots vs 4 DDR3L slots 1 PCIe 1x length (closed) vs 4x length (open) black slots 2 SATA (black missing) vs 3 SATA connectors 2 USB3 vs 4 USB3 back ports 1 DisplayPort vs 2 DisplayPorts 0 serial vs 1 serial port 0 VGA vs 1 VGA(using motherboard header) 0 PS2 vs 2 PS2 ports B250 chipset vs Q170 chipset I took the gamble and flashed the 3050 micro port, just by adding the "Flash descriptor", "ME" and "Igbe" regions of the working [Optiplex 5040 SFF deguarded ROM](https://ticket.coreboot.org/issues/588) and only inserting pci 1f6 and peg0 to the devicetree.cb all other code is untouched. ``` ... device domain 0 on + device ref peg0 on + register "Peg0MaxLinkWidth" = "Peg0_x16" + + # Configure PCIe clockgen in PCH + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + end device ref igpu on register "PrimaryDisplay" = "Display_iGFX" end ... ... device ref hda on end device ref smbus on end + device pci 1f.6 on end # GbE <--- Extra port which contains I219-V but disabled also works on Asrock H110 Pro BTC+ end ... ``` The boards serial output works and it detects RAM only in 2 of 4 slots that resemble the 3050 SFF. Also correct sizes 2GB, 4GB, 8GB and variants including DDR3 vs DDR3L gets correctly detected. Different CPU's will also run Skylake i3-6100T, Kabylake G3950 and Coffeelake G4900T. ``` [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32. [DEBUG] CPU: Intel(R) Core(TM) i3-6100T CPU @ 3.20GHz [DEBUG] CPU: ID 506e3, Skylake H R0, ucode: 000000ef [DEBUG] CPU: AES supported, TXT NOT supported, VT supported [DEBUG] MCH: device id 190f (rev 07) is Skylake-S (2 Core) [DEBUG] PCH: device id a146 (rev 31) is Q170 [DEBUG] IGD: device id 1912 (rev 06) is Skylake DT GT2 [WARN ] PMC: Duplicate GPE DW register values detected; using default GPE route frr [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x750000. [DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 8 [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: mcache @0xfef04e00 built for 16 files, used 0x364 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x9d1c0 size 0xd0f0 in mcache @0xfef04e8c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 87 ms [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32. [WARN ] HECI: CSE device 16.0 is disabled [DEBUG] pm1_sts: 0900 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 [DEBUG] TCO_STS: 0000 0001 [DEBUG] GEN_PMCON: d0050200 00003008 [DEBUG] GBLRST_CAUSE: 00000002 00000000 [DEBUG] prev_sleep_state 0 (S0) [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: Found 'fspm.bin' @0xcddc0 size 0x63000 in mcache @0xfef0503c [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [NOTE ] MRC: no data in 'RW_MRC_CACHE' [DEBUG] SPD @ 0x50 [INFO ] SPD: module type is DDR3 [INFO ] SPD: module part number is HMT41GU6MFR8C-PB [INFO ] SPD: banks 8, ranks 2, rows 16, columns 10, density 4096 Mb [INFO ] SPD: device width 8 bits, bus width 64 bits [INFO ] SPD: module size is 8192 MB (per channel) [DEBUG] SPD @ 0x52 [INFO ] SPD: module type is DDR3 [INFO ] SPD: module part number is HMT41GU6MFR8C-PB [INFO ] SPD: banks 8, ranks 2, rows 16, columns 10, density 4096 Mb [INFO ] SPD: device width 8 bits, bus width 64 bits [INFO ] SPD: module size is 8192 MB (per channel) [EMERG] FspMemoryInit error, status=0x80000007 ``` Kabylake just with one Dimm inserted: ``` [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32 bootblock starting (log level: 7)... [DEBUG] CPU: Intel(R) Celeron(R) CPU G3950 @ 3.00GHz [DEBUG] CPU: ID 906e9, Kabylake H B0, ucode: 000000f7 [DEBUG] CPU: AES supported, TXT NOT supported, VT supported [DEBUG] MCH: device id 590f (rev 06) is Kabylake-S [DEBUG] PCH: device id a146 (rev 31) is Q170 [DEBUG] IGD: device id 5902 (rev 04) is Kaby Lake DT GT1F [WARN ] PMC: Duplicate GPE DW register values detected; using default GPE route from MISCCFG register [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x750000. [DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 8 [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: mcache @0xfef04e00 built for 16 files, used 0x364 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x9d1c0 size 0xd0f0 in mcache @0xfef04e8c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 88 ms [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32 romstage starting (log level: 7)... [WARN ] HECI: CSE device 16.0 is disabled [DEBUG] pm1_sts: 0800 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 [DEBUG] TCO_STS: 0000 0001 [DEBUG] GEN_PMCON: d0040200 0000700a [DEBUG] GBLRST_CAUSE: 00000000 00000000 [DEBUG] prev_sleep_state 5 (S5) [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: Found 'fspm.bin' @0xcddc0 size 0x63000 in mcache @0xfef0503c [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [NOTE ] MRC: no data in 'RW_MRC_CACHE' [INFO ] No memory dimm at address A4 [DEBUG] SPD @ 0x50 [INFO ] SPD: module type is DDR3 [INFO ] SPD: module part number is HMT41GU6MFR8C-PB [INFO ] SPD: banks 8, ranks 2, rows 16, columns 10, density 4096 Mb [INFO ] SPD: device width 8 bits, bus width 64 bits [INFO ] SPD: module size is 8192 MB (per channel) [EMERG] FspMemoryInit error, status=0x80000007 ``` Coffeelake with just 1 Dimm inserted: ``` [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32 bootblock starting (log level: 7)... [DEBUG] CPU: Intel(R) Celeron(R) G4900T CPU @ 2.90GHz [DEBUG] CPU: ID 906eb, Unknown, ucode: 000000f5 [DEBUG] CPU: AES supported, TXT NOT supported, VT supported [DEBUG] MCH: device id 3e0f (rev 08) is Unknown [DEBUG] PCH: device id a146 (rev 31) is Q170 [DEBUG] IGD: device id 3e93 (rev 00) is Unknown [WARN ] PMC: Duplicate GPE DW register values detected; using default GPE route from MISCCFG register [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x750000. [DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 8 [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: mcache @0xfef04e00 built for 16 files, used 0x364 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x9d1c0 size 0xd0f0 in mcache @0xfef04e8c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 86 ms [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32 romstage starting (log level: 7)... [WARN ] HECI: CSE device 16.0 is disabled [DEBUG] pm1_sts: 0800 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 [DEBUG] TCO_STS: 0000 0001 [DEBUG] GEN_PMCON: d0040200 0000700a [DEBUG] GBLRST_CAUSE: 00000000 00000000 [DEBUG] prev_sleep_state 5 (S5) [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: Found 'fspm.bin' @0xcddc0 size 0x63000 in mcache @0xfef0503c [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [NOTE ] MRC: no data in 'RW_MRC_CACHE' [INFO ] No memory dimm at address A4 [DEBUG] SPD @ 0x50 [INFO ] SPD: module type is DDR3 [INFO ] SPD: module part number is HMT41GU6MFR8C-PB [INFO ] SPD: banks 8, ranks 2, rows 16, columns 10, density 4096 Mb [INFO ] SPD: device width 8 bits, bus width 64 bits [INFO ] SPD: module size is 8192 MB (per channel) [EMERG] FspMemoryInit error, status=0x80000007 No Dimms at all inserted or other 2 unsupported banks used [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32 bootblock starting (log level: 7)... [DEBUG] CPU: Intel(R) Celeron(R) G4900T CPU @ 2.90GHz [DEBUG] CPU: ID 906eb, Unknown, ucode: 000000f5 [DEBUG] CPU: AES supported, TXT NOT supported, VT supported [DEBUG] MCH: device id 3e0f (rev 08) is Unknown [DEBUG] PCH: device id a146 (rev 31) is Q170 [DEBUG] IGD: device id 3e93 (rev 00) is Unknown [WARN ] PMC: Duplicate GPE DW register values detected; using default GPE route from MISCCFG register [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x750000. [DEBUG] FMAP: base = 0x0 size = 0x1000000 #areas = 8 [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: mcache @0xfef04e00 built for 16 files, used 0x364 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x9d1c0 size 0xd0f0 in mcache @0xfef04e8c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 86 ms [NOTE ] coreboot-25.03-324-geffd1ffdad73-dirty Mon Apr 28 05:44:45 UTC 2025 x86_32 romstage starting (log level: 7)... [WARN ] HECI: CSE device 16.0 is disabled [DEBUG] pm1_sts: 0800 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 [DEBUG] TCO_STS: 0000 0001 [DEBUG] GEN_PMCON: d0040200 0000700a [DEBUG] GBLRST_CAUSE: 00000000 00000000 [DEBUG] prev_sleep_state 5 (S5) [DEBUG] FMAP: area COREBOOT found @ 750200 (9108992 bytes) [INFO ] CBFS: Found 'fspm.bin' @0xcddc0 size 0x63000 in mcache @0xfef0503c [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [NOTE ] MRC: no data in 'RW_MRC_CACHE' [INFO ] No memory dimm at address A0 [INFO ] No memory dimm at address A4 [EMERG] FspMemoryInit error, status=0x80000007 ``` Will upload autoport logs soon, anyone already some obvious edits/hints to the existing [optiplex_3050 code](https://github.com/coreboot/coreboot/tree/main/src/mainboard/dell/opt… get me past this [EMERG] FspMemoryInit error, status=0x80000007 error? -- You have received this notification because you have either subscribed to it, or are involved in it. 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