coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

by Masoud Fatollahy

Hi, Why is it problem to boot from an usb port when we are using linuxbios and filo. as I can see all usb code are there, what is missing? Thanks, /Masoud

10 years, 9 months

[LinuxBIOS] Add initial support for intel i855gme northbridge

by Jon Dufresne

Add initial support for i855gme. This is a work in progress and I don't expect it to work on all boards, or even any besides mine. This is based heavily on i855pm. Signed off by Jon Dufresne <jon.dufresne(a)gmail.com>

12 years, 4 months

[LinuxBIOS] A8N5X port

by Robert Millan

This patch includes config files for the asus/a8n5x port. It is the same as asus/a8n_e with a different pnp layout, so I used #include's whenever possible. System boots and is usable with usb keyboard. works: - serial port - vga (old pci card) - memtest86+ succeeds, but only with Rudolf's patch for unbuffered dimms in K8. Otherwise you get spurious memory corruption. - ide disk - usb doesn't: - ps/2 keyboard - onboard ethernet - vga pci-e card (??) - any other pci card I tried wasn't tested: - sata - game port - onboard audio (not supported by alsa anyway) - ps/2 mouse -- Robert Millan <GPLv2> I know my rights; I want my phone call! <DRM> What use is a phone call, if you are unable to speak? (as seen on /.)

12 years, 6 months

LZMA magic number

by Myles Watson

Is there a magic number for LZMA? Should there be? I accidentally used an uncompressed payload with v2 when it expected a compressed payload, and it gave me the message: Decoder scratchpad too small!! Decoding error = 1 I think it would be nicer to have an error like: Payload not compressed with lzma! Myles

12 years, 8 months

some thoughts on dts vs. Kconfig vs. makefiles vs. C code

by ron minnich

I have no idea if this helps. But there's been discussion of "DRAM settings in DTS" and "where does CARBASE go" and so on, so I think we need to try to document some rules. Here is a first cut. thanks ron

12 years, 11 months

flashrom verify fails, CK804, MCP55

by Tiago Marques

On two boards, one MCP55 based and another CK804, if I flash the proprietary BIOS with: flasrom -wv bios.bin Verification fails and if I try to boot, it doesn't. Have to flash the BIOS in another board based on K8T890 that I have. In that one all works fine, with both BIOS chips I have - one winbond and a PMC. Haven't tried flashing coreboot due to lack of support. Since the chipsets are support, this isn't supposed to happen, right? Best regards, Tiago Marques On 1/27/08, Stefan Reinauer <stepan(a)coresystems.de> wrote: > * Tiago Marques <tiagomnm(a)gmail.com> [080127 16:21]: > > Hi. > > Both failed, tried with two different BIOS chips. > > Flashing with AWDFlash works fine though. > > Had to flash it again in a VIA K8T890 board, which works flawlessly. > > Any ideas, fix? > > What's the problem? > > -- > coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 • Fax: +49 761 7664613 > Email: info(a)coresystems.de • http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg • HRB 7656 > Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 >

12 years, 11 months

[LinuxBIOS] flashrom support for AMD Geode CS5536

by Lane Brooks

Attached is a patch that enables AMD Geode CS5536 chipset support. I have tested it successfully on a MSM800 board from digital logic. It does, however, have a few issues that I would like some feedback on. In my discussions with Marc Jones, Geode systems write protect the BIOS via RCONFs (cache settings similar to MTRRs). Unlocking requires changing MSR 0x1808 top byte to 0x22. Reading and writing to the msr, however, requires instrucitons rdmsr/wrmsr, which are ring0 privileged instructions so only the kernel can do the read/write. So my patch uses the msr kernel module to access these instructions from user space using the /dev/cpu/0/msr device. My questions are: - I do not think this is portable beyond linux. Is that an issue? - My code assumes the msr kernel module is already loaded. Is there a way to force a kernel module to load from the C code? My code does die gracefully with a message reminding them to load the kernel module if things fail. - It seems like there should be a way to revert the msr back after flashing is completed to put the bios back in write protect mode. Is there a cleanup mechanism available? Something like disable_flash... Thanks, Lane Brooks

13 years

[LinuxBIOS] flashrom on ga 2761gxdk

by ron minnich

It now finds the part, and gets ready to program it, but exits instantly without doing anything. I think this is the culprit: void generic_spi_page_program(int block, uint8_t *buf, uint8_t *bios) { if (it8716f_flashport) it8716f_spi_page_program(block, buf, bios); } i.e. the flashport is not set. So, before I dig too far into this, is there some simple thing I should look at to get flashrom working on this board? Also, seems to me it's a pretty serious error if this can not be determined, ... anyone mind if I add an error message? right now it exits with no error, having done no work :-) thanks ron

13 years

[PATCH] CN10K patch, FILO ide discover patch.

by Urbez Santana Roma

Note: for install this patch, you must download the last coreboot SVN, and install first the patch posted by Corey Osgood, that includes CN700/C7 and jetway mainboard. The filo patch is for correct a problem with FILO when tries to find the IDE disk, if more that one IDE interface is on, and no all IDE's are in native Mode. The count of compatibility interfaces are wrong, and not finds the interface that is marked as a IDE 0x0101 or SATA 0x0180 and not all are native, the search of the io base and control, are wrong. If this is not correct sorry :))) If in VT8237R have SATA as an 0101 and the IDE too 0101 class, with this patch, works, because counts corectly the unique non native interface IDE, as the first. NOTE1: in the epia-cn/Config.lb the IDE and SATA are enabled. NOTE2: in epia-cn/auto.c the values of PCI_DEV(0,0x11,0) 0x50 and 0x51 are different, for have IDE and SATA enableds at function enable_mainboard_devices NOTE3: Here is a file base.c that haves a udelay with use of rtdsc NOTE4: another function via_cn_fixup, fixes the use of PCI devices access to the memory. Must be improved, and not use a fixed value. NOTE5: have a change in cn700/raminit.c for configure in CN the memory. NOTE6: vt8237r configures the SATA device as an IDE class 0x0101 must be 0x0180????? Urbez Santana.

13 years, 1 month

Re: [coreboot] [LinuxBIOS] FILO with the USB

by Corey Osgood

Sorry to be a pain, but any progress with this? Thanks, Corey > OK, thank you. > My employer approved the submission. I"ll do it soon. > > On Nov 26, 2007 1:24 AM, Corey Osgood <[EMAIL PROTECTED]> wrote: > > > Fridel Fainshtein wrote: > > > OK, > > > > > > supposing FILO USB works > > > How do I submit the corrections? > > > > > > > http://www.linuxbios.org/Development_Guidelines#How_to_contribute > > > > In short form: > > 1) cd to the filo-0.5/ folder > > 2) svn add * -R (if you've created any new files, be sure to move files > > you don't want added first) > > 3) svn diff > clever_patchname.patch > > 4) edit the patch, add a short description of what the patch does (which > > goes into the svn commit log) and a Signed-off-by: line, per the > > guidelines linked to above. > > > > Thanks! > > -Corey > >

13 years, 2 months

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coreboot February 2008