Hello,
Recently I have decided to give a try to coreboot for first time and
flashed my ThinkPad T420, but a few weeks ago I have swapped the USB
controller on the back, next to the battery, with a FireWire/USB controller
(40GAB5809-G200) from another T420. Nothing special, since some models have
been shipped like this. The controller is no longer accessible on my laptop.
It seems like it may have been detected as an "SD Host Controller" or not
detected at all. I will probably have to remove the chip and compare the
output of lspci and lshw. If nothing has changed, I will probably have to
return the stock BIOS and compare the results again. I have also tried to
load some of the firewire kernel modules manually with modprobe.
The operating systems I have tested so far are Arch Linux and Xubuntu. I am
willing to provide more useful information, boot into a fresh Windows
install, flash the chip again or whatever else. Correct me if I am wrong,
but if I go back to the stock BIOS, the next time I flash, I will have to
disassemble the laptop again and otherwise I must be fine with flashing
internally, right?
Thanks
Dear coreboot community,
I have encountered problem with silicon init on Tiger Lake RVP platform.
I managed to resolve previous issues with memory initialization and now
hitting an error with TCSS init. The FSP asserts on IOM ready check,
which is 0. The configuration has selected CONFIG_USE_INTEL_FSP_MP_INIT
(without MP PPI service).
When the CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI is
selected, then the FSP-S returns smoothly (at least from one of the
phases I guess) and resets after clearing MCEs in coreboot's CPU init:
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
Clearing out pending MCEs
Setting up local APIC...
apic_id: 0x00 done.
Turbo is available but hidden
Turbo is available and visible
CPU #0 initialized
Initializing CPU #2
Initializing CPU #6
Initializing CPU #7
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
Clearing out pending MCEs
Cl (tutaj następuje reset)
Any ideas what may cause these issues? When I clean this up, I will
upstream the DDR4 variant of TGL UP3 RVP.
--
Michał Żygowski
Firmware Engineer
https://3mdeb.com | @3mdeb_com
Hi Paul,
When logs are (almost) disabled the error isn't shown, so if I add the
delay with logs disabled the log output will have almost no difference at
all.
Following are the logs, including a log with Coreboot debug enabled + no
delay. For all logs FSP loglevel is set to NoDebug:
- nvme-err.log : no delay; coreboot debug_level=Error; NVMe error: at the
end of the log is shown the error in the UEFI FW:
ERROR: C40000002:V02010007 I0 93B80004-9FB3-11D4-9A3A-0090273FC14D
7E90A998;
- nvme-ok-delay.log : 20ms delay; coreboot debug_level=Error; NVMe ok;
- nvme-ok.log : no delay; coreboot debug_level=Spew; NVMe ok: the coreboot
log output is enough to make NVMe work properly;
The NVMe is in the root port 00:0b.0, it is shown as 04:00.0
Thanks,
Sumo
On Mon, Aug 16, 2021 at 2:57 PM Paul Menzel <pmenzel(a)molgen.mpg.de> wrote:
> Dear Sumo,
>
>
> Am 16.08.21 um 18:38 schrieb Sumo:
>
> > The NVMe is not detected when serial console logs are disabled, I mean by
> > setting both Coreboot log_level=Error (or less) and FSP
> > PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then
> > further on the device is not listed in the UEFI FW (same issue shown in
> > either CorebootPayloadPkg or UefiPayloadPkg). When Linux boots the device
> > appears normally.
> >
> > The problem is fixed by adding a small delay inside dev_enumerate() - a
> > 20ms delay at the very beginning of the function is enough. I'm wondering
> > if there is a better solution for this, the device is already defined in
> > the devicetree.cb (set as on). Maybe coreboot is too fast and the NVMe is
> > still booting up - or the PCIe link is still training, not sure. Coreboot
> > doesn't retry if the device is not detected right away?
>
> Please share the logs without and with the delay.
>
>
> Kind regards,
>
> Paul
>
Greetings,
I gather that while native ram init is very far along and quite featureful,
it doesn't support ECC. I'm interested to know if there have been past
attempts at it, and what might be required for it to work.
In the unofficial mapping [1] it looks like there's just one register to
turn it on, plus some registers to inject faults for testing. (I
imagine you would also need to clear the memory to avoid lots of errors
from random initial contents, and make sure all the DIMMS are the same type
first)
It certainly "looks" simple (famous last words) so I'm wondering in part if
the unofficial register documentation is just very incomplete? Is there any
intel guidance on ECC out there?
I suppose having ECC is attractive for servers, though I don't think people
would still run ivybridge/sandybridge in production. I'm more interested in
it for the Optiplex 9010 which appears to support ECC on the factory BIOS.
[2] Would make a really nice NAS (external SAS disk shelf) if ECC worked
under coreboot. Would also get bonus points as a daily-driver/home server
from me.
[1]
https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html
Sincerely,
-Matthew Bradley
Hi all,
that we had another case of a missing-device-below-chip in a devicetree
made me write a patch for `sconfig` [1]. Now that it's checking for the
issue, that uncovered a few (31) more cases [2] that need to be fixed
before upstream can benefit from the patch. Please help to fix the
devicetrees.
Note, `sconfig` currently doesn't print the file name of override trees,
e.g. when it says
SCONFIG mainboard/.../devicetree.cb
line 10: end: syntax error
that might as well refer to line 10 in an override tree.
Nico
[1] https://review.coreboot.org/c/coreboot/+/51119
[2] https://qa.coreboot.org/job/coreboot-gerrit/164572/
Failing boards:
board.AMD_BILBY
board.AMD_CEREME
board.AMD_MANDOLIN
board.GETAC_P470
board.GOOGLE_BRYA0
board.GOOGLE_FALCO
board.GOOGLE_PEPPY
board.GOOGLE_WOLF
board.KONTRON_BSL6
board.LENOVO_R500
board.LENOVO_T430S
board.LENOVO_T431S
board.LENOVO_T520
board.LENOVO_T530
board.LENOVO_W530
board.LENOVO_X1
board.LENOVO_X220
board.LENOVO_X220I
board.LENOVO_X220_MRC_BIN
board.LENOVO_X220_OPTION_TABLE_DEBUG_TPM_EXTENDED_CBFS
board.LENOVO_X230
board.LENOVO_X230S
board.LENOVO_X230T
board.LENOVO_X301
board.LENOVO_X60
board.RODA_RK886EX
board.SIEMENS_BOXER26
I tried to update the BIOS through FPT utilities.
FPT.exe -F coreboot.rom
I got the error message
Error 167, protected Range register are set by BIOS...
I checked my SPI_BAR register
SPI_BAR + 4 [15] =0 (FLOCKDN
SPI_BAR + C = 0x0
SPI_BAR + DC [1] = 1 Enable BLE
SPI_BAR + DC [5] = 1 Enable EISS
Is it caused by BLE and EISS?
If yes, how can I change the register to disable BLE and EISS?
--
Steve
Thank for help!
We want to add UART functions on the board,it is superio to use eSPI interface,
How to recognize this interface in thesystem, there is currently modified bootblck.c and devicetree.cb, have otherplaces to modify?
Hicari
Hi!
We developed our CRB motherboard on Intel Atom C3538 (4 core) Denverton_NS processor. Faced with the following problem.
For part of processors with the same SKU and steping (Atom C3538), lapic #4 in devicetree.cb needed (95%), and for the other part lapic #0 (5%).
Intel confirmed that it might be so and that's okay ...
Part of devicetree.cb:
device cpu_cluster 0 on
device lapic 4 on end
end
If we do not specify lapic id correctly in devicetree.cb, freeBSD OS does not BOOT (Unix like).
FreeBSD BOOT log (set lapic #4 in devicetree.cb but need lapic #0):
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
APIC: Found table at 0x7f769420
APIC: Using the MADT enumerator.
MADT: Found CPU APIC ID 0 ACPI ID 0: enabled
SMP: Added CPU 0 (AP)
MADT: Found CPU APIC ID 4 ACPI ID 1: enabled
SMP: Added CPU 4 (AP)
MADT: Found CPU APIC ID 12 ACPI ID 2: enabled
SMP: Added CPU 12 (AP)
MADT: Found CPU APIC ID 16 ACPI ID 3: enabled
SMP: Added CPU 16 (AP)
MADT: Found CPU APIC ID 24 ACPI ID 4: enabled
SMP: Added CPU 24 (AP)
Copyright (c) 1992-2019 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 11.3-RELEASE #0 r349754: Fri Jul 5 04:45:24 UTC 2019
root@releng2.nyi.freebsd.org:/usr/obj/usr/src/sys/GENERIC amd64
FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0)
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
Table 'HPET' at 0x7f7694a0
ACPI: No SRAT table found
PPIM 0: PA=0xa0000, VA=0xffffffff82410000, size=0x10000, mode=0
VT(vga): resolution 640x480
Preloaded elf kernel "/boot/kernel/kernel" at 0xffffffff8226d000.
Calibrating TSC clock ... TSC clock: 2100071708 Hz
CPU: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz (2100.07-MHz K8-class CPU)
Origin="GenuineIntel" Id=0x506f1 Family=0x6 Model=0x5f Stepping=1
Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
Features2=0x4ff8ebbf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,RDRAND>
AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM>
AMD Features2=0x101<LAHF,Prefetch>
Structured Extended Features=0x2294e283<FSGSBASE,TSCADJ,SMEP,ERMS,NFPUSG,MPX,PQE,RDSEED,SMAP,CLFLUSHOPT,PROCTRACE,SHA>
Structured Extended Features3=0xac000400<MD_CLEAR,IBPB,STIBP,ARCH_CAP,SSBD>
XSAVE Features=0xf<XSAVEOPT,XSAVEC,XINUSE,XSAVES>
IA32_ARCH_CAPS=0x69<RDCL_NO,SKIP_L1DFL_VME>
VT-x: Basic Features=0xda0400<SMM,INS/OUTS,TRUE>
Pin-Based Controls=0xff<ExtINT,NMI,VNMI,PreTmr,PostIntr>
Primary Processor Controls=0xfff9fffe<INTWIN,TSCOff,HLT,INVLPG,MWAIT,RDPMC,RDTSC,CR3-LD,CR3-ST,CR8-LD,CR8-ST,TPR,NMIWIN,MOV-DR,IO,IOmap,MTF,MSRmap,MONITOR,PAUSE>
Secondary Processor Controls=0x1d6fff<APIC,EPT,DT,RDTSCP,x2APIC,VPID,WBINVD,UG,APIC-reg,VID,PAUSE-loop,RDRAND,VMFUNC,VMCS,XSAVES>
Exit Controls=0xda0400<PAT-LD,EFER-SV,PTMR-SV>
Entry Controls=0xda0400
EPT Features=0x6334141<XO,PW4,UC,WB,2M,1G,INVEPT,AD,single,all>
VPID Features=0xf01<INVVPID,individual,single,all,single-globals>
TSC: P-state invariant, performance statistics
DTLB: 4k pages, fully associative, 32 entries
Data TLB: 4 KBytes pages, 4-way set associative, 512 entries
Instruction TLB: 4 KByte pages, fully associative, 48 entries
DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
L2 cache: 2048 kbytes, 16-way associative, 64 bytes/line
real memory = 8589934592 (8192 MB)
Physical memory chunk(s):
0x0000000000010000 - 0x000000000009bfff, 573440 bytes (140 pages)
0x0000000000100000 - 0x00000000001fffff, 1048576 bytes (256 pages)
0x0000000002400000 - 0x000000007f74ffff, 2100625408 bytes (512848 pages)
0x0000000100000000 - 0x000000027012efff, 6175256576 bytes (1507631 pages)
avail memory = 8220336128 (7839 MB)
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
Table 'HPET' at 0x7f7694a0
ACPI: No DMAR table found
Event timer "LAPIC" quality 600
ACPI APIC Table: <COREv4 COREBOOT>
WARNING: L1 data cache covers less APIC IDs than a core
0 < 1
Package ID shift: 5
L2 cache ID shift: 2
L1 cache ID shift: 1
Core ID shift: 1
panic: AP #4 (PHY# 0) failed!
cpuid = 0
KDB: stack backtrace:
#0 0xffffffff80b4c4b7 at kdb_backtrace+0x67
#1 0xffffffff80b054ce at vpanic+0x17e
#2 0xffffffff80b05343 at panic+0x43
#3 0xffffffff80f752a4 at native_start_all_aps+0x344
#4 0xffffffff80f74c4f at cpu_mp_start+0x2ef
#5 0xffffffff80b5cb76 at mp_start+0xa6
#6 0xffffffff80aa0b48 at mi_startup+0x118
#7 0xffffffff8031202c at btext+0x2c
Uptime: 1s
Other Linux OS boot but show an incorrect number of cores (5 instead of 4) and offline processor cores appear (see log).
Ubuntu 18.04 LTS (GNU/Linux 4.15.0-20-generic x86_64)
# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 5
On-line CPU(s) list: 0,2-4
Off-line CPU(s) list: 1
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 95
Model name: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz
Stepping: 1
CPU MHz: 2097.502
CPU max MHz: 2100.0000
CPU min MHz: 800.0000
BogoMIPS: 4200.00
Virtualization: VT-x
L1d cache: 24K
L1i cache: 32K
L2 cache: 2048K
NUMA node0 CPU(s): 0,2-4
What can be done in this situation? How to make a universal version of devicetree.cb?
Hi all,
since Immunefi was so kind to put 15k EUR pledge for [1] we host open
call where we will discuss future of KGPE-D16 and its coreboot support.
If you interested about this hardware feel free to join at 15:00 UTC:
https://meet.3mdeb.com/kgpe-d16-refresh
We will post minutes on github.
[1] https://github.com/osresearch/heads/issues/719
--
Piotr Król
Founder and Chief Executive Officer
GPG: B2EE71E967AA9E4C
https://3mdeb.com | @3mdeb_com