Greetings,
I gather that while native ram init is very far along and quite featureful, it doesn't support ECC. I'm interested to know if there have been past attempts at it, and what might be required for it to work.
In the unofficial mapping [1] it looks like there's just one register to turn it on, plus some registers to inject faults for testing. (I imagine you would also need to clear the memory to avoid lots of errors from random initial contents, and make sure all the DIMMS are the same type first)
It certainly "looks" simple (famous last words) so I'm wondering in part if the unofficial register documentation is just very incomplete? Is there any intel guidance on ECC out there?
I suppose having ECC is attractive for servers, though I don't think people would still run ivybridge/sandybridge in production. I'm more interested in it for the Optiplex 9010 which appears to support ECC on the factory BIOS. [2] Would make a really nice NAS (external SAS disk shelf) if ECC worked under coreboot. Would also get bonus points as a daily-driver/home server from me.
[1] https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html
Sincerely, -Matthew Bradley
Hi Matt, the ECC support on Sandy/Ivy Bridge should be fully working since Aug 2020, to be exact, commit b5fa9c8200423beb660403b6656fa8fd5d7edc31 . By default it is automatically enabled if the hostbridge and all DIMMs are ECC capable. It was tested on HP Z220 workstation PC.
Regards, Patrick Rudolph B.Sc. Electrical Engineering System Firmware Developer
9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph@9elements.com Phone: +49 234 68 94 188
Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Eray Basar
Datenschutzhinweise nach Art. 13 DSGVO
On Fri, Aug 13, 2021 at 9:46 PM Matt B matthewwbradley6@gmail.com wrote:
Greetings,
I gather that while native ram init is very far along and quite featureful, it doesn't support ECC. I'm interested to know if there have been past attempts at it, and what might be required for it to work.
In the unofficial mapping [1] it looks like there's just one register to turn it on, plus some registers to inject faults for testing. (I imagine you would also need to clear the memory to avoid lots of errors from random initial contents, and make sure all the DIMMS are the same type first)
It certainly "looks" simple (famous last words) so I'm wondering in part if the unofficial register documentation is just very incomplete? Is there any intel guidance on ECC out there?
I suppose having ECC is attractive for servers, though I don't think people would still run ivybridge/sandybridge in production. I'm more interested in it for the Optiplex 9010 which appears to support ECC on the factory BIOS. [2] Would make a really nice NAS (external SAS disk shelf) if ECC worked under coreboot. Would also get bonus points as a daily-driver/home server from me.
[1] https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html
Sincerely, -Matthew Bradley
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hello Patrick,
Thank you very much for your reply!
From subsequent investigation it appears that the ECC lines of the 7010 SFF are indeed connected and Xeon CPUs can be made to work under the stock BIOS (and presumably under coreboot).
A minor side question I have: does the chipset on intel ivybridge platforms play a role in ECC support? It appears to me that the only components involved are the CPU, RAM DIMMs, and BIOS.
Sincerely, -Matthew Bradley
On Sat, Aug 14, 2021 at 12:24 PM Patrick Rudolph < patrick.rudolph@9elements.com> wrote:
Hi Matt, the ECC support on Sandy/Ivy Bridge should be fully working since Aug 2020, to be exact, commit b5fa9c8200423beb660403b6656fa8fd5d7edc31 . By default it is automatically enabled if the hostbridge and all DIMMs are ECC capable. It was tested on HP Z220 workstation PC.
Regards, Patrick Rudolph B.Sc. Electrical Engineering System Firmware Developer
9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph@9elements.com Phone: +49 234 68 94 188
Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Eray Basar
Datenschutzhinweise nach Art. 13 DSGVO
On Fri, Aug 13, 2021 at 9:46 PM Matt B matthewwbradley6@gmail.com wrote:
Greetings,
I gather that while native ram init is very far along and quite
featureful, it doesn't support ECC. I'm interested to know if there have been past attempts at it, and what might be required for it to work.
In the unofficial mapping [1] it looks like there's just one register to
turn it on, plus some registers to inject faults for testing. (I imagine you would also need to clear the memory to avoid lots of errors from random initial contents, and make sure all the DIMMS are the same type first)
It certainly "looks" simple (famous last words) so I'm wondering in part
if the unofficial register documentation is just very incomplete? Is there any intel guidance on ECC out there?
I suppose having ECC is attractive for servers, though I don't think
people would still run ivybridge/sandybridge in production. I'm more interested in it for the Optiplex 9010 which appears to support ECC on the factory BIOS. [2] Would make a really nice NAS (external SAS disk shelf) if ECC worked under coreboot. Would also get bonus points as a daily-driver/home server from me.
[1]
https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html
Sincerely, -Matthew Bradley
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi Matt, For ECC support you only need compatible CPU, RAM DIMMs, the mainboard and of course the firmware. In addition some features on Intel's x86 platforms can be toggled by hard- or soft straps. So yes, the chipset (or it's configuration) might play a role in ECC, but I can't say for sure. The best place to look for this information would be the PDG and BWG which is available under NDA.
Kind Regards, Patrick Rudolph
Patrick Rudolph B.Sc. Electrical Engineering System Firmware Developer
9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph@9elements.com Phone: +49 234 68 94 188
Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Eray Basar
Datenschutzhinweise nach Art. 13 DSGVO
On Tue, Aug 31, 2021 at 11:46 PM Matt B matthewwbradley6@gmail.com wrote:
Hello Patrick,
Thank you very much for your reply!
From subsequent investigation it appears that the ECC lines of the 7010 SFF are indeed connected and Xeon CPUs can be made to work under the stock BIOS (and presumably under coreboot).
A minor side question I have: does the chipset on intel ivybridge platforms play a role in ECC support? It appears to me that the only components involved are the CPU, RAM DIMMs, and BIOS.
Sincerely, -Matthew Bradley
On Sat, Aug 14, 2021 at 12:24 PM Patrick Rudolph patrick.rudolph@9elements.com wrote:
Hi Matt, the ECC support on Sandy/Ivy Bridge should be fully working since Aug 2020, to be exact, commit b5fa9c8200423beb660403b6656fa8fd5d7edc31 . By default it is automatically enabled if the hostbridge and all DIMMs are ECC capable. It was tested on HP Z220 workstation PC.
Regards, Patrick Rudolph B.Sc. Electrical Engineering System Firmware Developer
9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: patrick.rudolph@9elements.com Phone: +49 234 68 94 188
Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Eray Basar
Datenschutzhinweise nach Art. 13 DSGVO
On Fri, Aug 13, 2021 at 9:46 PM Matt B matthewwbradley6@gmail.com wrote:
Greetings,
I gather that while native ram init is very far along and quite featureful, it doesn't support ECC. I'm interested to know if there have been past attempts at it, and what might be required for it to work.
In the unofficial mapping [1] it looks like there's just one register to turn it on, plus some registers to inject faults for testing. (I imagine you would also need to clear the memory to avoid lots of errors from random initial contents, and make sure all the DIMMS are the same type first)
It certainly "looks" simple (famous last words) so I'm wondering in part if the unofficial register documentation is just very incomplete? Is there any intel guidance on ECC out there?
I suppose having ECC is attractive for servers, though I don't think people would still run ivybridge/sandybridge in production. I'm more interested in it for the Optiplex 9010 which appears to support ECC on the factory BIOS. [2] Would make a really nice NAS (external SAS disk shelf) if ECC worked under coreboot. Would also get bonus points as a daily-driver/home server from me.
[1] https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html
Sincerely, -Matthew Bradley
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi Matthew,
On 8/31/21 11:46 PM, Matt B wrote:
Hello Patrick,
Thank you very much for your reply!
From subsequent investigation it appears that the ECC lines of the 7010 SFF are indeed connected and Xeon CPUs can be made to work under the stock BIOS (and presumably under coreboot).
A minor side question I have: does the chipset on intel ivybridge platforms play a role in ECC support? It appears to me that the only components involved are the CPU, RAM DIMMs, and BIOS.
I have some good news for you. 1) I can assure that ECC lines are connected between CPU and DIMMs on 7010/9010 DT schematics 2) I have successfully launched my OptiPlex 9010 SFF with a Xeon E3-1275 v2 and 4x 4GB UDIMMs non-ECC.
Unfortunately I haven't been able to launch the machine with ECC RDIMMs due to I/O latency overflow in the native raminit. Probably it will only work with unregistered DIMMs (which I will probably try soon) because registers on the DIMMs introduce higher latency. Maybe Patrick can shed some light on this raminit matter?
Best regards,
Would an Ivybridge CPU even be expected to work with RDIMMs? Was this something anticipated when native raminit was written?
-Matt
On Mon, Sep 6, 2021 at 6:00 PM Michał Żygowski michal.zygowski@3mdeb.com wrote:
Hi Matthew,
On 8/31/21 11:46 PM, Matt B wrote:
Hello Patrick,
Thank you very much for your reply!
From subsequent investigation it appears that the ECC lines of the 7010 SFF are indeed connected and Xeon CPUs can be made to work under the stock BIOS (and presumably under coreboot).
A minor side question I have: does the chipset on intel ivybridge platforms play a role in ECC support? It appears to me that the only components involved are the CPU, RAM DIMMs, and BIOS.
I have some good news for you.
- I can assure that ECC lines are connected between CPU and DIMMs on
7010/9010 DT schematics 2) I have successfully launched my OptiPlex 9010 SFF with a Xeon E3-1275 v2 and 4x 4GB UDIMMs non-ECC.
Unfortunately I haven't been able to launch the machine with ECC RDIMMs due to I/O latency overflow in the native raminit. Probably it will only work with unregistered DIMMs (which I will probably try soon) because registers on the DIMMs introduce higher latency. Maybe Patrick can shed some light on this raminit matter?
Best regards,
Michał Żygowski Firmware Engineer GPG: 6B5BA214D21FCEB2 https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi Matt, list,
On Wed, Sep 8, 2021 at 3:29 PM Matt B matthewwbradley6@gmail.com wrote:
Would an Ivybridge CPU even be expected to work with RDIMMs? Was this something anticipated when native raminit was written?
I don't think so. RDIMMs have higher latencies and very likely exceed the maximum value that can be programmed into the chipset's timing registers. Native raminit doesn't account for RDIMMs at all.
-Matt
Best regards, Angel
Hello,
Thanks Angel. To clarify, the part of the chipset you're referring to would be the memory controller on the CPU, yes? Not somewhere on the southbridge?
Thanks, -Matt
On Wed, Sep 8, 2021 at 11:33 AM Angel Pons th3fanbus@gmail.com wrote:
Hi Matt, list,
On Wed, Sep 8, 2021 at 3:29 PM Matt B matthewwbradley6@gmail.com wrote:
Would an Ivybridge CPU even be expected to work with RDIMMs? Was this
something anticipated when native raminit was written?
I don't think so. RDIMMs have higher latencies and very likely exceed the maximum value that can be programmed into the chipset's timing registers. Native raminit doesn't account for RDIMMs at all.
-Matt
Best regards, Angel
-
Angel Pons -
Matt B -
Michał Żygowski -
Patrick Rudolph